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tcg/ppc: enable dynamic TLB sizing
[qemu.git] / tcg / ppc / tcg-target.inc.c
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810260a8 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
53c89efd
RH		 25#include "elf.h"
26#include "tcg-pool.inc.c"
27
ffcfbece
RH		 28#if defined _CALL_DARWIN || defined __APPLE__
29#define TCG_TARGET_CALL_DARWIN
30#endif
7f25c469
RH		 31#ifdef _CALL_SYSV
32# define TCG_TARGET_CALL_ALIGN_ARGS 1
33#endif
ffcfbece 34
dfca1778
RH		 35/* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
39#ifdef _CALL_AIX
40# define TCG_REG_TMP1 TCG_REG_R2
41#else
42# define TCG_REG_TMP1 TCG_REG_R12
43#endif
44
5964fca8
RH		 45#define TCG_REG_TB TCG_REG_R31
46#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
a84ac4cb 47
de3d636d
RH		 48/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
49#define SZP ((int)sizeof(void *))
50
4c3831a0
RH		 51/* Shorthand for size of a register. */
52#define SZR (TCG_TARGET_REG_BITS / 8)
53
3d582c61
RH		 54#define TCG_CT_CONST_S16 0x100
55#define TCG_CT_CONST_U16 0x200
56#define TCG_CT_CONST_S32 0x400
57#define TCG_CT_CONST_U32 0x800
58#define TCG_CT_CONST_ZERO 0x1000
6c858762 59#define TCG_CT_CONST_MONE 0x2000
d0b07481 60#define TCG_CT_CONST_WSZ 0x4000
fe6f943f 61
e083c4a2 62static tcg_insn_unit *tb_ret_addr;
810260a8 63
33e75fb9 64bool have_isa_2_06;
d0b07481
RH		 65bool have_isa_3_00;
66
1e6e9aca
RH		 67#define HAVE_ISA_2_06 have_isa_2_06
68#define HAVE_ISEL have_isa_2_06
49d9870a 69
4cbea598 70#ifndef CONFIG_SOFTMMU
f6548c0a 71#define TCG_GUEST_BASE_REG 30
f6548c0a 72#endif
73
8d8fdbae 74#ifdef CONFIG_DEBUG_TCG
810260a8 75static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
76 "r0",
77 "r1",
98926b0a 78 "r2",
810260a8 79 "r3",
80 "r4",
81 "r5",
82 "r6",
83 "r7",
84 "r8",
85 "r9",
86 "r10",
87 "r11",
88 "r12",
89 "r13",
90 "r14",
91 "r15",
92 "r16",
93 "r17",
94 "r18",
95 "r19",
96 "r20",
97 "r21",
98 "r22",
99 "r23",
100 "r24",
101 "r25",
102 "r26",
103 "r27",
104 "r28",
105 "r29",
106 "r30",
107 "r31"
108};
d4a9eb1f 109#endif
810260a8 110
111static const int tcg_target_reg_alloc_order[] = {
5e1702b0 112 TCG_REG_R14, /* call saved registers */
810260a8 113 TCG_REG_R15,
114 TCG_REG_R16,
115 TCG_REG_R17,
116 TCG_REG_R18,
117 TCG_REG_R19,
118 TCG_REG_R20,
119 TCG_REG_R21,
120 TCG_REG_R22,
121 TCG_REG_R23,
5e1702b0
RH		 122 TCG_REG_R24,
123 TCG_REG_R25,
124 TCG_REG_R26,
125 TCG_REG_R27,
810260a8 126 TCG_REG_R28,
127 TCG_REG_R29,
128 TCG_REG_R30,
129 TCG_REG_R31,
5e1702b0
RH		 130 TCG_REG_R12, /* call clobbered, non-arguments */
131 TCG_REG_R11,
dfca1778
RH		 132 TCG_REG_R2,
133 TCG_REG_R13,
5e1702b0 134 TCG_REG_R10, /* call clobbered, arguments */
810260a8 135 TCG_REG_R9,
5e1702b0
RH		 136 TCG_REG_R8,
137 TCG_REG_R7,
138 TCG_REG_R6,
139 TCG_REG_R5,
140 TCG_REG_R4,
141 TCG_REG_R3,
810260a8 142};
143
144static const int tcg_target_call_iarg_regs[] = {
145 TCG_REG_R3,
146 TCG_REG_R4,
147 TCG_REG_R5,
148 TCG_REG_R6,
149 TCG_REG_R7,
150 TCG_REG_R8,
151 TCG_REG_R9,
152 TCG_REG_R10
153};
154
be9c4183 155static const int tcg_target_call_oarg_regs[] = {
dfca1778
RH		 156 TCG_REG_R3,
157 TCG_REG_R4
810260a8 158};
159
160static const int tcg_target_callee_save_regs[] = {
dfca1778 161#ifdef TCG_TARGET_CALL_DARWIN
5d7ff5bb
AF		 162 TCG_REG_R11,
163#endif
810260a8 164 TCG_REG_R14,
165 TCG_REG_R15,
166 TCG_REG_R16,
167 TCG_REG_R17,
168 TCG_REG_R18,
169 TCG_REG_R19,
170 TCG_REG_R20,
171 TCG_REG_R21,
172 TCG_REG_R22,
173 TCG_REG_R23,
095271d4 174 TCG_REG_R24,
175 TCG_REG_R25,
176 TCG_REG_R26,
cea5f9a2 177 TCG_REG_R27, /* currently used for the global env */
810260a8 178 TCG_REG_R28,
179 TCG_REG_R29,
180 TCG_REG_R30,
181 TCG_REG_R31
182};
183
b0940da0
RH		 184static inline bool in_range_b(tcg_target_long target)
185{
186 return target == sextract64(target, 0, 26);
187}
188
e083c4a2 189static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 190{
e083c4a2 191 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 192 tcg_debug_assert(in_range_b(disp));
810260a8 193 return disp & 0x3fffffc;
194}
195
d5132903 196static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 197{
d5132903
RH		 198 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
199 if (in_range_b(disp)) {
200 *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc);
201 return true;
202 }
203 return false;
810260a8 204}
205
e083c4a2 206static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 207{
e083c4a2 208 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
eabb7b91 209 tcg_debug_assert(disp == (int16_t) disp);
810260a8 210 return disp & 0xfffc;
211}
212
d5132903 213static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
810260a8 214{
d5132903
RH		 215 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
216 if (disp == (int16_t) disp) {
217 *pc = (*pc & ~0xfffc) | (disp & 0xfffc);
218 return true;
219 }
220 return false;
810260a8 221}
222
810260a8 223/* parse target specific constraints */
069ea736
RH		 224static const char *target_parse_constraint(TCGArgConstraint *ct,
225 const char *ct_str, TCGType type)
810260a8 226{
069ea736 227 switch (*ct_str++) {
810260a8 228 case 'A': case 'B': case 'C': case 'D':
229 ct->ct |= TCG_CT_REG;
541dd4ce 230 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
810260a8 231 break;
232 case 'r':
233 ct->ct |= TCG_CT_REG;
f46934df 234 ct->u.regs = 0xffffffff;
810260a8 235 break;
236 case 'L': /* qemu_ld constraint */
237 ct->ct |= TCG_CT_REG;
f46934df 238 ct->u.regs = 0xffffffff;
541dd4ce 239 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 240#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
242 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
735ee40d 243#endif
810260a8 244 break;
c070355d 245 case 'S': /* qemu_st constraint */
810260a8 246 ct->ct |= TCG_CT_REG;
f46934df 247 ct->u.regs = 0xffffffff;
541dd4ce 248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
735ee40d 249#ifdef CONFIG_SOFTMMU
541dd4ce
RH		 250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
735ee40d 253#endif
810260a8 254 break;
3d582c61
RH		 255 case 'I':
256 ct->ct |= TCG_CT_CONST_S16;
257 break;
258 case 'J':
259 ct->ct |= TCG_CT_CONST_U16;
260 break;
6c858762
RH		 261 case 'M':
262 ct->ct |= TCG_CT_CONST_MONE;
263 break;
3d582c61
RH		 264 case 'T':
265 ct->ct |= TCG_CT_CONST_S32;
266 break;
267 case 'U':
fe6f943f 268 ct->ct |= TCG_CT_CONST_U32;
269 break;
d0b07481
RH		 270 case 'W':
271 ct->ct |= TCG_CT_CONST_WSZ;
272 break;
3d582c61
RH		 273 case 'Z':
274 ct->ct |= TCG_CT_CONST_ZERO;
275 break;
810260a8 276 default:
069ea736 277 return NULL;
810260a8 278 }
069ea736 279 return ct_str;
810260a8 280}
281
282/* test if a constant matches the constraint */
f6c6afc1 283static int tcg_target_const_match(tcg_target_long val, TCGType type,
541dd4ce 284 const TCGArgConstraint *arg_ct)
810260a8 285{
3d582c61
RH		 286 int ct = arg_ct->ct;
287 if (ct & TCG_CT_CONST) {
288 return 1;
1194dcba
RH		 289 }
290
291 /* The only 32-bit constraint we use aside from
292 TCG_CT_CONST is TCG_CT_CONST_S16. */
293 if (type == TCG_TYPE_I32) {
294 val = (int32_t)val;
295 }
296
297 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
3d582c61
RH		 298 return 1;
299 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
810260a8 300 return 1;
3d582c61 301 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
fe6f943f 302 return 1;
3d582c61
RH		 303 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
304 return 1;
305 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
306 return 1;
6c858762
RH		 307 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
308 return 1;
d0b07481
RH		 309 } else if ((ct & TCG_CT_CONST_WSZ)
310 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
311 return 1;
3d582c61 312 }
810260a8 313 return 0;
314}
315
316#define OPCD(opc) ((opc)<<26)
317#define XO19(opc) (OPCD(19)|((opc)<<1))
8a94cfb0
AB		 318#define MD30(opc) (OPCD(30)|((opc)<<2))
319#define MDS30(opc) (OPCD(30)|((opc)<<1))
810260a8 320#define XO31(opc) (OPCD(31)|((opc)<<1))
321#define XO58(opc) (OPCD(58)|(opc))
322#define XO62(opc) (OPCD(62)|(opc))
323
324#define B OPCD( 18)
325#define BC OPCD( 16)
326#define LBZ OPCD( 34)
327#define LHZ OPCD( 40)
328#define LHA OPCD( 42)
329#define LWZ OPCD( 32)
644f591a 330#define LWZUX XO31( 55)
810260a8 331#define STB OPCD( 38)
332#define STH OPCD( 44)
333#define STW OPCD( 36)
334
335#define STD XO62( 0)
336#define STDU XO62( 1)
337#define STDX XO31(149)
338
339#define LD XO58( 0)
340#define LDX XO31( 21)
341#define LDU XO58( 1)
644f591a 342#define LDUX XO31( 53)
301f6d90 343#define LWA XO58( 2)
810260a8 344#define LWAX XO31(341)
345
1cd62ae9 346#define ADDIC OPCD( 12)
810260a8 347#define ADDI OPCD( 14)
348#define ADDIS OPCD( 15)
349#define ORI OPCD( 24)
350#define ORIS OPCD( 25)
351#define XORI OPCD( 26)
352#define XORIS OPCD( 27)
353#define ANDI OPCD( 28)
354#define ANDIS OPCD( 29)
355#define MULLI OPCD( 7)
356#define CMPLI OPCD( 10)
357#define CMPI OPCD( 11)
148bdd23 358#define SUBFIC OPCD( 8)
810260a8 359
360#define LWZU OPCD( 33)
361#define STWU OPCD( 37)
362
313d91c7 363#define RLWIMI OPCD( 20)
810260a8 364#define RLWINM OPCD( 21)
313d91c7 365#define RLWNM OPCD( 23)
810260a8 366
8a94cfb0
AB		 367#define RLDICL MD30( 0)
368#define RLDICR MD30( 1)
369#define RLDIMI MD30( 3)
370#define RLDCL MDS30( 8)
810260a8 371
372#define BCLR XO19( 16)
373#define BCCTR XO19(528)
374#define CRAND XO19(257)
375#define CRANDC XO19(129)
376#define CRNAND XO19(225)
377#define CROR XO19(449)
1cd62ae9 378#define CRNOR XO19( 33)
810260a8 379
380#define EXTSB XO31(954)
381#define EXTSH XO31(922)
382#define EXTSW XO31(986)
383#define ADD XO31(266)
384#define ADDE XO31(138)
6c858762
RH		 385#define ADDME XO31(234)
386#define ADDZE XO31(202)
810260a8 387#define ADDC XO31( 10)
388#define AND XO31( 28)
389#define SUBF XO31( 40)
390#define SUBFC XO31( 8)
391#define SUBFE XO31(136)
6c858762
RH		 392#define SUBFME XO31(232)
393#define SUBFZE XO31(200)
810260a8 394#define OR XO31(444)
395#define XOR XO31(316)
396#define MULLW XO31(235)
8fa391a0 397#define MULHW XO31( 75)
810260a8 398#define MULHWU XO31( 11)
399#define DIVW XO31(491)
400#define DIVWU XO31(459)
401#define CMP XO31( 0)
402#define CMPL XO31( 32)
403#define LHBRX XO31(790)
404#define LWBRX XO31(534)
49d9870a 405#define LDBRX XO31(532)
810260a8 406#define STHBRX XO31(918)
407#define STWBRX XO31(662)
49d9870a 408#define STDBRX XO31(660)
810260a8 409#define MFSPR XO31(339)
410#define MTSPR XO31(467)
411#define SRAWI XO31(824)
412#define NEG XO31(104)
1cd62ae9 413#define MFCR XO31( 19)
6995a4a0 414#define MFOCRF (MFCR | (1u << 20))
157f2662 415#define NOR XO31(124)
1cd62ae9 416#define CNTLZW XO31( 26)
417#define CNTLZD XO31( 58)
d0b07481
RH		 418#define CNTTZW XO31(538)
419#define CNTTZD XO31(570)
33e75fb9
RH		 420#define CNTPOPW XO31(378)
421#define CNTPOPD XO31(506)
ce1010d6
RH		 422#define ANDC XO31( 60)
423#define ORC XO31(412)
424#define EQV XO31(284)
425#define NAND XO31(476)
70fac59a 426#define ISEL XO31( 15)
810260a8 427
428#define MULLD XO31(233)
429#define MULHD XO31( 73)
430#define MULHDU XO31( 9)
431#define DIVD XO31(489)
432#define DIVDU XO31(457)
433
434#define LBZX XO31( 87)
4f4a67ae 435#define LHZX XO31(279)
810260a8 436#define LHAX XO31(343)
437#define LWZX XO31( 23)
438#define STBX XO31(215)
439#define STHX XO31(407)
440#define STWX XO31(151)
441
7b4af5ee
PK		 442#define EIEIO XO31(854)
443#define HWSYNC XO31(598)
444#define LWSYNC (HWSYNC | (1u << 21))
445
541dd4ce 446#define SPR(a, b) ((((a)<<5)|(b))<<11)
810260a8 447#define LR SPR(8, 0)
448#define CTR SPR(9, 0)
449
450#define SLW XO31( 24)
451#define SRW XO31(536)
452#define SRAW XO31(792)
453
454#define SLD XO31( 27)
455#define SRD XO31(539)
456#define SRAD XO31(794)
fe6f943f 457#define SRADI XO31(413<<1)
810260a8 458
810260a8 459#define TW XO31( 4)
541dd4ce 460#define TRAP (TW | TO(31))
810260a8 461
a84ac4cb
RH		 462#define NOP ORI /* ori 0,0,0 */
463
810260a8 464#define RT(r) ((r)<<21)
465#define RS(r) ((r)<<21)
466#define RA(r) ((r)<<16)
467#define RB(r) ((r)<<11)
468#define TO(t) ((t)<<21)
469#define SH(s) ((s)<<11)
470#define MB(b) ((b)<<6)
471#define ME(e) ((e)<<1)
472#define BO(o) ((o)<<21)
473#define MB64(b) ((b)<<5)
6995a4a0 474#define FXM(b) (1 << (19 - (b)))
810260a8 475
476#define LK 1
477
2fd8eddc
RH		 478#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
479#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
480#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
481#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
810260a8 482
483#define BF(n) ((n)<<23)
484#define BI(n, c) (((c)+((n)*4))<<16)
485#define BT(n, c) (((c)+((n)*4))<<21)
486#define BA(n, c) (((c)+((n)*4))<<16)
487#define BB(n, c) (((c)+((n)*4))<<11)
70fac59a 488#define BC_(n, c) (((c)+((n)*4))<<6)
810260a8 489
541dd4ce
RH		 490#define BO_COND_TRUE BO(12)
491#define BO_COND_FALSE BO( 4)
492#define BO_ALWAYS BO(20)
810260a8 493
494enum {
495 CR_LT,
496 CR_GT,
497 CR_EQ,
498 CR_SO
499};
500
0aed257f 501static const uint32_t tcg_to_bc[] = {
541dd4ce
RH		 502 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
503 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
504 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
505 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
506 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
507 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
508 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
509 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
510 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
511 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
810260a8 512};
513
70fac59a
RH		 514/* The low bit here is set if the RA and RB fields must be inverted. */
515static const uint32_t tcg_to_isel[] = {
516 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
517 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
518 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
519 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
520 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
521 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
522 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
523 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
524 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
525 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
526};
527
6ac17786 528static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
030ffe39
RH		 529 intptr_t value, intptr_t addend)
530{
531 tcg_insn_unit *target;
532 tcg_insn_unit old;
533
534 value += addend;
535 target = (tcg_insn_unit *)value;
536
537 switch (type) {
538 case R_PPC_REL14:
d5132903 539 return reloc_pc14(code_ptr, target);
030ffe39 540 case R_PPC_REL24:
d5132903 541 return reloc_pc24(code_ptr, target);
030ffe39
RH		 542 case R_PPC_ADDR16:
543 /* We are abusing this relocation type. This points to a pair
544 of insns, addis + load. If the displacement is small, we
545 can nop out the addis. */
546 if (value == (int16_t)value) {
547 code_ptr[0] = NOP;
548 old = deposit32(code_ptr[1], 0, 16, value);
549 code_ptr[1] = deposit32(old, 16, 5, TCG_REG_TB);
550 } else {
551 int16_t lo = value;
552 int hi = value - lo;
d5132903
RH		 553 if (hi + lo != value) {
554 return false;
555 }
030ffe39
RH		 556 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
557 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
558 }
559 break;
560 default:
561 g_assert_not_reached();
562 }
6ac17786 563 return true;
030ffe39
RH		 564}
565
a84ac4cb
RH		 566static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
567 TCGReg base, tcg_target_long offset);
568
796f1a68 569static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
810260a8 570{
796f1a68 571 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
f8b84129
RH		 572 if (ret != arg) {
573 tcg_out32(s, OR | SAB(arg, ret, arg));
574 }
810260a8 575}
576
aceac8d6
RH		 577static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
578 int sh, int mb)
810260a8 579{
eabb7b91 580 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
541dd4ce
RH		 581 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
582 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
583 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
810260a8 584}
585
9e555b73
RH		 586static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
587 int sh, int mb, int me)
588{
589 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
590}
591
6e5e0602
RH		 592static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
593{
594 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
595}
596
a757e1ee
RH		 597static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
598{
599 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
600}
601
0a9564b9
RH		 602static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
603{
604 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
605}
606
a757e1ee
RH		 607static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
608{
609 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
610}
611
5e916c28
RH		 612static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
613{
614 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
615}
616
77bfc7c0
RH		 617/* Emit a move into ret of arg, if it can be done in one insn. */
618static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
619{
620 if (arg == (int16_t)arg) {
621 tcg_out32(s, ADDI | TAI(ret, 0, arg));
622 return true;
623 }
624 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
625 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
626 return true;
627 }
628 return false;
629}
630
5964fca8
RH		 631static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
632 tcg_target_long arg, bool in_prologue)
810260a8 633{
5964fca8 634 intptr_t tb_diff;
77bfc7c0
RH		 635 tcg_target_long tmp;
636 int shift;
5964fca8
RH		 637
638 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
639
640 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
641 arg = (int32_t)arg;
642 }
643
644 /* Load 16-bit immediates with one insn. */
77bfc7c0 645 if (tcg_out_movi_one(s, ret, arg)) {
5964fca8
RH		 646 return;
647 }
648
649 /* Load addresses within the TB with one insn. */
650 tb_diff = arg - (intptr_t)s->code_gen_ptr;
651 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
652 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
653 return;
654 }
655
77bfc7c0
RH		 656 /* Load 32-bit immediates with two insns. Note that we've already
657 eliminated bare ADDIS, so we know both insns are required. */
5964fca8 658 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
2fd8eddc 659 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
77bfc7c0 660 tcg_out32(s, ORI | SAI(ret, ret, arg));
5964fca8 661 return;
810260a8 662 }
5964fca8 663 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
421233a1
RH		 664 tcg_out32(s, ADDI | TAI(ret, 0, arg));
665 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
5964fca8
RH		 666 return;
667 }
a84ac4cb 668
77bfc7c0
RH		 669 /* Load masked 16-bit value. */
670 if (arg > 0 && (arg & 0x8000)) {
671 tmp = arg | 0x7fff;
672 if ((tmp & (tmp + 1)) == 0) {
673 int mb = clz64(tmp + 1) + 1;
674 tcg_out32(s, ADDI | TAI(ret, 0, arg));
675 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
676 return;
677 }
678 }
679
680 /* Load common masks with 2 insns. */
681 shift = ctz64(arg);
682 tmp = arg >> shift;
683 if (tmp == (int16_t)tmp) {
684 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
685 tcg_out_shli64(s, ret, ret, shift);
686 return;
687 }
688 shift = clz64(arg);
689 if (tcg_out_movi_one(s, ret, arg << shift)) {
690 tcg_out_shri64(s, ret, ret, shift);
691 return;
692 }
693
5964fca8
RH		 694 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
695 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
696 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
697 return;
698 }
a84ac4cb 699
53c89efd
RH		 700 /* Use the constant pool, if possible. */
701 if (!in_prologue && USE_REG_TB) {
702 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
703 -(intptr_t)s->code_gen_ptr);
030ffe39
RH		 704 tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0));
705 tcg_out32(s, LD | TAI(ret, ret, 0));
53c89efd
RH		 706 return;
707 }
708
77bfc7c0
RH		 709 tmp = arg >> 31 >> 1;
710 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
711 if (tmp) {
5964fca8 712 tcg_out_shli64(s, ret, ret, 32);
810260a8 713 }
5964fca8
RH		 714 if (arg & 0xffff0000) {
715 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
716 }
717 if (arg & 0xffff) {
718 tcg_out32(s, ORI | SAI(ret, ret, arg));
719 }
720}
721
722static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
723 tcg_target_long arg)
724{
725 tcg_out_movi_int(s, type, ret, arg, false);
810260a8 726}
727
637af30c 728static bool mask_operand(uint32_t c, int *mb, int *me)
a9249dff
RH		 729{
730 uint32_t lsb, test;
731
732 /* Accept a bit pattern like:
733 0....01....1
734 1....10....0
735 0..01..10..0
736 Keep track of the transitions. */
737 if (c == 0 || c == -1) {
738 return false;
739 }
740 test = c;
741 lsb = test & -test;
742 test += lsb;
743 if (test & (test - 1)) {
744 return false;
745 }
746
747 *me = clz32(lsb);
748 *mb = test ? clz32(test & -test) + 1 : 0;
749 return true;
750}
751
637af30c
RH		 752static bool mask64_operand(uint64_t c, int *mb, int *me)
753{
754 uint64_t lsb;
755
756 if (c == 0) {
757 return false;
758 }
759
760 lsb = c & -c;
761 /* Accept 1..10..0. */
762 if (c == -lsb) {
763 *mb = 0;
764 *me = clz64(lsb);
765 return true;
766 }
767 /* Accept 0..01..1. */
768 if (lsb == 1 && (c & (c + 1)) == 0) {
769 *mb = clz64(c + 1) + 1;
770 *me = 63;
771 return true;
772 }
773 return false;
774}
775
a9249dff
RH		 776static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
777{
778 int mb, me;
779
1e1df962
RH		 780 if (mask_operand(c, &mb, &me)) {
781 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
782 } else if ((c & 0xffff) == c) {
a9249dff
RH		 783 tcg_out32(s, ANDI | SAI(src, dst, c));
784 return;
785 } else if ((c & 0xffff0000) == c) {
786 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
787 return;
a9249dff 788 } else {
8327a470
RH		 789 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
790 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
a9249dff
RH		 791 }
792}
793
637af30c
RH		 794static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
795{
796 int mb, me;
797
eabb7b91 798 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1e1df962 799 if (mask64_operand(c, &mb, &me)) {
637af30c
RH		 800 if (mb == 0) {
801 tcg_out_rld(s, RLDICR, dst, src, 0, me);
802 } else {
803 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
804 }
1e1df962
RH		 805 } else if ((c & 0xffff) == c) {
806 tcg_out32(s, ANDI | SAI(src, dst, c));
807 return;
808 } else if ((c & 0xffff0000) == c) {
809 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
810 return;
637af30c 811 } else {
8327a470
RH		 812 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
813 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
637af30c
RH		 814 }
815}
816
dce74c57
RH		 817static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
818 int op_lo, int op_hi)
819{
820 if (c >> 16) {
821 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
822 src = dst;
823 }
824 if (c & 0xffff) {
825 tcg_out32(s, op_lo | SAI(src, dst, c));
826 src = dst;
827 }
828}
829
830static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
831{
832 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
833}
834
835static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
836{
837 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
838}
839
e083c4a2 840static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
5d7ff5bb 841{
e083c4a2 842 ptrdiff_t disp = tcg_pcrel_diff(s, target);
b0940da0 843 if (in_range_b(disp)) {
541dd4ce
RH		 844 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
845 } else {
de3d636d 846 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
8327a470 847 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
541dd4ce 848 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
5d7ff5bb
AF		 849 }
850}
851
b18d5d2b
RH		 852static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
853 TCGReg base, tcg_target_long offset)
810260a8 854{
b18d5d2b 855 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
de7761a3 856 bool is_store = false;
dfca1778 857 TCGReg rs = TCG_REG_TMP1;
b18d5d2b 858
b18d5d2b
RH		 859 switch (opi) {
860 case LD: case LWA:
861 align = 3;
862 /* FALLTHRU */
863 default:
864 if (rt != TCG_REG_R0) {
865 rs = rt;
de7761a3 866 break;
b18d5d2b
RH		 867 }
868 break;
869 case STD:
870 align = 3;
de7761a3 871 /* FALLTHRU */
b18d5d2b 872 case STB: case STH: case STW:
de7761a3 873 is_store = true;
b18d5d2b 874 break;
810260a8 875 }
810260a8 876
b18d5d2b
RH		 877 /* For unaligned, or very large offsets, use the indexed form. */
878 if (offset & align || offset != (int32_t)offset) {
d4cba13b
RH		 879 if (rs == base) {
880 rs = TCG_REG_R0;
881 }
882 tcg_debug_assert(!is_store || rs != rt);
de7761a3
RH		 883 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
884 tcg_out32(s, opx | TAB(rt, base, rs));
b18d5d2b
RH		 885 return;
886 }
887
888 l0 = (int16_t)offset;
889 offset = (offset - l0) >> 16;
890 l1 = (int16_t)offset;
891
892 if (l1 < 0 && orig >= 0) {
893 extra = 0x4000;
894 l1 = (int16_t)(offset - 0x4000);
895 }
896 if (l1) {
897 tcg_out32(s, ADDIS | TAI(rs, base, l1));
898 base = rs;
899 }
900 if (extra) {
901 tcg_out32(s, ADDIS | TAI(rs, base, extra));
902 base = rs;
903 }
904 if (opi != ADDI || base != rt || l0 != 0) {
905 tcg_out32(s, opi | TAI(rt, base, l0));
828808f5 906 }
907}
908
d604f1a9
RH		 909static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
910 TCGReg arg1, intptr_t arg2)
911{
912 int opi, opx;
810260a8 913
eabb7b91 914 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 915 if (type == TCG_TYPE_I32) {
916 opi = LWZ, opx = LWZX;
917 } else {
918 opi = LD, opx = LDX;
919 }
920 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
921}
fedee3e7 922
d604f1a9
RH		 923static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
924 TCGReg arg1, intptr_t arg2)
810260a8 925{
d604f1a9 926 int opi, opx;
fedee3e7 927
eabb7b91 928 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
d604f1a9
RH		 929 if (type == TCG_TYPE_I32) {
930 opi = STW, opx = STWX;
fedee3e7 931 } else {
d604f1a9 932 opi = STD, opx = STDX;
fedee3e7 933 }
d604f1a9
RH		 934 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
935}
810260a8 936
59d7c14e
RH		 937static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
938 TCGReg base, intptr_t ofs)
939{
940 return false;
941}
942
d604f1a9
RH		 943static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
944 int const_arg2, int cr, TCGType type)
945{
946 int imm;
947 uint32_t op;
810260a8 948
abcf61c4
RH		 949 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
950
d604f1a9
RH		 951 /* Simplify the comparisons below wrt CMPI. */
952 if (type == TCG_TYPE_I32) {
953 arg2 = (int32_t)arg2;
4a40e231 954 }
fedee3e7 955
d604f1a9
RH		 956 switch (cond) {
957 case TCG_COND_EQ:
958 case TCG_COND_NE:
959 if (const_arg2) {
960 if ((int16_t) arg2 == arg2) {
961 op = CMPI;
962 imm = 1;
963 break;
964 } else if ((uint16_t) arg2 == arg2) {
965 op = CMPLI;
966 imm = 1;
967 break;
968 }
969 }
970 op = CMPL;
971 imm = 0;
972 break;
fedee3e7 973
d604f1a9
RH		 974 case TCG_COND_LT:
975 case TCG_COND_GE:
976 case TCG_COND_LE:
977 case TCG_COND_GT:
978 if (const_arg2) {
979 if ((int16_t) arg2 == arg2) {
980 op = CMPI;
981 imm = 1;
982 break;
983 }
984 }
985 op = CMP;
986 imm = 0;
987 break;
fedee3e7 988
d604f1a9
RH		 989 case TCG_COND_LTU:
990 case TCG_COND_GEU:
991 case TCG_COND_LEU:
992 case TCG_COND_GTU:
993 if (const_arg2) {
994 if ((uint16_t) arg2 == arg2) {
995 op = CMPLI;
996 imm = 1;
997 break;
998 }
999 }
1000 op = CMPL;
1001 imm = 0;
1002 break;
fedee3e7 1003
d604f1a9
RH		 1004 default:
1005 tcg_abort();
fedee3e7 1006 }
d604f1a9 1007 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
fedee3e7 1008
d604f1a9
RH		 1009 if (imm) {
1010 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1011 } else {
1012 if (const_arg2) {
1013 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1014 arg2 = TCG_REG_R0;
1015 }
1016 tcg_out32(s, op | RA(arg1) | RB(arg2));
1017 }
810260a8 1018}
1019
d604f1a9
RH		 1020static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1021 TCGReg dst, TCGReg src)
7f12d649 1022{
a757e1ee
RH		 1023 if (type == TCG_TYPE_I32) {
1024 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1025 tcg_out_shri32(s, dst, dst, 5);
1026 } else {
1027 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1028 tcg_out_shri64(s, dst, dst, 6);
1029 }
7f12d649
RH		 1030}
1031
d604f1a9 1032static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
7f12d649 1033{
d604f1a9
RH		 1034 /* X != 0 implies X + -1 generates a carry. Extra addition
1035 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1036 if (dst != src) {
1037 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1038 tcg_out32(s, SUBFE | TAB(dst, dst, src));
7f12d649 1039 } else {
d604f1a9
RH		 1040 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1041 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
7f12d649 1042 }
d604f1a9 1043}
7f12d649 1044
d604f1a9
RH		 1045static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1046 bool const_arg2)
1047{
1048 if (const_arg2) {
1049 if ((uint32_t)arg2 == arg2) {
1050 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1051 } else {
1052 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1053 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1054 }
1055 } else {
1056 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1057 }
1058 return TCG_REG_R0;
7f12d649
RH		 1059}
1060
d604f1a9
RH		 1061static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1062 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1063 int const_arg2)
7f12d649 1064{
d604f1a9 1065 int crop, sh;
7f12d649 1066
eabb7b91 1067 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
a757e1ee 1068
d604f1a9
RH		 1069 /* Ignore high bits of a potential constant arg2. */
1070 if (type == TCG_TYPE_I32) {
1071 arg2 = (uint32_t)arg2;
1072 }
7f12d649 1073
d604f1a9
RH		 1074 /* Handle common and trivial cases before handling anything else. */
1075 if (arg2 == 0) {
1076 switch (cond) {
1077 case TCG_COND_EQ:
1078 tcg_out_setcond_eq0(s, type, arg0, arg1);
1079 return;
1080 case TCG_COND_NE:
a757e1ee 1081 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1082 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1083 arg1 = TCG_REG_R0;
1084 }
1085 tcg_out_setcond_ne0(s, arg0, arg1);
1086 return;
1087 case TCG_COND_GE:
1088 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1089 arg1 = arg0;
1090 /* FALLTHRU */
1091 case TCG_COND_LT:
1092 /* Extract the sign bit. */
a757e1ee
RH		 1093 if (type == TCG_TYPE_I32) {
1094 tcg_out_shri32(s, arg0, arg1, 31);
1095 } else {
1096 tcg_out_shri64(s, arg0, arg1, 63);
1097 }
d604f1a9
RH		 1098 return;
1099 default:
1100 break;
1101 }
1102 }
7f12d649 1103
d604f1a9
RH		 1104 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1105 All other cases below are also at least 3 insns, so speed up the
1106 code generator by not considering them and always using ISEL. */
1107 if (HAVE_ISEL) {
1108 int isel, tab;
7f12d649 1109
d604f1a9 1110 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
7f12d649 1111
d604f1a9 1112 isel = tcg_to_isel[cond];
7f12d649 1113
d604f1a9
RH		 1114 tcg_out_movi(s, type, arg0, 1);
1115 if (isel & 1) {
1116 /* arg0 = (bc ? 0 : 1) */
1117 tab = TAB(arg0, 0, arg0);
1118 isel &= ~1;
1119 } else {
1120 /* arg0 = (bc ? 1 : 0) */
1121 tcg_out_movi(s, type, TCG_REG_R0, 0);
1122 tab = TAB(arg0, arg0, TCG_REG_R0);
1123 }
1124 tcg_out32(s, isel | tab);
1125 return;
1126 }
49d9870a 1127
d604f1a9
RH		 1128 switch (cond) {
1129 case TCG_COND_EQ:
1130 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1131 tcg_out_setcond_eq0(s, type, arg0, arg1);
1132 return;
810260a8 1133
d604f1a9
RH		 1134 case TCG_COND_NE:
1135 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1136 /* Discard the high bits only once, rather than both inputs. */
a757e1ee 1137 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
d604f1a9
RH		 1138 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1139 arg1 = TCG_REG_R0;
1140 }
1141 tcg_out_setcond_ne0(s, arg0, arg1);
1142 return;
810260a8 1143
d604f1a9
RH		 1144 case TCG_COND_GT:
1145 case TCG_COND_GTU:
1146 sh = 30;
1147 crop = 0;
1148 goto crtest;
810260a8 1149
d604f1a9
RH		 1150 case TCG_COND_LT:
1151 case TCG_COND_LTU:
1152 sh = 29;
1153 crop = 0;
1154 goto crtest;
810260a8 1155
d604f1a9
RH		 1156 case TCG_COND_GE:
1157 case TCG_COND_GEU:
1158 sh = 31;
1159 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1160 goto crtest;
810260a8 1161
d604f1a9
RH		 1162 case TCG_COND_LE:
1163 case TCG_COND_LEU:
1164 sh = 31;
1165 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1166 crtest:
1167 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1168 if (crop) {
1169 tcg_out32(s, crop);
1170 }
1171 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1172 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1173 break;
1174
1175 default:
1176 tcg_abort();
1177 }
810260a8 1178}
1179
bec16311 1180static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
810260a8 1181{
d604f1a9 1182 if (l->has_value) {
f9c7246f 1183 bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr);
49d9870a 1184 } else {
bec16311 1185 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
810260a8 1186 }
f9c7246f 1187 tcg_out32(s, bc);
810260a8 1188}
1189
d604f1a9
RH		 1190static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1191 TCGArg arg1, TCGArg arg2, int const_arg2,
bec16311 1192 TCGLabel *l, TCGType type)
810260a8 1193{
d604f1a9 1194 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
bec16311 1195 tcg_out_bc(s, tcg_to_bc[cond], l);
d604f1a9 1196}
fa94c3be 1197
d604f1a9
RH		 1198static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1199 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1200 TCGArg v2, bool const_c2)
1201{
1202 /* If for some reason both inputs are zero, don't produce bad code. */
1203 if (v1 == 0 && v2 == 0) {
1204 tcg_out_movi(s, type, dest, 0);
1205 return;
b9e946c7 1206 }
f6548c0a 1207
d604f1a9 1208 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
a69abbe0 1209
d604f1a9
RH		 1210 if (HAVE_ISEL) {
1211 int isel = tcg_to_isel[cond];
810260a8 1212
d604f1a9
RH		 1213 /* Swap the V operands if the operation indicates inversion. */
1214 if (isel & 1) {
1215 int t = v1;
1216 v1 = v2;
1217 v2 = t;
1218 isel &= ~1;
1219 }
1220 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1221 if (v2 == 0) {
1222 tcg_out_movi(s, type, TCG_REG_R0, 0);
1223 }
1224 tcg_out32(s, isel | TAB(dest, v1, v2));
1225 } else {
1226 if (dest == v2) {
1227 cond = tcg_invert_cond(cond);
1228 v2 = v1;
1229 } else if (dest != v1) {
1230 if (v1 == 0) {
1231 tcg_out_movi(s, type, dest, 0);
1232 } else {
1233 tcg_out_mov(s, type, dest, v1);
1234 }
1235 }
1236 /* Branch forward over one insn */
1237 tcg_out32(s, tcg_to_bc[cond] | 8);
1238 if (v2 == 0) {
1239 tcg_out_movi(s, type, dest, 0);
1240 } else {
1241 tcg_out_mov(s, type, dest, v2);
1242 }
29b69198 1243 }
810260a8 1244}
1245
d0b07481
RH		 1246static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1247 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1248{
1249 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1250 tcg_out32(s, opc | RA(a0) | RS(a1));
1251 } else {
1252 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1253 /* Note that the only other valid constant for a2 is 0. */
1254 if (HAVE_ISEL) {
1255 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1256 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1257 } else if (!const_a2 && a0 == a2) {
1258 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1259 tcg_out32(s, opc | RA(a0) | RS(a1));
1260 } else {
1261 tcg_out32(s, opc | RA(a0) | RS(a1));
1262 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1263 if (const_a2) {
1264 tcg_out_movi(s, type, a0, 0);
1265 } else {
1266 tcg_out_mov(s, type, a0, a2);
1267 }
1268 }
1269 }
1270}
1271
abcf61c4
RH		 1272static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1273 const int *const_args)
1274{
1275 static const struct { uint8_t bit1, bit2; } bits[] = {
1276 [TCG_COND_LT ] = { CR_LT, CR_LT },
1277 [TCG_COND_LE ] = { CR_LT, CR_GT },
1278 [TCG_COND_GT ] = { CR_GT, CR_GT },
1279 [TCG_COND_GE ] = { CR_GT, CR_LT },
1280 [TCG_COND_LTU] = { CR_LT, CR_LT },
1281 [TCG_COND_LEU] = { CR_LT, CR_GT },
1282 [TCG_COND_GTU] = { CR_GT, CR_GT },
1283 [TCG_COND_GEU] = { CR_GT, CR_LT },
1284 };
1285
1286 TCGCond cond = args[4], cond2;
1287 TCGArg al, ah, bl, bh;
1288 int blconst, bhconst;
1289 int op, bit1, bit2;
1290
1291 al = args[0];
1292 ah = args[1];
1293 bl = args[2];
1294 bh = args[3];
1295 blconst = const_args[2];
1296 bhconst = const_args[3];
1297
1298 switch (cond) {
1299 case TCG_COND_EQ:
1300 op = CRAND;
1301 goto do_equality;
1302 case TCG_COND_NE:
1303 op = CRNAND;
1304 do_equality:
1305 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1306 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1307 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1308 break;
1309
1310 case TCG_COND_LT:
1311 case TCG_COND_LE:
1312 case TCG_COND_GT:
1313 case TCG_COND_GE:
1314 case TCG_COND_LTU:
1315 case TCG_COND_LEU:
1316 case TCG_COND_GTU:
1317 case TCG_COND_GEU:
1318 bit1 = bits[cond].bit1;
1319 bit2 = bits[cond].bit2;
1320 op = (bit1 != bit2 ? CRANDC : CRAND);
1321 cond2 = tcg_unsigned_cond(cond);
1322
1323 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1324 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1325 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1326 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1327 break;
1328
1329 default:
1330 tcg_abort();
1331 }
1332}
1333
1334static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1335 const int *const_args)
1336{
1337 tcg_out_cmp2(s, args + 1, const_args + 1);
1338 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1339 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1340}
1341
1342static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1343 const int *const_args)
1344{
1345 tcg_out_cmp2(s, args, const_args);
bec16311 1346 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
abcf61c4
RH		 1347}
1348
7b4af5ee
PK		 1349static void tcg_out_mb(TCGContext *s, TCGArg a0)
1350{
1351 uint32_t insn = HWSYNC;
1352 a0 &= TCG_MO_ALL;
1353 if (a0 == TCG_MO_LD_LD) {
1354 insn = LWSYNC;
1355 } else if (a0 == TCG_MO_ST_ST) {
1356 insn = EIEIO;
1357 }
1358 tcg_out32(s, insn);
1359}
1360
a8583393
RH		 1361void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
1362 uintptr_t addr)
810260a8 1363{
5964fca8
RH		 1364 if (TCG_TARGET_REG_BITS == 64) {
1365 tcg_insn_unit i1, i2;
1366 intptr_t tb_diff = addr - tc_ptr;
1367 intptr_t br_diff = addr - (jmp_addr + 4);
1368 uint64_t pair;
1369
1370 /* This does not exercise the range of the branch, but we do
1371 still need to be able to load the new value of TCG_REG_TB.
1372 But this does still happen quite often. */
1373 if (tb_diff == (int16_t)tb_diff) {
1374 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1375 i2 = B | (br_diff & 0x3fffffc);
1376 } else {
1377 intptr_t lo = (int16_t)tb_diff;
1378 intptr_t hi = (int32_t)(tb_diff - lo);
1379 assert(tb_diff == hi + lo);
1380 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1381 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
1382 }
5bfd75a3 1383#ifdef HOST_WORDS_BIGENDIAN
5964fca8 1384 pair = (uint64_t)i1 << 32 | i2;
5bfd75a3 1385#else
5964fca8 1386 pair = (uint64_t)i2 << 32 | i1;
5bfd75a3
RH		 1387#endif
1388
ba026602
PMD		 1389 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
1390 within atomic_set that would fail to build a ppc32 host. */
1391 atomic_set__nocheck((uint64_t *)jmp_addr, pair);
5964fca8
RH		 1392 flush_icache_range(jmp_addr, jmp_addr + 8);
1393 } else {
1394 intptr_t diff = addr - jmp_addr;
1395 tcg_debug_assert(in_range_b(diff));
1396 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1397 flush_icache_range(jmp_addr, jmp_addr + 4);
1398 }
399f1648 1399}
810260a8 1400
d604f1a9 1401static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
810260a8 1402{
eaf7d1cf 1403#ifdef _CALL_AIX
d604f1a9
RH		 1404 /* Look through the descriptor. If the branch is in range, and we
1405 don't have to spend too much effort on building the toc. */
1406 void *tgt = ((void **)target)[0];
1407 uintptr_t toc = ((uintptr_t *)target)[1];
1408 intptr_t diff = tcg_pcrel_diff(s, tgt);
b18d5d2b 1409
d604f1a9 1410 if (in_range_b(diff) && toc == (uint32_t)toc) {
dfca1778 1411 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
d604f1a9 1412 tcg_out_b(s, LK, tgt);
541dd4ce 1413 } else {
d604f1a9
RH		 1414 /* Fold the low bits of the constant into the addresses below. */
1415 intptr_t arg = (intptr_t)target;
1416 int ofs = (int16_t)arg;
1417
1418 if (ofs + 8 < 0x8000) {
1419 arg -= ofs;
1420 } else {
1421 ofs = 0;
1422 }
dfca1778
RH		 1423 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1424 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
d604f1a9 1425 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
dfca1778 1426 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
d604f1a9 1427 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
541dd4ce 1428 }
77e58d0d
UW		 1429#elif defined(_CALL_ELF) && _CALL_ELF == 2
1430 intptr_t diff;
1431
1432 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1433 address, which the callee uses to compute its TOC address. */
1434 /* FIXME: when the branch is in range, we could avoid r12 load if we
1435 knew that the destination uses the same TOC, and what its local
1436 entry point offset is. */
1437 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1438
1439 diff = tcg_pcrel_diff(s, target);
1440 if (in_range_b(diff)) {
1441 tcg_out_b(s, LK, target);
1442 } else {
1443 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1444 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1445 }
eaf7d1cf
RH		 1446#else
1447 tcg_out_b(s, LK, target);
d604f1a9 1448#endif
810260a8 1449}
1450
d604f1a9
RH		 1451static const uint32_t qemu_ldx_opc[16] = {
1452 [MO_UB] = LBZX,
1453 [MO_UW] = LHZX,
1454 [MO_UL] = LWZX,
1455 [MO_Q] = LDX,
1456 [MO_SW] = LHAX,
1457 [MO_SL] = LWAX,
1458 [MO_BSWAP | MO_UB] = LBZX,
1459 [MO_BSWAP | MO_UW] = LHBRX,
1460 [MO_BSWAP | MO_UL] = LWBRX,
1461 [MO_BSWAP | MO_Q] = LDBRX,
1462};
810260a8 1463
d604f1a9
RH		 1464static const uint32_t qemu_stx_opc[16] = {
1465 [MO_UB] = STBX,
1466 [MO_UW] = STHX,
1467 [MO_UL] = STWX,
1468 [MO_Q] = STDX,
1469 [MO_BSWAP | MO_UB] = STBX,
1470 [MO_BSWAP | MO_UW] = STHBRX,
1471 [MO_BSWAP | MO_UL] = STWBRX,
1472 [MO_BSWAP | MO_Q] = STDBRX,
1473};
991041a4 1474
d604f1a9
RH		 1475static const uint32_t qemu_exts_opc[4] = {
1476 EXTSB, EXTSH, EXTSW, 0
1477};
810260a8 1478
d604f1a9 1479#if defined (CONFIG_SOFTMMU)
659ef5cb
RH		 1480#include "tcg-ldst.inc.c"
1481
d604f1a9
RH		 1482/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1483 * int mmu_idx, uintptr_t ra)
1484 */
1485static void * const qemu_ld_helpers[16] = {
1486 [MO_UB] = helper_ret_ldub_mmu,
1487 [MO_LEUW] = helper_le_lduw_mmu,
1488 [MO_LEUL] = helper_le_ldul_mmu,
1489 [MO_LEQ] = helper_le_ldq_mmu,
1490 [MO_BEUW] = helper_be_lduw_mmu,
1491 [MO_BEUL] = helper_be_ldul_mmu,
1492 [MO_BEQ] = helper_be_ldq_mmu,
1493};
810260a8 1494
d604f1a9
RH		 1495/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1496 * uintxx_t val, int mmu_idx, uintptr_t ra)
1497 */
1498static void * const qemu_st_helpers[16] = {
1499 [MO_UB] = helper_ret_stb_mmu,
1500 [MO_LEUW] = helper_le_stw_mmu,
1501 [MO_LEUL] = helper_le_stl_mmu,
1502 [MO_LEQ] = helper_le_stq_mmu,
1503 [MO_BEUW] = helper_be_stw_mmu,
1504 [MO_BEUL] = helper_be_stl_mmu,
1505 [MO_BEQ] = helper_be_stq_mmu,
1506};
810260a8 1507
644f591a
RH		 1508/* We expect tlb_mask to be before tlb_table. */
1509QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
1510 offsetof(CPUArchState, tlb_mask));
1511
d604f1a9
RH		 1512/* Perform the TLB load and compare. Places the result of the comparison
1513 in CR7, loads the addend of the TLB into R3, and returns the register
1514 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1515
68d45bb6 1516static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
7f25c469 1517 TCGReg addrlo, TCGReg addrhi,
d604f1a9
RH		 1518 int mem_index, bool is_read)
1519{
1520 int cmp_off
1521 = (is_read
644f591a
RH		 1522 ? offsetof(CPUTLBEntry, addr_read)
1523 : offsetof(CPUTLBEntry, addr_write));
1524 int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
1525 int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
1526 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
85aa8081
RH		 1527 unsigned s_bits = opc & MO_SIZE;
1528 unsigned a_bits = get_alignment_bits(opc);
d604f1a9 1529
644f591a
RH		 1530 if (table_off > 0x7fff) {
1531 int mask_hi = mask_off - (int16_t)mask_off;
1532 int table_hi = table_off - (int16_t)table_off;
1533
1534 table_base = TCG_REG_R4;
1535 if (mask_hi == table_hi) {
1536 mask_base = table_base;
1537 } else if (mask_hi) {
1538 mask_base = TCG_REG_R3;
1539 tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16));
7f25c469 1540 }
644f591a
RH		 1541 tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16));
1542 mask_off -= mask_hi;
1543 table_off -= table_hi;
810260a8 1544 }
810260a8 1545
644f591a
RH		 1546 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1547 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off);
1548 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off);
1549
1550 /* Extract the page index, shifted into place for tlb index. */
1551 if (TCG_TARGET_REG_BITS == 32) {
1552 tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
1553 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
4c314da6 1554 } else {
644f591a
RH		 1555 tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
1556 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
810260a8 1557 }
644f591a 1558 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
810260a8 1559
644f591a
RH		 1560 /* Load the TLB comparator. */
1561 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1562 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
1563 ? LWZUX : LDUX);
1564 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
7f25c469 1565 } else {
644f591a
RH		 1566 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
1567 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1568 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1569 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1570 } else {
1571 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1572 }
7f25c469 1573 }
d604f1a9
RH		 1574
1575 /* Load the TLB addend for use on the fast path. Do this asap
1576 to minimize any load use delay. */
644f591a
RH		 1577 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
1578 offsetof(CPUTLBEntry, addend));
d604f1a9 1579
68d45bb6 1580 /* Clear the non-page, non-alignment bits from the address */
85aa8081
RH		 1581 if (TCG_TARGET_REG_BITS == 32) {
1582 /* We don't support unaligned accesses on 32-bits.
1583 * Preserve the bottom bits and thus trigger a comparison
1584 * failure on unaligned accesses.
68d45bb6 1585 */
85aa8081 1586 if (a_bits < s_bits) {
1f00b27f
SS		 1587 a_bits = s_bits;
1588 }
7f25c469 1589 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1f00b27f 1590 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
85aa8081
RH		 1591 } else {
1592 TCGReg t = addrlo;
1593
1594 /* If the access is unaligned, we need to make sure we fail if we
1595 * cross a page boundary. The trick is to add the access size-1
1596 * to the address before masking the low bits. That will make the
1597 * address overflow to the next page if we cross a page boundary,
1598 * which will then force a mismatch of the TLB compare.
1599 */
1600 if (a_bits < s_bits) {
1601 unsigned a_mask = (1 << a_bits) - 1;
1602 unsigned s_mask = (1 << s_bits) - 1;
1603 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1604 t = TCG_REG_R0;
1605 }
1606
1607 /* Mask the address for the requested alignment. */
1608 if (TARGET_LONG_BITS == 32) {
1609 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1610 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
644f591a
RH		 1611 /* Zero-extend the address for use in the final address. */
1612 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1613 addrlo = TCG_REG_R4;
85aa8081
RH		 1614 } else if (a_bits == 0) {
1615 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1616 } else {
1617 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1f00b27f 1618 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
68d45bb6 1619 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
68d45bb6 1620 }
70fac59a 1621 }
d604f1a9 1622
7f25c469 1623 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
dfca1778
RH		 1624 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1625 0, 7, TCG_TYPE_I32);
7f25c469
RH		 1626 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1627 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1628 } else {
dfca1778
RH		 1629 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1630 0, 7, TCG_TYPE_TL);
7f25c469 1631 }
d604f1a9 1632
7f25c469 1633 return addrlo;
70fac59a 1634}
1cd62ae9 1635
d604f1a9
RH		 1636/* Record the context of a call to the out of line helper code for the slow
1637 path for a load or store, so that we can later generate the correct
1638 helper code. */
3972ef6f 1639static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
7f25c469
RH		 1640 TCGReg datalo_reg, TCGReg datahi_reg,
1641 TCGReg addrlo_reg, TCGReg addrhi_reg,
3972ef6f 1642 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
70fac59a 1643{
d604f1a9
RH		 1644 TCGLabelQemuLdst *label = new_ldst_label(s);
1645
1646 label->is_ld = is_ld;
3972ef6f 1647 label->oi = oi;
7f25c469
RH		 1648 label->datalo_reg = datalo_reg;
1649 label->datahi_reg = datahi_reg;
1650 label->addrlo_reg = addrlo_reg;
1651 label->addrhi_reg = addrhi_reg;
d604f1a9 1652 label->raddr = raddr;
7f25c469 1653 label->label_ptr[0] = lptr;
70fac59a 1654}
1cd62ae9 1655
d604f1a9 1656static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
70fac59a 1657{
3972ef6f
RH		 1658 TCGMemOpIdx oi = lb->oi;
1659 TCGMemOp opc = get_memop(oi);
7f25c469 1660 TCGReg hi, lo, arg = TCG_REG_R3;
70fac59a 1661
d5132903 1662 **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
70fac59a 1663
7f25c469 1664 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1cd62ae9 1665
7f25c469
RH		 1666 lo = lb->addrlo_reg;
1667 hi = lb->addrhi_reg;
1668 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1669#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1670 arg |= 1;
1671#endif
1672 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1673 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1674 } else {
1675 /* If the address needed to be zero-extended, we'll have already
1676 placed it in R4. The only remaining case is 64-bit guest. */
1677 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1678 }
752c1fdb 1679
3972ef6f 1680 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1681 tcg_out32(s, MFSPR | RT(arg) | LR);
70fac59a 1682
2b7ec66f 1683 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
70fac59a 1684
7f25c469
RH		 1685 lo = lb->datalo_reg;
1686 hi = lb->datahi_reg;
1687 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1688 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1689 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1690 } else if (opc & MO_SIGN) {
d604f1a9 1691 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
7f25c469 1692 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
d604f1a9 1693 } else {
7f25c469 1694 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
70fac59a
RH		 1695 }
1696
d604f1a9
RH		 1697 tcg_out_b(s, 0, lb->raddr);
1698}
70fac59a 1699
d604f1a9
RH		 1700static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1701{
3972ef6f
RH		 1702 TCGMemOpIdx oi = lb->oi;
1703 TCGMemOp opc = get_memop(oi);
d604f1a9 1704 TCGMemOp s_bits = opc & MO_SIZE;
7f25c469 1705 TCGReg hi, lo, arg = TCG_REG_R3;
1cd62ae9 1706
d5132903 1707 **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
1cd62ae9 1708
7f25c469
RH		 1709 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1710
1711 lo = lb->addrlo_reg;
1712 hi = lb->addrhi_reg;
1713 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1714#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1715 arg |= 1;
1716#endif
1717 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1718 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1719 } else {
1720 /* If the address needed to be zero-extended, we'll have already
1721 placed it in R4. The only remaining case is 64-bit guest. */
1722 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1723 }
1cd62ae9 1724
7f25c469
RH		 1725 lo = lb->datalo_reg;
1726 hi = lb->datahi_reg;
1727 if (TCG_TARGET_REG_BITS == 32) {
1728 switch (s_bits) {
1729 case MO_64:
1730#ifdef TCG_TARGET_CALL_ALIGN_ARGS
1731 arg |= 1;
1732#endif
1733 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1734 /* FALLTHRU */
1735 case MO_32:
1736 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1737 break;
1738 default:
1739 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1740 break;
1741 }
1742 } else {
1743 if (s_bits == MO_64) {
1744 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1745 } else {
1746 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1747 }
1748 }
1cd62ae9 1749
3972ef6f 1750 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
7f25c469 1751 tcg_out32(s, MFSPR | RT(arg) | LR);
1cd62ae9 1752
2b7ec66f 1753 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
d604f1a9
RH		 1754
1755 tcg_out_b(s, 0, lb->raddr);
1cd62ae9 1756}
d604f1a9 1757#endif /* SOFTMMU */
1cd62ae9 1758
7f25c469 1759static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
810260a8 1760{
7f25c469
RH		 1761 TCGReg datalo, datahi, addrlo, rbase;
1762 TCGReg addrhi __attribute__((unused));
59227d5d 1763 TCGMemOpIdx oi;
7f25c469 1764 TCGMemOp opc, s_bits;
d604f1a9 1765#ifdef CONFIG_SOFTMMU
7f25c469 1766 int mem_index;
d604f1a9
RH		 1767 tcg_insn_unit *label_ptr;
1768#endif
810260a8 1769
7f25c469
RH		 1770 datalo = *args++;
1771 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1772 addrlo = *args++;
1773 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1774 oi = *args++;
1775 opc = get_memop(oi);
7f25c469
RH		 1776 s_bits = opc & MO_SIZE;
1777
d604f1a9 1778#ifdef CONFIG_SOFTMMU
59227d5d 1779 mem_index = get_mmuidx(oi);
68d45bb6 1780 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
d604f1a9
RH		 1781
1782 /* Load a pointer into the current opcode w/conditional branch-link. */
1783 label_ptr = s->code_ptr;
f9c7246f 1784 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
d604f1a9
RH		 1785
1786 rbase = TCG_REG_R3;
1787#else /* !CONFIG_SOFTMMU */
b76f21a7 1788 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 1789 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1790 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1791 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1792 }
1793#endif
1794
7f25c469
RH		 1795 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1796 if (opc & MO_BSWAP) {
1797 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1798 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1799 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1800 } else if (rbase != 0) {
1801 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1802 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1803 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1804 } else if (addrlo == datahi) {
1805 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1806 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1807 } else {
1808 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1809 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1810 }
541dd4ce 1811 } else {
2b7ec66f 1812 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
7f25c469
RH		 1813 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1814 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1815 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1816 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1817 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1818 } else if (insn) {
1819 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1820 } else {
1821 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1822 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1823 insn = qemu_exts_opc[s_bits];
1824 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1825 }
810260a8 1826 }
810260a8 1827
d604f1a9 1828#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1829 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1830 s->code_ptr, label_ptr);
d604f1a9 1831#endif
810260a8 1832}
1833
7f25c469 1834static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
027ffea9 1835{
7f25c469
RH		 1836 TCGReg datalo, datahi, addrlo, rbase;
1837 TCGReg addrhi __attribute__((unused));
59227d5d 1838 TCGMemOpIdx oi;
7f25c469 1839 TCGMemOp opc, s_bits;
d604f1a9 1840#ifdef CONFIG_SOFTMMU
7f25c469 1841 int mem_index;
d604f1a9
RH		 1842 tcg_insn_unit *label_ptr;
1843#endif
027ffea9 1844
7f25c469
RH		 1845 datalo = *args++;
1846 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1847 addrlo = *args++;
1848 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
59227d5d
RH		 1849 oi = *args++;
1850 opc = get_memop(oi);
7f25c469
RH		 1851 s_bits = opc & MO_SIZE;
1852
d604f1a9 1853#ifdef CONFIG_SOFTMMU
59227d5d 1854 mem_index = get_mmuidx(oi);
68d45bb6 1855 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
027ffea9 1856
d604f1a9
RH		 1857 /* Load a pointer into the current opcode w/conditional branch-link. */
1858 label_ptr = s->code_ptr;
f9c7246f 1859 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
027ffea9 1860
d604f1a9
RH		 1861 rbase = TCG_REG_R3;
1862#else /* !CONFIG_SOFTMMU */
b76f21a7 1863 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
7f25c469 1864 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
dfca1778
RH		 1865 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1866 addrlo = TCG_REG_TMP1;
d604f1a9
RH		 1867 }
1868#endif
1869
7f25c469
RH		 1870 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1871 if (opc & MO_BSWAP) {
1872 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1873 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1874 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1875 } else if (rbase != 0) {
1876 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1877 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1878 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1879 } else {
1880 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1881 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1882 }
027ffea9 1883 } else {
2b7ec66f 1884 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
7f25c469
RH		 1885 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1886 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
dfca1778 1887 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
7f25c469 1888 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
dfca1778 1889 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
7f25c469
RH		 1890 } else {
1891 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1892 }
027ffea9 1893 }
d604f1a9
RH		 1894
1895#ifdef CONFIG_SOFTMMU
3972ef6f
RH		 1896 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1897 s->code_ptr, label_ptr);
d604f1a9 1898#endif
027ffea9
RH		 1899}
1900
53c89efd
RH		 1901static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
1902{
1903 int i;
1904 for (i = 0; i < count; ++i) {
1905 p[i] = NOP;
1906 }
1907}
1908
a921fddc
RH		 1909/* Parameters for function call generation, used in tcg.c. */
1910#define TCG_TARGET_STACK_ALIGN 16
a921fddc
RH		 1911#define TCG_TARGET_EXTEND_ARGS 1
1912
802ca56e
RH		 1913#ifdef _CALL_AIX
1914# define LINK_AREA_SIZE (6 * SZR)
1915# define LR_OFFSET (1 * SZR)
1916# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1045fc04
PM		 1917#elif defined(TCG_TARGET_CALL_DARWIN)
1918# define LINK_AREA_SIZE (6 * SZR)
1919# define LR_OFFSET (2 * SZR)
ffcfbece
RH		 1920#elif TCG_TARGET_REG_BITS == 64
1921# if defined(_CALL_ELF) && _CALL_ELF == 2
1922# define LINK_AREA_SIZE (4 * SZR)
1923# define LR_OFFSET (1 * SZR)
1924# endif
1925#else /* TCG_TARGET_REG_BITS == 32 */
1926# if defined(_CALL_SYSV)
ffcfbece
RH		 1927# define LINK_AREA_SIZE (2 * SZR)
1928# define LR_OFFSET (1 * SZR)
ffcfbece
RH		 1929# endif
1930#endif
1931#ifndef LR_OFFSET
1932# error "Unhandled abi"
1933#endif
1934#ifndef TCG_TARGET_CALL_STACK_OFFSET
a2a98f80 1935# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
802ca56e
RH		 1936#endif
1937
1938#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1939#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
d604f1a9 1940
802ca56e
RH		 1941#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1942 + TCG_STATIC_CALL_ARGS_SIZE \
1943 + CPU_TEMP_BUF_SIZE \
1944 + REG_SAVE_SIZE \
1945 + TCG_TARGET_STACK_ALIGN - 1) \
1946 & -TCG_TARGET_STACK_ALIGN)
1947
1948#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
d604f1a9
RH		 1949
1950static void tcg_target_qemu_prologue(TCGContext *s)
810260a8 1951{
d604f1a9 1952 int i;
810260a8 1953
802ca56e 1954#ifdef _CALL_AIX
a84ac4cb
RH		 1955 void **desc = (void **)s->code_ptr;
1956 desc[0] = desc + 2; /* entry point */
1957 desc[1] = 0; /* environment pointer */
1958 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
d604f1a9
RH		 1959#endif
1960
a84ac4cb
RH		 1961 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1962 CPU_TEMP_BUF_SIZE);
1963
d604f1a9
RH		 1964 /* Prologue */
1965 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
ffcfbece
RH		 1966 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1967 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
802ca56e 1968
d604f1a9 1969 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1970 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1971 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1972 }
802ca56e 1973 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 1974
4cbea598 1975#ifndef CONFIG_SOFTMMU
b76f21a7 1976 if (guest_base) {
5964fca8 1977 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
d604f1a9
RH		 1978 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1979 }
1980#endif
1981
1982 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1983 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
5964fca8
RH		 1984 if (USE_REG_TB) {
1985 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
a84ac4cb 1986 }
5964fca8 1987 tcg_out32(s, BCCTR | BO_ALWAYS);
d604f1a9
RH		 1988
1989 /* Epilogue */
5964fca8 1990 s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
d604f1a9 1991
802ca56e 1992 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
d604f1a9 1993 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
4c3831a0
RH		 1994 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1995 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
d604f1a9 1996 }
d604f1a9
RH		 1997 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1998 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1999 tcg_out32(s, BCLR | BO_ALWAYS);
810260a8 2000}
2001
541dd4ce
RH		 2002static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
2003 const int *const_args)
810260a8 2004{
ee924fa6 2005 TCGArg a0, a1, a2;
e46b9681 2006 int c;
2007
810260a8 2008 switch (opc) {
2009 case INDEX_op_exit_tb:
de3d636d 2010 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
e083c4a2 2011 tcg_out_b(s, 0, tb_ret_addr);
810260a8 2012 break;
2013 case INDEX_op_goto_tb:
5964fca8
RH		 2014 if (s->tb_jmp_insn_offset) {
2015 /* Direct jump. */
2016 if (TCG_TARGET_REG_BITS == 64) {
2017 /* Ensure the next insns are 8-byte aligned. */
2018 if ((uintptr_t)s->code_ptr & 7) {
2019 tcg_out32(s, NOP);
2020 }
2021 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2022 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2023 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2024 } else {
2025 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2026 tcg_out32(s, B);
2027 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
2028 break;
2029 }
2030 } else {
2031 /* Indirect jump. */
2032 tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
2033 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2034 (intptr_t)(s->tb_jmp_insn_offset + args[0]));
2035 }
2036 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
5bfd75a3 2037 tcg_out32(s, BCCTR | BO_ALWAYS);
9f754620 2038 set_jmp_reset_offset(s, args[0]);
5964fca8
RH		 2039 if (USE_REG_TB) {
2040 /* For the unlinked case, need to reset TCG_REG_TB. */
9f754620 2041 c = -tcg_current_code_size(s);
5964fca8
RH		 2042 assert(c == (int16_t)c);
2043 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
2044 }
810260a8 2045 break;
0c240785
RH		 2046 case INDEX_op_goto_ptr:
2047 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
5964fca8
RH		 2048 if (USE_REG_TB) {
2049 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2050 }
2051 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
0c240785
RH		 2052 tcg_out32(s, BCCTR | BO_ALWAYS);
2053 break;
810260a8 2054 case INDEX_op_br:
2055 {
bec16311 2056 TCGLabel *l = arg_label(args[0]);
f9c7246f 2057 uint32_t insn = B;
810260a8 2058
2059 if (l->has_value) {
f9c7246f 2060 insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr);
541dd4ce 2061 } else {
bec16311 2062 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
810260a8 2063 }
f9c7246f 2064 tcg_out32(s, insn);
810260a8 2065 }
2066 break;
810260a8 2067 case INDEX_op_ld8u_i32:
2068 case INDEX_op_ld8u_i64:
b18d5d2b 2069 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
810260a8 2070 break;
2071 case INDEX_op_ld8s_i32:
2072 case INDEX_op_ld8s_i64:
b18d5d2b 2073 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
541dd4ce 2074 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
810260a8 2075 break;
2076 case INDEX_op_ld16u_i32:
2077 case INDEX_op_ld16u_i64:
b18d5d2b 2078 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
810260a8 2079 break;
2080 case INDEX_op_ld16s_i32:
2081 case INDEX_op_ld16s_i64:
b18d5d2b 2082 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
810260a8 2083 break;
2084 case INDEX_op_ld_i32:
2085 case INDEX_op_ld32u_i64:
b18d5d2b 2086 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
810260a8 2087 break;
2088 case INDEX_op_ld32s_i64:
b18d5d2b 2089 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
810260a8 2090 break;
2091 case INDEX_op_ld_i64:
b18d5d2b 2092 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
810260a8 2093 break;
2094 case INDEX_op_st8_i32:
2095 case INDEX_op_st8_i64:
b18d5d2b 2096 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
810260a8 2097 break;
2098 case INDEX_op_st16_i32:
2099 case INDEX_op_st16_i64:
b18d5d2b 2100 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
810260a8 2101 break;
2102 case INDEX_op_st_i32:
2103 case INDEX_op_st32_i64:
b18d5d2b 2104 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
810260a8 2105 break;
2106 case INDEX_op_st_i64:
b18d5d2b 2107 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
810260a8 2108 break;
2109
2110 case INDEX_op_add_i32:
ee924fa6
RH		 2111 a0 = args[0], a1 = args[1], a2 = args[2];
2112 if (const_args[2]) {
ee924fa6 2113 do_addi_32:
b18d5d2b 2114 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
ee924fa6
RH		 2115 } else {
2116 tcg_out32(s, ADD | TAB(a0, a1, a2));
2117 }
810260a8 2118 break;
2119 case INDEX_op_sub_i32:
ee924fa6 2120 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2121 if (const_args[1]) {
2122 if (const_args[2]) {
2123 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2124 } else {
2125 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2126 }
2127 } else if (const_args[2]) {
ee924fa6
RH		 2128 a2 = -a2;
2129 goto do_addi_32;
2130 } else {
2131 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2132 }
810260a8 2133 break;
2134
2135 case INDEX_op_and_i32:
37251b98 2136 a0 = args[0], a1 = args[1], a2 = args[2];
a9249dff 2137 if (const_args[2]) {
37251b98 2138 tcg_out_andi32(s, a0, a1, a2);
a9249dff 2139 } else {
37251b98 2140 tcg_out32(s, AND | SAB(a1, a0, a2));
a9249dff
RH		 2141 }
2142 break;
2143 case INDEX_op_and_i64:
37251b98 2144 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2145 if (const_args[2]) {
37251b98 2146 tcg_out_andi64(s, a0, a1, a2);
637af30c 2147 } else {
37251b98 2148 tcg_out32(s, AND | SAB(a1, a0, a2));
810260a8 2149 }
810260a8 2150 break;
fe6f943f 2151 case INDEX_op_or_i64:
810260a8 2152 case INDEX_op_or_i32:
dce74c57 2153 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2154 if (const_args[2]) {
dce74c57
RH		 2155 tcg_out_ori32(s, a0, a1, a2);
2156 } else {
2157 tcg_out32(s, OR | SAB(a1, a0, a2));
810260a8 2158 }
810260a8 2159 break;
fe6f943f 2160 case INDEX_op_xor_i64:
810260a8 2161 case INDEX_op_xor_i32:
dce74c57 2162 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2163 if (const_args[2]) {
dce74c57
RH		 2164 tcg_out_xori32(s, a0, a1, a2);
2165 } else {
2166 tcg_out32(s, XOR | SAB(a1, a0, a2));
810260a8 2167 }
810260a8 2168 break;
ce1010d6 2169 case INDEX_op_andc_i32:
37251b98
RH		 2170 a0 = args[0], a1 = args[1], a2 = args[2];
2171 if (const_args[2]) {
2172 tcg_out_andi32(s, a0, a1, ~a2);
2173 } else {
2174 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2175 }
2176 break;
ce1010d6 2177 case INDEX_op_andc_i64:
37251b98
RH		 2178 a0 = args[0], a1 = args[1], a2 = args[2];
2179 if (const_args[2]) {
2180 tcg_out_andi64(s, a0, a1, ~a2);
2181 } else {
2182 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2183 }
ce1010d6
RH		 2184 break;
2185 case INDEX_op_orc_i32:
37251b98
RH		 2186 if (const_args[2]) {
2187 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2188 break;
2189 }
2190 /* FALLTHRU */
ce1010d6
RH		 2191 case INDEX_op_orc_i64:
2192 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2193 break;
2194 case INDEX_op_eqv_i32:
37251b98
RH		 2195 if (const_args[2]) {
2196 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2197 break;
2198 }
2199 /* FALLTHRU */
ce1010d6
RH		 2200 case INDEX_op_eqv_i64:
2201 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2202 break;
2203 case INDEX_op_nand_i32:
2204 case INDEX_op_nand_i64:
2205 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2206 break;
2207 case INDEX_op_nor_i32:
2208 case INDEX_op_nor_i64:
2209 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2210 break;
810260a8 2211
d0b07481
RH		 2212 case INDEX_op_clz_i32:
2213 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2214 args[2], const_args[2]);
2215 break;
2216 case INDEX_op_ctz_i32:
2217 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2218 args[2], const_args[2]);
2219 break;
33e75fb9
RH		 2220 case INDEX_op_ctpop_i32:
2221 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2222 break;
d0b07481
RH		 2223
2224 case INDEX_op_clz_i64:
2225 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2226 args[2], const_args[2]);
2227 break;
2228 case INDEX_op_ctz_i64:
2229 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2230 args[2], const_args[2]);
2231 break;
33e75fb9
RH		 2232 case INDEX_op_ctpop_i64:
2233 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2234 break;
d0b07481 2235
810260a8 2236 case INDEX_op_mul_i32:
ef809300 2237 a0 = args[0], a1 = args[1], a2 = args[2];
810260a8 2238 if (const_args[2]) {
ef809300
RH		 2239 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2240 } else {
2241 tcg_out32(s, MULLW | TAB(a0, a1, a2));
810260a8 2242 }
810260a8 2243 break;
2244
2245 case INDEX_op_div_i32:
541dd4ce 2246 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
810260a8 2247 break;
2248
2249 case INDEX_op_divu_i32:
541dd4ce 2250 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
810260a8 2251 break;
2252
810260a8 2253 case INDEX_op_shl_i32:
2254 if (const_args[2]) {
a757e1ee 2255 tcg_out_shli32(s, args[0], args[1], args[2]);
9e555b73 2256 } else {
541dd4ce 2257 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
9e555b73 2258 }
810260a8 2259 break;
2260 case INDEX_op_shr_i32:
2261 if (const_args[2]) {
a757e1ee 2262 tcg_out_shri32(s, args[0], args[1], args[2]);
9e555b73 2263 } else {
541dd4ce 2264 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
9e555b73 2265 }
810260a8 2266 break;
2267 case INDEX_op_sar_i32:
541dd4ce
RH		 2268 if (const_args[2]) {
2269 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2270 } else {
2271 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2272 }
810260a8 2273 break;
313d91c7
RH		 2274 case INDEX_op_rotl_i32:
2275 if (const_args[2]) {
2276 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2277 } else {
2278 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2279 | MB(0) | ME(31));
2280 }
2281 break;
2282 case INDEX_op_rotr_i32:
2283 if (const_args[2]) {
2284 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2285 } else {
8327a470
RH		 2286 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2287 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
313d91c7
RH		 2288 | MB(0) | ME(31));
2289 }
2290 break;
810260a8 2291
2292 case INDEX_op_brcond_i32:
4c314da6 2293 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2294 arg_label(args[3]), TCG_TYPE_I32);
e924bbec 2295 break;
810260a8 2296 case INDEX_op_brcond_i64:
4c314da6 2297 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
bec16311 2298 arg_label(args[3]), TCG_TYPE_I64);
810260a8 2299 break;
abcf61c4
RH		 2300 case INDEX_op_brcond2_i32:
2301 tcg_out_brcond2(s, args, const_args);
2302 break;
810260a8 2303
2304 case INDEX_op_neg_i32:
810260a8 2305 case INDEX_op_neg_i64:
541dd4ce 2306 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
810260a8 2307 break;
2308
157f2662 2309 case INDEX_op_not_i32:
2310 case INDEX_op_not_i64:
541dd4ce 2311 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
157f2662 2312 break;
2313
810260a8 2314 case INDEX_op_add_i64:
ee924fa6
RH		 2315 a0 = args[0], a1 = args[1], a2 = args[2];
2316 if (const_args[2]) {
ee924fa6 2317 do_addi_64:
b18d5d2b 2318 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
ee924fa6
RH		 2319 } else {
2320 tcg_out32(s, ADD | TAB(a0, a1, a2));
2321 }
810260a8 2322 break;
2323 case INDEX_op_sub_i64:
ee924fa6 2324 a0 = args[0], a1 = args[1], a2 = args[2];
148bdd23
RH		 2325 if (const_args[1]) {
2326 if (const_args[2]) {
2327 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2328 } else {
2329 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2330 }
2331 } else if (const_args[2]) {
ee924fa6
RH		 2332 a2 = -a2;
2333 goto do_addi_64;
2334 } else {
2335 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2336 }
810260a8 2337 break;
2338
2339 case INDEX_op_shl_i64:
541dd4ce 2340 if (const_args[2]) {
0a9564b9 2341 tcg_out_shli64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2342 } else {
2343 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2344 }
810260a8 2345 break;
2346 case INDEX_op_shr_i64:
541dd4ce 2347 if (const_args[2]) {
5e916c28 2348 tcg_out_shri64(s, args[0], args[1], args[2]);
541dd4ce
RH		 2349 } else {
2350 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2351 }
810260a8 2352 break;
2353 case INDEX_op_sar_i64:
fe6f943f 2354 if (const_args[2]) {
541dd4ce
RH		 2355 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2356 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2357 } else {
2358 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
fe6f943f 2359 }
810260a8 2360 break;
313d91c7
RH		 2361 case INDEX_op_rotl_i64:
2362 if (const_args[2]) {
2363 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2364 } else {
2365 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2366 }
2367 break;
2368 case INDEX_op_rotr_i64:
2369 if (const_args[2]) {
2370 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2371 } else {
8327a470
RH		 2372 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2373 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
313d91c7
RH		 2374 }
2375 break;
810260a8 2376
2377 case INDEX_op_mul_i64:
ef809300
RH		 2378 a0 = args[0], a1 = args[1], a2 = args[2];
2379 if (const_args[2]) {
2380 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2381 } else {
2382 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2383 }
810260a8 2384 break;
2385 case INDEX_op_div_i64:
541dd4ce 2386 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
810260a8 2387 break;
2388 case INDEX_op_divu_i64:
541dd4ce 2389 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
810260a8 2390 break;
810260a8 2391
1768ec06 2392 case INDEX_op_qemu_ld_i32:
7f25c469
RH		 2393 tcg_out_qemu_ld(s, args, false);
2394 break;
1768ec06 2395 case INDEX_op_qemu_ld_i64:
7f25c469 2396 tcg_out_qemu_ld(s, args, true);
810260a8 2397 break;
1768ec06 2398 case INDEX_op_qemu_st_i32:
7f25c469
RH		 2399 tcg_out_qemu_st(s, args, false);
2400 break;
1768ec06 2401 case INDEX_op_qemu_st_i64:
7f25c469 2402 tcg_out_qemu_st(s, args, true);
810260a8 2403 break;
2404
e46b9681 2405 case INDEX_op_ext8s_i32:
2406 case INDEX_op_ext8s_i64:
2407 c = EXTSB;
2408 goto gen_ext;
2409 case INDEX_op_ext16s_i32:
2410 case INDEX_op_ext16s_i64:
2411 c = EXTSH;
2412 goto gen_ext;
4f2331e5 2413 case INDEX_op_ext_i32_i64:
e46b9681 2414 case INDEX_op_ext32s_i64:
2415 c = EXTSW;
2416 goto gen_ext;
2417 gen_ext:
541dd4ce 2418 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
e46b9681 2419 break;
4f2331e5
AJ		 2420 case INDEX_op_extu_i32_i64:
2421 tcg_out_ext32u(s, args[0], args[1]);
2422 break;
e46b9681 2423
1cd62ae9 2424 case INDEX_op_setcond_i32:
541dd4ce
RH		 2425 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2426 const_args[2]);
1cd62ae9 2427 break;
2428 case INDEX_op_setcond_i64:
541dd4ce
RH		 2429 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2430 const_args[2]);
1cd62ae9 2431 break;
abcf61c4
RH		 2432 case INDEX_op_setcond2_i32:
2433 tcg_out_setcond2(s, args, const_args);
2434 break;
1cd62ae9 2435
5d221582
RH		 2436 case INDEX_op_bswap16_i32:
2437 case INDEX_op_bswap16_i64:
2438 a0 = args[0], a1 = args[1];
2439 /* a1 = abcd */
2440 if (a0 != a1) {
2441 /* a0 = (a1 r<< 24) & 0xff # 000c */
2442 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2443 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2444 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2445 } else {
2446 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2447 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2448 /* a0 = (a1 r<< 24) & 0xff # 000c */
2449 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2450 /* a0 = a0 | r0 # 00dc */
2451 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2452 }
2453 break;
2454
2455 case INDEX_op_bswap32_i32:
2456 case INDEX_op_bswap32_i64:
2457 /* Stolen from gcc's builtin_bswap32 */
2458 a1 = args[1];
2459 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2460
2461 /* a1 = args[1] # abcd */
2462 /* a0 = rotate_left (a1, 8) # bcda */
2463 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2464 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2465 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2466 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2467 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2468
2469 if (a0 == TCG_REG_R0) {
de3d636d 2470 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
5d221582
RH		 2471 }
2472 break;
2473
68aebd45 2474 case INDEX_op_bswap64_i64:
8327a470 2475 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
68aebd45 2476 if (a0 == a1) {
8327a470 2477 a0 = TCG_REG_R0;
68aebd45
RH		 2478 a2 = a1;
2479 }
2480
2481 /* a1 = # abcd efgh */
2482 /* a0 = rl32(a1, 8) # 0000 fghe */
2483 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2484 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2485 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2486 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2487 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2488
2489 /* a0 = rl64(a0, 32) # hgfe 0000 */
2490 /* a2 = rl64(a1, 32) # efgh abcd */
2491 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2492 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2493
2494 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2495 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2496 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2497 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2498 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2499 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2500
2501 if (a0 == 0) {
de3d636d 2502 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
68aebd45
RH		 2503 }
2504 break;
2505
33de9ed2 2506 case INDEX_op_deposit_i32:
39dc85b9
RH		 2507 if (const_args[2]) {
2508 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2509 tcg_out_andi32(s, args[0], args[0], ~mask);
2510 } else {
2511 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2512 32 - args[3] - args[4], 31 - args[3]);
2513 }
33de9ed2
RH		 2514 break;
2515 case INDEX_op_deposit_i64:
39dc85b9
RH		 2516 if (const_args[2]) {
2517 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2518 tcg_out_andi64(s, args[0], args[0], ~mask);
2519 } else {
2520 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2521 64 - args[3] - args[4]);
2522 }
33de9ed2
RH		 2523 break;
2524
c05021c3
RH		 2525 case INDEX_op_extract_i32:
2526 tcg_out_rlw(s, RLWINM, args[0], args[1],
2527 32 - args[2], 32 - args[3], 31);
2528 break;
2529 case INDEX_op_extract_i64:
2530 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2531 break;
2532
027ffea9
RH		 2533 case INDEX_op_movcond_i32:
2534 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2535 args[3], args[4], const_args[2]);
2536 break;
2537 case INDEX_op_movcond_i64:
2538 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2539 args[3], args[4], const_args[2]);
2540 break;
2541
796f1a68 2542#if TCG_TARGET_REG_BITS == 64
6c858762 2543 case INDEX_op_add2_i64:
796f1a68
RH		 2544#else
2545 case INDEX_op_add2_i32:
2546#endif
6c858762
RH		 2547 /* Note that the CA bit is defined based on the word size of the
2548 environment. So in 64-bit mode it's always carry-out of bit 63.
2549 The fallback code using deposit works just as well for 32-bit. */
2550 a0 = args[0], a1 = args[1];
84247357 2551 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
6c858762
RH		 2552 a0 = TCG_REG_R0;
2553 }
84247357
AB		 2554 if (const_args[4]) {
2555 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
6c858762 2556 } else {
84247357 2557 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
6c858762
RH		 2558 }
2559 if (const_args[5]) {
84247357 2560 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
6c858762 2561 } else {
84247357 2562 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
6c858762
RH		 2563 }
2564 if (a0 != args[0]) {
de3d636d 2565 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2566 }
2567 break;
2568
796f1a68 2569#if TCG_TARGET_REG_BITS == 64
6c858762 2570 case INDEX_op_sub2_i64:
796f1a68
RH		 2571#else
2572 case INDEX_op_sub2_i32:
2573#endif
6c858762 2574 a0 = args[0], a1 = args[1];
b31284ce 2575 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
6c858762
RH		 2576 a0 = TCG_REG_R0;
2577 }
2578 if (const_args[2]) {
b31284ce 2579 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
6c858762 2580 } else {
b31284ce 2581 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
6c858762 2582 }
b31284ce
RH		 2583 if (const_args[3]) {
2584 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
6c858762 2585 } else {
b31284ce 2586 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
6c858762
RH		 2587 }
2588 if (a0 != args[0]) {
de3d636d 2589 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
6c858762
RH		 2590 }
2591 break;
2592
abcf61c4
RH		 2593 case INDEX_op_muluh_i32:
2594 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2595 break;
8fa391a0
RH		 2596 case INDEX_op_mulsh_i32:
2597 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2598 break;
32f5717f
RH		 2599 case INDEX_op_muluh_i64:
2600 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2601 break;
2602 case INDEX_op_mulsh_i64:
2603 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
6645c147
RH		 2604 break;
2605
7b4af5ee
PK		 2606 case INDEX_op_mb:
2607 tcg_out_mb(s, args[0]);
2608 break;
2609
96d0ee7f
RH		 2610 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2611 case INDEX_op_mov_i64:
2612 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2613 case INDEX_op_movi_i64:
2614 case INDEX_op_call: /* Always emitted via tcg_out_call. */
810260a8 2615 default:
541dd4ce 2616 tcg_abort();
810260a8 2617 }
2618}
2619
6cb3658a
RH		 2620static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2621{
2622 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2623 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2624 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2625 static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
2626 static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
2627 static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
2628 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2629 static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
2630 static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
2631 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2632 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2633 static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
2634 static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
2635 static const TCGTargetOpDef r_rI_ri
2636 = { .args_ct_str = { "r", "rI", "ri" } };
2637 static const TCGTargetOpDef r_rI_rT
2638 = { .args_ct_str = { "r", "rI", "rT" } };
2639 static const TCGTargetOpDef r_r_rZW
2640 = { .args_ct_str = { "r", "r", "rZW" } };
2641 static const TCGTargetOpDef L_L_L_L
2642 = { .args_ct_str = { "L", "L", "L", "L" } };
2643 static const TCGTargetOpDef S_S_S_S
2644 = { .args_ct_str = { "S", "S", "S", "S" } };
2645 static const TCGTargetOpDef movc
2646 = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
2647 static const TCGTargetOpDef dep
2648 = { .args_ct_str = { "r", "0", "rZ" } };
2649 static const TCGTargetOpDef br2
2650 = { .args_ct_str = { "r", "r", "ri", "ri" } };
2651 static const TCGTargetOpDef setc2
2652 = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
2653 static const TCGTargetOpDef add2
2654 = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
2655 static const TCGTargetOpDef sub2
2656 = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
2657
2658 switch (op) {
2659 case INDEX_op_goto_ptr:
2660 return &r;
796f1a68 2661
6cb3658a
RH		 2662 case INDEX_op_ld8u_i32:
2663 case INDEX_op_ld8s_i32:
2664 case INDEX_op_ld16u_i32:
2665 case INDEX_op_ld16s_i32:
2666 case INDEX_op_ld_i32:
2667 case INDEX_op_st8_i32:
2668 case INDEX_op_st16_i32:
2669 case INDEX_op_st_i32:
2670 case INDEX_op_ctpop_i32:
2671 case INDEX_op_neg_i32:
2672 case INDEX_op_not_i32:
2673 case INDEX_op_ext8s_i32:
2674 case INDEX_op_ext16s_i32:
2675 case INDEX_op_bswap16_i32:
2676 case INDEX_op_bswap32_i32:
2677 case INDEX_op_extract_i32:
2678 case INDEX_op_ld8u_i64:
2679 case INDEX_op_ld8s_i64:
2680 case INDEX_op_ld16u_i64:
2681 case INDEX_op_ld16s_i64:
2682 case INDEX_op_ld32u_i64:
2683 case INDEX_op_ld32s_i64:
2684 case INDEX_op_ld_i64:
2685 case INDEX_op_st8_i64:
2686 case INDEX_op_st16_i64:
2687 case INDEX_op_st32_i64:
2688 case INDEX_op_st_i64:
2689 case INDEX_op_ctpop_i64:
2690 case INDEX_op_neg_i64:
2691 case INDEX_op_not_i64:
2692 case INDEX_op_ext8s_i64:
2693 case INDEX_op_ext16s_i64:
2694 case INDEX_op_ext32s_i64:
2695 case INDEX_op_ext_i32_i64:
2696 case INDEX_op_extu_i32_i64:
2697 case INDEX_op_bswap16_i64:
2698 case INDEX_op_bswap32_i64:
2699 case INDEX_op_bswap64_i64:
2700 case INDEX_op_extract_i64:
2701 return &r_r;
abcf61c4 2702
6cb3658a
RH		 2703 case INDEX_op_add_i32:
2704 case INDEX_op_and_i32:
2705 case INDEX_op_or_i32:
2706 case INDEX_op_xor_i32:
2707 case INDEX_op_andc_i32:
2708 case INDEX_op_orc_i32:
2709 case INDEX_op_eqv_i32:
2710 case INDEX_op_shl_i32:
2711 case INDEX_op_shr_i32:
2712 case INDEX_op_sar_i32:
2713 case INDEX_op_rotl_i32:
2714 case INDEX_op_rotr_i32:
2715 case INDEX_op_setcond_i32:
2716 case INDEX_op_and_i64:
2717 case INDEX_op_andc_i64:
2718 case INDEX_op_shl_i64:
2719 case INDEX_op_shr_i64:
2720 case INDEX_op_sar_i64:
2721 case INDEX_op_rotl_i64:
2722 case INDEX_op_rotr_i64:
2723 case INDEX_op_setcond_i64:
2724 return &r_r_ri;
2725 case INDEX_op_mul_i32:
2726 case INDEX_op_mul_i64:
2727 return &r_r_rI;
2728 case INDEX_op_div_i32:
2729 case INDEX_op_divu_i32:
2730 case INDEX_op_nand_i32:
2731 case INDEX_op_nor_i32:
2732 case INDEX_op_muluh_i32:
2733 case INDEX_op_mulsh_i32:
2734 case INDEX_op_orc_i64:
2735 case INDEX_op_eqv_i64:
2736 case INDEX_op_nand_i64:
2737 case INDEX_op_nor_i64:
2738 case INDEX_op_div_i64:
2739 case INDEX_op_divu_i64:
2740 case INDEX_op_mulsh_i64:
2741 case INDEX_op_muluh_i64:
2742 return &r_r_r;
2743 case INDEX_op_sub_i32:
2744 return &r_rI_ri;
2745 case INDEX_op_add_i64:
2746 return &r_r_rT;
2747 case INDEX_op_or_i64:
2748 case INDEX_op_xor_i64:
2749 return &r_r_rU;
2750 case INDEX_op_sub_i64:
2751 return &r_rI_rT;
2752 case INDEX_op_clz_i32:
2753 case INDEX_op_ctz_i32:
2754 case INDEX_op_clz_i64:
2755 case INDEX_op_ctz_i64:
2756 return &r_r_rZW;
796f1a68 2757
6cb3658a
RH		 2758 case INDEX_op_brcond_i32:
2759 case INDEX_op_brcond_i64:
2760 return &r_ri;
6c858762 2761
6cb3658a
RH		 2762 case INDEX_op_movcond_i32:
2763 case INDEX_op_movcond_i64:
2764 return &movc;
2765 case INDEX_op_deposit_i32:
2766 case INDEX_op_deposit_i64:
2767 return &dep;
2768 case INDEX_op_brcond2_i32:
2769 return &br2;
2770 case INDEX_op_setcond2_i32:
2771 return &setc2;
2772 case INDEX_op_add2_i64:
2773 case INDEX_op_add2_i32:
2774 return &add2;
2775 case INDEX_op_sub2_i64:
2776 case INDEX_op_sub2_i32:
2777 return &sub2;
810260a8 2778
6cb3658a
RH		 2779 case INDEX_op_qemu_ld_i32:
2780 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2781 ? &r_L : &r_L_L);
2782 case INDEX_op_qemu_st_i32:
2783 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2784 ? &S_S : &S_S_S);
2785 case INDEX_op_qemu_ld_i64:
2786 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2787 : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
2788 case INDEX_op_qemu_st_i64:
2789 return (TCG_TARGET_REG_BITS == 64 ? &S_S
2790 : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
f69d277e 2791
6cb3658a
RH		 2792 default:
2793 return NULL;
f69d277e 2794 }
f69d277e
RH		 2795}
2796
541dd4ce 2797static void tcg_target_init(TCGContext *s)
810260a8 2798{
cd629de1 2799 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
d0b07481
RH		 2800 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
2801
1e6e9aca
RH		 2802 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2803 have_isa_2_06 = true;
2804 }
d0b07481
RH		 2805#ifdef PPC_FEATURE2_ARCH_3_00
2806 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
2807 have_isa_3_00 = true;
2808 }
2809#endif
1e6e9aca 2810
f46934df
RH		 2811 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2812 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2813
2814 tcg_target_call_clobber_regs = 0;
2815 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2816 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2817 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2818 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
2819 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
2820 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
2821 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
2822 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2823 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2824 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2825 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2826 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
810260a8 2827
ccb1bb66 2828 s->reserved_regs = 0;
5e1702b0
RH		 2829 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2830 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
dfca1778
RH		 2831#if defined(_CALL_SYSV)
2832 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
5d7ff5bb 2833#endif
dfca1778 2834#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
5e1702b0 2835 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
dfca1778
RH		 2836#endif
2837 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
5964fca8
RH		 2838 if (USE_REG_TB) {
2839 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
a84ac4cb 2840 }
810260a8 2841}
fa94c3be 2842
ffcfbece 2843#ifdef __ELF__
fa94c3be
RH		 2844typedef struct {
2845 DebugFrameCIE cie;
2846 DebugFrameFDEHeader fde;
2847 uint8_t fde_def_cfa[4];
2848 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2849} DebugFrame;
2850
2851/* We're expecting a 2 byte uleb128 encoded value. */
2852QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2853
ffcfbece
RH		 2854#if TCG_TARGET_REG_BITS == 64
2855# define ELF_HOST_MACHINE EM_PPC64
2856#else
2857# define ELF_HOST_MACHINE EM_PPC
2858#endif
fa94c3be
RH		 2859
2860static DebugFrame debug_frame = {
2861 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2862 .cie.id = -1,
2863 .cie.version = 1,
2864 .cie.code_align = 1,
802ca56e 2865 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
fa94c3be
RH		 2866 .cie.return_column = 65,
2867
2868 /* Total FDE size does not include the "len" member. */
2869 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2870
2871 .fde_def_cfa = {
802ca56e 2872 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
fa94c3be
RH		 2873 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2874 (FRAME_SIZE >> 7)
2875 },
2876 .fde_reg_ofs = {
802ca56e
RH		 2877 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2878 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
fa94c3be
RH		 2879 }
2880};
2881
2882void tcg_register_jit(void *buf, size_t buf_size)
2883{
2884 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2885 int i;
2886
2887 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2888 p[0] = 0x80 + tcg_target_callee_save_regs[i];
802ca56e 2889 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
fa94c3be
RH		 2890 }
2891
802ca56e 2892 debug_frame.fde.func_start = (uintptr_t)buf;
fa94c3be
RH		 2893 debug_frame.fde.func_len = buf_size;
2894
2895 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2896}
ffcfbece 2897#endif /* __ELF__ */
224f9fd4 2898
224f9fd4
RH		 2899void flush_icache_range(uintptr_t start, uintptr_t stop)
2900{
2901 uintptr_t p, start1, stop1;
b255b2c8
EC		 2902 size_t dsize = qemu_dcache_linesize;
2903 size_t isize = qemu_icache_linesize;
224f9fd4
RH		 2904
2905 start1 = start & ~(dsize - 1);
2906 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2907 for (p = start1; p < stop1; p += dsize) {
2908 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2909 }
2910 asm volatile ("sync" : : : "memory");
2911
2912 start &= start & ~(isize - 1);
2913 stop1 = (stop + isize - 1) & ~(isize - 1);
2914 for (p = start1; p < stop1; p += isize) {
2915 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2916 }
2917 asm volatile ("sync" : : : "memory");
2918 asm volatile ("isync" : : : "memory");
2919}
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