[qemu.git] / target-microblaze / cpu.h

/*
 *  MicroBlaze virtual CPU header
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_MICROBLAZE_H
#define CPU_MICROBLAZE_H

#include "config.h"
#include "qemu-common.h"

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUMBState

#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
struct CPUMBState;
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_MICROBLAZE

#define EXCP_NMI        1
#define EXCP_MMU        2
#define EXCP_IRQ        3
#define EXCP_BREAK      4
#define EXCP_HW_BREAK   5
#define EXCP_HW_EXCP    6

/* MicroBlaze-specific interrupt pending bits.  */
#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3

/* Register aliases. R0 - R15 */
#define R_SP     1
#define SR_PC    0
#define SR_MSR   1
#define SR_EAR   3
#define SR_ESR   5
#define SR_FSR   7
#define SR_BTR   0xb
#define SR_EDR   0xd

/* MSR flags.  */
#define MSR_BE  (1<<0) /* 0x001 */
#define MSR_IE  (1<<1) /* 0x002 */
#define MSR_C   (1<<2) /* 0x004 */
#define MSR_BIP (1<<3) /* 0x008 */
#define MSR_FSL (1<<4) /* 0x010 */
#define MSR_ICE (1<<5) /* 0x020 */
#define MSR_DZ  (1<<6) /* 0x040 */
#define MSR_DCE (1<<7) /* 0x080 */
#define MSR_EE  (1<<8) /* 0x100 */
#define MSR_EIP (1<<9) /* 0x200 */
#define MSR_PVR (1<<10) /* 0x400 */
#define MSR_CC  (1<<31)

/* Machine State Register (MSR) Fields */
#define MSR_UM (1<<11) /* User Mode */
#define MSR_UMS        (1<<12) /* User Mode Save */
#define MSR_VM (1<<13) /* Virtual Mode */
#define MSR_VMS        (1<<14) /* Virtual Mode Save */

#define MSR_KERNEL      MSR_EE|MSR_VM
//#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
#define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE

/* Exception State Register (ESR) Fields */
#define          ESR_DIZ       (1<<11) /* Zone Protection */
#define          ESR_S         (1<<10) /* Store instruction */

#define          ESR_ESS_FSL_OFFSET     5

#define          ESR_EC_FSL             0
#define          ESR_EC_UNALIGNED_DATA  1
#define          ESR_EC_ILLEGAL_OP      2
#define          ESR_EC_INSN_BUS        3
#define          ESR_EC_DATA_BUS        4
#define          ESR_EC_DIVZERO         5
#define          ESR_EC_FPU             6
#define          ESR_EC_PRIVINSN        7
#define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
#define          ESR_EC_DATA_STORAGE    8
#define          ESR_EC_INSN_STORAGE    9
#define          ESR_EC_DATA_TLB        10
#define          ESR_EC_INSN_TLB        11
#define          ESR_EC_MASK            31

/* Floating Point Status Register (FSR) Bits */
#define FSR_IO          (1<<4) /* Invalid operation */
#define FSR_DZ          (1<<3) /* Divide-by-zero */
#define FSR_OF          (1<<2) /* Overflow */
#define FSR_UF          (1<<1) /* Underflow */
#define FSR_DO          (1<<0) /* Denormalized operand error */

/* Version reg.  */
/* Basic PVR mask */
#define PVR0_PVR_FULL_MASK              0x80000000
#define PVR0_USE_BARREL_MASK            0x40000000
#define PVR0_USE_DIV_MASK               0x20000000
#define PVR0_USE_HW_MUL_MASK            0x10000000
#define PVR0_USE_FPU_MASK               0x08000000
#define PVR0_USE_EXC_MASK               0x04000000
#define PVR0_USE_ICACHE_MASK            0x02000000
#define PVR0_USE_DCACHE_MASK            0x01000000
#define PVR0_USE_MMU                    0x00800000      /* new */
#define PVR0_USE_BTC			0x00400000
#define PVR0_ENDI			0x00200000
#define PVR0_FAULT			0x00100000
#define PVR0_VERSION_MASK               0x0000FF00
#define PVR0_USER1_MASK                 0x000000FF

/* User 2 PVR mask */
#define PVR1_USER2_MASK                 0xFFFFFFFF

/* Configuration PVR masks */
#define PVR2_D_OPB_MASK                 0x80000000
#define PVR2_D_LMB_MASK                 0x40000000
#define PVR2_I_OPB_MASK                 0x20000000
#define PVR2_I_LMB_MASK                 0x10000000
#define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
#define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
#define PVR2_D_PLB_MASK                 0x02000000      /* new */
#define PVR2_I_PLB_MASK                 0x01000000      /* new */
#define PVR2_INTERCONNECT               0x00800000      /* new */
#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
#define PVR2_USE_FSL_EXC                0x00040000      /* new */
#define PVR2_USE_MSR_INSTR              0x00020000
#define PVR2_USE_PCMP_INSTR             0x00010000
#define PVR2_AREA_OPTIMISED             0x00008000
#define PVR2_USE_BARREL_MASK            0x00004000
#define PVR2_USE_DIV_MASK               0x00002000
#define PVR2_USE_HW_MUL_MASK            0x00001000
#define PVR2_USE_FPU_MASK               0x00000800
#define PVR2_USE_MUL64_MASK             0x00000400
#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
#define PVR2_USE_IPLBEXC                0x00000100
#define PVR2_USE_DPLBEXC                0x00000080
#define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
#define PVR2_UNALIGNED_EXC_MASK         0x00000020
#define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
#define PVR2_IOPB_BUS_EXC_MASK          0x00000008
#define PVR2_DOPB_BUS_EXC_MASK          0x00000004
#define PVR2_DIV_ZERO_EXC_MASK          0x00000002
#define PVR2_FPU_EXC_MASK               0x00000001

/* Debug and exception PVR masks */
#define PVR3_DEBUG_ENABLED_MASK         0x80000000
#define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define PVR3_FSL_LINKS_MASK             0x00000380

/* ICache config PVR masks */
#define PVR4_USE_ICACHE_MASK            0x80000000
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000

/* DCache config PVR masks */
#define PVR5_USE_DCACHE_MASK            0x80000000
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
#define PVR5_DCACHE_WRITEBACK_MASK      0x00004000

/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF

/* ICache high address PVR mask */
#define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF

/* DCache base address PVR mask */
#define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF

/* DCache high address PVR mask */
#define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF

/* Target family PVR mask */
#define PVR10_TARGET_FAMILY_MASK        0xFF000000

/* MMU descrtiption */
#define PVR11_USE_MMU                   0xC0000000
#define PVR11_MMU_ITLB_SIZE             0x38000000
#define PVR11_MMU_DTLB_SIZE             0x07000000
#define PVR11_MMU_TLB_ACCESS            0x00C00000
#define PVR11_MMU_ZONES                 0x003E0000
/* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF


/* CPU flags.  */

/* Condition codes.  */
#define CC_GE  5
#define CC_GT  4
#define CC_LE  3
#define CC_LT  2
#define CC_NE  1
#define CC_EQ  0

#define NB_MMU_MODES    3

#define STREAM_EXCEPTION (1 << 0)
#define STREAM_ATOMIC    (1 << 1)
#define STREAM_TEST      (1 << 2)
#define STREAM_CONTROL   (1 << 3)
#define STREAM_NONBLOCK  (1 << 4)

struct CPUMBState {
    uint32_t debug;
    uint32_t btaken;
    uint32_t btarget;
    uint32_t bimm;

    uint32_t imm;
    uint32_t regs[33];
    uint32_t sregs[24];
    float_status fp_status;
    /* Stack protectors. Yes, it's a hw feature.  */
    uint32_t slr, shr;

    /* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
    uint32_t res_addr;

    /* Internal flags.  */
#define IMM_FLAG	4
#define MSR_EE_FLAG     (1 << 8)
#define DRTI_FLAG	(1 << 16)
#define DRTE_FLAG	(1 << 17)
#define DRTB_FLAG	(1 << 18)
#define D_FLAG		(1 << 19)  /* Bit in ESR.  */
/* TB dependent CPUMBState.  */
#define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
    uint32_t iflags;

    struct {
        uint32_t regs[16];
    } pvr;

#if !defined(CONFIG_USER_ONLY)
    /* Unified MMU.  */
    struct microblaze_mmu mmu;
#endif

    CPU_COMMON
};

#include "cpu-qom.h"

void mb_tcg_init(void);
MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
int cpu_mb_exec(CPUMBState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_mb_signal_handler(int host_signum, void *pinfo,
                          void *puc);

enum {
    CC_OP_DYNAMIC, /* Use env->cc_op  */
    CC_OP_FLAGS,
    CC_OP_CMP,
};

/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
#define TARGET_PAGE_BITS 12
#define MMAP_SHIFT TARGET_PAGE_BITS

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

static inline CPUMBState *cpu_init(const char *cpu_model)
{
    MicroBlazeCPU *cpu = cpu_mb_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

#define cpu_exec cpu_mb_exec
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _user
#define MMU_NOMMU_IDX   0
#define MMU_KERNEL_IDX  1
#define MMU_USER_IDX    2
/* See NB_MMU_MODES further up the file.  */

static inline int cpu_mmu_index (CPUMBState *env)
{
        /* Are we in nommu mode?.  */
        if (!(env->sregs[SR_MSR] & MSR_VM))
            return MMU_NOMMU_IDX;

	if (env->sregs[SR_MSR] & MSR_UM)
            return MMU_USER_IDX;
        return MMU_KERNEL_IDX;
}

int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
                            int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault

static inline int cpu_interrupts_enabled(CPUMBState *env)
{
    return env->sregs[SR_MSR] & MSR_IE;
}

#include "exec/cpu-all.h"

static inline target_ulong cpu_get_pc(CPUMBState *env)
{
    return env->sregs[SR_PC];
}

static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->sregs[SR_PC];
    *cs_base = 0;
    *flags = (env->iflags & IFLAGS_TB_MASK) |
                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
}

#if !defined(CONFIG_USER_ONLY)
void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size);
#endif

static inline bool cpu_has_work(CPUState *cpu)
{
    return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}

#include "exec/exec-all.h"

static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb)
{
    env->sregs[SR_PC] = tb->pc;
}

#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze virtual CPU header
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	18	*/
	19	#ifndef CPU_MICROBLAZE_H
	20	#define CPU_MICROBLAZE_H
	21
94598c1d SW	22	#include "config.h"
	23	#include "qemu-common.h"
	24
4acb54ba EI	25	#define TARGET_LONG_BITS 32
4acb54ba EI	26
9349b4f9	27	#define CPUArchState struct CPUMBState
4acb54ba	28
022c62cb	29	#include "exec/cpu-defs.h"
6b4c305c	30	#include "fpu/softfloat.h"
4acb54ba	31	struct CPUMBState;
9b9a970a	32	typedef struct CPUMBState CPUMBState;
4acb54ba EI	33	#if !defined(CONFIG_USER_ONLY)
	34	#include "mmu.h"
	35	#endif
	36
	37	#define TARGET_HAS_ICE 1
	38
0d5d4699	39	#define ELF_MACHINE EM_MICROBLAZE
4acb54ba EI	40
	41	#define EXCP_NMI 1
	42	#define EXCP_MMU 2
	43	#define EXCP_IRQ 3
	44	#define EXCP_BREAK 4
	45	#define EXCP_HW_BREAK 5
cedb936b	46	#define EXCP_HW_EXCP 6
4acb54ba	47
85097db6 RH	48	/* MicroBlaze-specific interrupt pending bits. */
	49	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
	50
4acb54ba EI	51	/* Register aliases. R0 - R15 */
	52	#define R_SP 1
	53	#define SR_PC 0
	54	#define SR_MSR 1
	55	#define SR_EAR 3
	56	#define SR_ESR 5
	57	#define SR_FSR 7
	58	#define SR_BTR 0xb
	59	#define SR_EDR 0xd
	60
	61	/* MSR flags. */
	62	#define MSR_BE (1<<0) /* 0x001 */
	63	#define MSR_IE (1<<1) /* 0x002 */
	64	#define MSR_C (1<<2) /* 0x004 */
	65	#define MSR_BIP (1<<3) /* 0x008 */
	66	#define MSR_FSL (1<<4) /* 0x010 */
	67	#define MSR_ICE (1<<5) /* 0x020 */
	68	#define MSR_DZ (1<<6) /* 0x040 */
	69	#define MSR_DCE (1<<7) /* 0x080 */
	70	#define MSR_EE (1<<8) /* 0x100 */
	71	#define MSR_EIP (1<<9) /* 0x200 */
8a84fc6b	72	#define MSR_PVR (1<<10) /* 0x400 */
4acb54ba EI	73	#define MSR_CC (1<<31)
	74
	75	/* Machine State Register (MSR) Fields */
	76	#define MSR_UM (1<<11) /* User Mode */
	77	#define MSR_UMS (1<<12) /* User Mode Save */
	78	#define MSR_VM (1<<13) /* Virtual Mode */
	79	#define MSR_VMS (1<<14) /* Virtual Mode Save */
	80
	81	#define MSR_KERNEL MSR_EE\|MSR_VM
	82	//#define MSR_USER MSR_KERNEL\|MSR_UM\|MSR_IE
	83	#define MSR_KERNEL_VMS MSR_EE\|MSR_VMS
	84	//#define MSR_USER_VMS MSR_KERNEL_VMS\|MSR_UMS\|MSR_IE
	85
	86	/* Exception State Register (ESR) Fields */
	87	#define ESR_DIZ (1<<11) /* Zone Protection */
	88	#define ESR_S (1<<10) /* Store instruction */
	89
85453641 EI	90	#define ESR_ESS_FSL_OFFSET 5
85453641 EI	91
cedb936b EI	92	#define ESR_EC_FSL 0
	93	#define ESR_EC_UNALIGNED_DATA 1
	94	#define ESR_EC_ILLEGAL_OP 2
	95	#define ESR_EC_INSN_BUS 3
	96	#define ESR_EC_DATA_BUS 4
	97	#define ESR_EC_DIVZERO 5
	98	#define ESR_EC_FPU 6
	99	#define ESR_EC_PRIVINSN 7
5818dee5	100	#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
cedb936b EI	101	#define ESR_EC_DATA_STORAGE 8
	102	#define ESR_EC_INSN_STORAGE 9
	103	#define ESR_EC_DATA_TLB 10
	104	#define ESR_EC_INSN_TLB 11
3b584046	105	#define ESR_EC_MASK 31
4acb54ba	106
bdc0bf29 EI	107	/* Floating Point Status Register (FSR) Bits */
	108	#define FSR_IO (1<<4) /* Invalid operation */
	109	#define FSR_DZ (1<<3) /* Divide-by-zero */
	110	#define FSR_OF (1<<2) /* Overflow */
	111	#define FSR_UF (1<<1) /* Underflow */
	112	#define FSR_DO (1<<0) /* Denormalized operand error */
	113
4acb54ba EI	114	/* Version reg. */
	115	/* Basic PVR mask */
	116	#define PVR0_PVR_FULL_MASK 0x80000000
	117	#define PVR0_USE_BARREL_MASK 0x40000000
	118	#define PVR0_USE_DIV_MASK 0x20000000
	119	#define PVR0_USE_HW_MUL_MASK 0x10000000
	120	#define PVR0_USE_FPU_MASK 0x08000000
	121	#define PVR0_USE_EXC_MASK 0x04000000
	122	#define PVR0_USE_ICACHE_MASK 0x02000000
	123	#define PVR0_USE_DCACHE_MASK 0x01000000
	124	#define PVR0_USE_MMU 0x00800000 /* new */
c4374bb7 MS	125	#define PVR0_USE_BTC 0x00400000
	126	#define PVR0_ENDI 0x00200000
	127	#define PVR0_FAULT 0x00100000
4acb54ba EI	128	#define PVR0_VERSION_MASK 0x0000FF00
	129	#define PVR0_USER1_MASK 0x000000FF
	130
	131	/* User 2 PVR mask */
	132	#define PVR1_USER2_MASK 0xFFFFFFFF
	133
	134	/* Configuration PVR masks */
	135	#define PVR2_D_OPB_MASK 0x80000000
	136	#define PVR2_D_LMB_MASK 0x40000000
	137	#define PVR2_I_OPB_MASK 0x20000000
	138	#define PVR2_I_LMB_MASK 0x10000000
	139	#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
	140	#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
	141	#define PVR2_D_PLB_MASK 0x02000000 /* new */
	142	#define PVR2_I_PLB_MASK 0x01000000 /* new */
	143	#define PVR2_INTERCONNECT 0x00800000 /* new */
	144	#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
	145	#define PVR2_USE_FSL_EXC 0x00040000 /* new */
	146	#define PVR2_USE_MSR_INSTR 0x00020000
	147	#define PVR2_USE_PCMP_INSTR 0x00010000
	148	#define PVR2_AREA_OPTIMISED 0x00008000
	149	#define PVR2_USE_BARREL_MASK 0x00004000
	150	#define PVR2_USE_DIV_MASK 0x00002000
	151	#define PVR2_USE_HW_MUL_MASK 0x00001000
	152	#define PVR2_USE_FPU_MASK 0x00000800
	153	#define PVR2_USE_MUL64_MASK 0x00000400
	154	#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
	155	#define PVR2_USE_IPLBEXC 0x00000100
	156	#define PVR2_USE_DPLBEXC 0x00000080
	157	#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
	158	#define PVR2_UNALIGNED_EXC_MASK 0x00000020
	159	#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
	160	#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
	161	#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
	162	#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
	163	#define PVR2_FPU_EXC_MASK 0x00000001
	164
	165	/* Debug and exception PVR masks */
	166	#define PVR3_DEBUG_ENABLED_MASK 0x80000000
	167	#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
	168	#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
	169	#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
	170	#define PVR3_FSL_LINKS_MASK 0x00000380
	171
	172	/* ICache config PVR masks */
	173	#define PVR4_USE_ICACHE_MASK 0x80000000
	174	#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
	175	#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
	176	#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
	177	#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
	178	#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
	179
	180	/* DCache config PVR masks */
	181	#define PVR5_USE_DCACHE_MASK 0x80000000
	182	#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
	183	#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
	184	#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
	185	#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
	186	#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
c4374bb7	187	#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
4acb54ba EI	188
	189	/* ICache base address PVR mask */
	190	#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
	191
	192	/* ICache high address PVR mask */
	193	#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
	194
	195	/* DCache base address PVR mask */
	196	#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
	197
	198	/* DCache high address PVR mask */
	199	#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
	200
	201	/* Target family PVR mask */
	202	#define PVR10_TARGET_FAMILY_MASK 0xFF000000
	203
	204	/* MMU descrtiption */
	205	#define PVR11_USE_MMU 0xC0000000
	206	#define PVR11_MMU_ITLB_SIZE 0x38000000
	207	#define PVR11_MMU_DTLB_SIZE 0x07000000
	208	#define PVR11_MMU_TLB_ACCESS 0x00C00000
7458a432	209	#define PVR11_MMU_ZONES 0x003E0000
4acb54ba EI	210	/* MSR Reset value PVR mask */
	211	#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
	212
	213
	214
	215	/* CPU flags. */
	216
	217	/* Condition codes. */
	218	#define CC_GE 5
	219	#define CC_GT 4
	220	#define CC_LE 3
	221	#define CC_LT 2
	222	#define CC_NE 1
	223	#define CC_EQ 0
	224
	225	#define NB_MMU_MODES 3
85453641 EI	226
	227	#define STREAM_EXCEPTION (1 << 0)
	228	#define STREAM_ATOMIC (1 << 1)
	229	#define STREAM_TEST (1 << 2)
	230	#define STREAM_CONTROL (1 << 3)
	231	#define STREAM_NONBLOCK (1 << 4)
	232
ae7d54d4	233	struct CPUMBState {
4acb54ba EI	234	uint32_t debug;
	235	uint32_t btaken;
	236	uint32_t btarget;
	237	uint32_t bimm;
	238
	239	uint32_t imm;
	240	uint32_t regs[33];
	241	uint32_t sregs[24];
97694c57	242	float_status fp_status;
5818dee5 EI	243	/* Stack protectors. Yes, it's a hw feature. */
5818dee5 EI	244	uint32_t slr, shr;
4acb54ba	245
8cc9b43f PC	246	/* lwx/swx reserved address */
	247	#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
	248	uint32_t res_addr;
	249
4acb54ba	250	/* Internal flags. */
cedb936b EI	251	#define IMM_FLAG 4
cedb936b EI	252	#define MSR_EE_FLAG (1 << 8)
4acb54ba EI	253	#define DRTI_FLAG (1 << 16)
	254	#define DRTE_FLAG (1 << 17)
	255	#define DRTB_FLAG (1 << 18)
	256	#define D_FLAG (1 << 19) /* Bit in ESR. */
68cee38a	257	/* TB dependent CPUMBState. */
fd1dc858	258	#define IFLAGS_TB_MASK (D_FLAG \| IMM_FLAG \| DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)
4acb54ba EI	259	uint32_t iflags;
	260
	261	struct {
	262	uint32_t regs[16];
	263	} pvr;
	264
	265	#if !defined(CONFIG_USER_ONLY)
	266	/* Unified MMU. */
	267	struct microblaze_mmu mmu;
	268	#endif
	269
	270	CPU_COMMON
ae7d54d4	271	};
4acb54ba	272
b77f98ca AF	273	#include "cpu-qom.h"
b77f98ca AF	274
cd0c24f9	275	void mb_tcg_init(void);
b33ab1f7	276	MicroBlazeCPU cpu_mb_init(const char cpu_model);
68cee38a	277	int cpu_mb_exec(CPUMBState *s);
4acb54ba EI	278	/* you can call this signal handler from your SIGBUS and SIGSEGV
	279	signal handlers to inform the virtual CPU of exceptions. non zero
	280	is returned if the signal was handled by the virtual CPU. */
	281	int cpu_mb_signal_handler(int host_signum, void *pinfo,
	282	void *puc);
	283
	284	enum {
	285	CC_OP_DYNAMIC, /* Use env->cc_op */
	286	CC_OP_FLAGS,
	287	CC_OP_CMP,
	288	};
	289
	290	/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
	291	#define TARGET_PAGE_BITS 12
	292	#define MMAP_SHIFT TARGET_PAGE_BITS
	293
52705890 RH	294	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	295	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	296
b33ab1f7 AF	297	static inline CPUMBState cpu_init(const char cpu_model)
	298	{
	299	MicroBlazeCPU *cpu = cpu_mb_init(cpu_model);
	300	if (cpu == NULL) {
	301	return NULL;
	302	}
	303	return &cpu->env;
	304	}
	305
4acb54ba EI	306	#define cpu_exec cpu_mb_exec
	307	#define cpu_gen_code cpu_mb_gen_code
	308	#define cpu_signal_handler cpu_mb_signal_handler
	309
4acb54ba EI	310	/* MMU modes definitions */
	311	#define MMU_MODE0_SUFFIX _nommu
	312	#define MMU_MODE1_SUFFIX _kernel
	313	#define MMU_MODE2_SUFFIX _user
	314	#define MMU_NOMMU_IDX 0
	315	#define MMU_KERNEL_IDX 1
	316	#define MMU_USER_IDX 2
	317	/* See NB_MMU_MODES further up the file. */
	318
68cee38a	319	static inline int cpu_mmu_index (CPUMBState *env)
4acb54ba EI	320	{
	321	/* Are we in nommu mode?. */
	322	if (!(env->sregs[SR_MSR] & MSR_VM))
	323	return MMU_NOMMU_IDX;
	324
	325	if (env->sregs[SR_MSR] & MSR_UM)
	326	return MMU_USER_IDX;
	327	return MMU_KERNEL_IDX;
	328	}
	329
68cee38a	330	int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
97b348e7	331	int mmu_idx);
0b5c1ce8	332	#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
4acb54ba	333
68cee38a	334	static inline int cpu_interrupts_enabled(CPUMBState *env)
4acb54ba EI	335	{
	336	return env->sregs[SR_MSR] & MSR_IE;
	337	}
	338
022c62cb	339	#include "exec/cpu-all.h"
4acb54ba	340
68cee38a	341	static inline target_ulong cpu_get_pc(CPUMBState *env)
4acb54ba EI	342	{
	343	return env->sregs[SR_PC];
	344	}
	345
68cee38a	346	static inline void cpu_get_tb_cpu_state(CPUMBState env, target_ulong pc,
4acb54ba EI	347	target_ulong cs_base, int flags)
	348	{
	349	*pc = env->sregs[SR_PC];
	350	*cs_base = 0;
fd1dc858 EI	351	*flags = (env->iflags & IFLAGS_TB_MASK) \|
fd1dc858 EI	352	(env->sregs[SR_MSR] & (MSR_UM \| MSR_VM \| MSR_EE));
4acb54ba	353	}
faed1c2a	354
3c7b48b7	355	#if !defined(CONFIG_USER_ONLY)
c658b94f AF	356	void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
	357	bool is_write, bool is_exec, int is_asi,
	358	unsigned size);
4acb54ba	359	#endif
f081c76c	360
3993c6bd	361	static inline bool cpu_has_work(CPUState *cpu)
f081c76c	362	{
259186a7	363	return cpu->interrupt_request & (CPU_INTERRUPT_HARD \| CPU_INTERRUPT_NMI);
f081c76c BS	364	}
f081c76c BS	365
022c62cb	366	#include "exec/exec-all.h"
f081c76c	367
68cee38a	368	static inline void cpu_pc_from_tb(CPUMBState env, TranslationBlock tb)
f081c76c BS	369	{
	370	env->sregs[SR_PC] = tb->pc;
	371	}
	372
3c7b48b7	373	#endif