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Commit | Line | Data |
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488cb996 GH |
1 | /* |
2 | * QEMU 16550A UART emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2008 Citrix Systems, Inc. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
175de524 | 25 | |
cb9c377f | 26 | #ifndef HW_SERIAL_H |
175de524 | 27 | #define HW_SERIAL_H |
488cb996 | 28 | |
4d43a603 | 29 | #include "chardev/char-fe.h" |
022c62cb | 30 | #include "exec/memory.h" |
8e8638fa | 31 | #include "qemu/fifo8.h" |
8228e353 | 32 | #include "chardev/char.h" |
7781b88e | 33 | #include "hw/sysbus.h" |
488cb996 GH |
34 | |
35 | #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ | |
36 | ||
1451b404 | 37 | typedef struct SerialState { |
7781b88e MAL |
38 | DeviceState parent; |
39 | ||
488cb996 GH |
40 | uint16_t divider; |
41 | uint8_t rbr; /* receive register */ | |
42 | uint8_t thr; /* transmit holding register */ | |
43 | uint8_t tsr; /* transmit shift register */ | |
44 | uint8_t ier; | |
45 | uint8_t iir; /* read only */ | |
46 | uint8_t lcr; | |
47 | uint8_t mcr; | |
48 | uint8_t lsr; /* read only */ | |
49 | uint8_t msr; /* read only */ | |
50 | uint8_t scr; | |
51 | uint8_t fcr; | |
52 | uint8_t fcr_vmstate; /* we can't write directly this value | |
53 | it has side effects */ | |
54 | /* NOTE: this hidden state is necessary for tx irq generation as | |
55 | it can be reset while reading iir */ | |
56 | int thr_ipending; | |
57 | qemu_irq irq; | |
becdfa00 | 58 | CharBackend chr; |
488cb996 | 59 | int last_break_enable; |
96651db4 | 60 | uint32_t baudbase; |
807464d8 | 61 | uint32_t tsr_retry; |
a1df76da | 62 | guint watch_tag; |
488cb996 GH |
63 | uint32_t wakeup; |
64 | ||
65 | /* Time when the last byte was successfully sent out of the tsr */ | |
66 | uint64_t last_xmit_ts; | |
8e8638fa PC |
67 | Fifo8 recv_fifo; |
68 | Fifo8 xmit_fifo; | |
69 | /* Interrupt trigger level for recv_fifo */ | |
70 | uint8_t recv_fifo_itl; | |
488cb996 | 71 | |
1246b259 | 72 | QEMUTimer *fifo_timeout_timer; |
488cb996 | 73 | int timeout_ipending; /* timeout interrupt pending state */ |
488cb996 GH |
74 | |
75 | uint64_t char_transmit_time; /* time to transmit a char in ticks */ | |
76 | int poll_msl; | |
77 | ||
1246b259 | 78 | QEMUTimer *modem_status_poll; |
488cb996 | 79 | MemoryRegion io; |
1451b404 | 80 | } SerialState; |
488cb996 | 81 | |
490a9d9b MAL |
82 | typedef struct SerialMM { |
83 | SysBusDevice parent; | |
84 | ||
85 | SerialState serial; | |
86 | ||
17fd1a64 | 87 | uint8_t regshift; |
80b2eed9 | 88 | uint8_t endianness; |
490a9d9b MAL |
89 | } SerialMM; |
90 | ||
10315a70 MAL |
91 | typedef struct SerialIO { |
92 | SysBusDevice parent; | |
93 | ||
94 | SerialState serial; | |
95 | } SerialIO; | |
96 | ||
488cb996 GH |
97 | extern const VMStateDescription vmstate_serial; |
98 | extern const MemoryRegionOps serial_io_ops; | |
99 | ||
488cb996 GH |
100 | void serial_set_frequency(SerialState *s, uint32_t frequency); |
101 | ||
7781b88e MAL |
102 | #define TYPE_SERIAL "serial" |
103 | #define SERIAL(s) OBJECT_CHECK(SerialState, (s), TYPE_SERIAL) | |
104 | ||
490a9d9b MAL |
105 | #define TYPE_SERIAL_MM "serial-mm" |
106 | #define SERIAL_MM(s) OBJECT_CHECK(SerialMM, (s), TYPE_SERIAL_MM) | |
107 | ||
10315a70 MAL |
108 | #define TYPE_SERIAL_IO "serial-io" |
109 | #define SERIAL_IO(s) OBJECT_CHECK(SerialIO, (s), TYPE_SERIAL_IO) | |
110 | ||
490a9d9b | 111 | SerialMM *serial_mm_init(MemoryRegion *address_space, |
17fd1a64 | 112 | hwaddr base, int regshift, |
490a9d9b MAL |
113 | qemu_irq irq, int baudbase, |
114 | Chardev *chr, enum device_endian end); | |
488cb996 GH |
115 | |
116 | /* serial-isa.c */ | |
def337ff PM |
117 | |
118 | #define MAX_ISA_SERIAL_PORTS 4 | |
119 | ||
eeceb084 | 120 | #define TYPE_ISA_SERIAL "isa-serial" |
4496dc49 | 121 | void serial_hds_isa_init(ISABus *bus, int from, int to); |
cb9c377f PB |
122 | |
123 | #endif |