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Actually enable 64bit configuration.
[qemu.git] / target-mips / op_helper_mem.c
CommitLineData
3a3f24fc
TS		 1#undef DEBUG_OP
2
9f25f11f
FB		 3#ifdef TARGET_WORDS_BIGENDIAN
4#define GET_LMASK(v) ((v) & 3)
5#else
6#define GET_LMASK(v) (((v) & 3) ^ 3)
7#endif
8
4ad40f36 9void glue(do_lwl, MEMSUFFIX) (uint32_t tmp)
6af0bf9c
FB		 10{
11#if defined (DEBUG_OP)
12 target_ulong sav = T0;
13#endif
6af0bf9c 14
9f25f11f 15 switch (GET_LMASK(T0)) {
6af0bf9c 16 case 0:
3a3f24fc 17 T0 = (int32_t)tmp;
6af0bf9c
FB		 18 break;
19 case 1:
3a3f24fc 20 T0 = (int32_t)((tmp << 8) | (T1 & 0x000000FF));
6af0bf9c
FB		 21 break;
22 case 2:
3a3f24fc 23 T0 = (int32_t)((tmp << 16) | (T1 & 0x0000FFFF));
6af0bf9c
FB		 24 break;
25 case 3:
3a3f24fc 26 T0 = (int32_t)((tmp << 24) | (T1 & 0x00FFFFFF));
6af0bf9c
FB		 27 break;
28 }
29#if defined (DEBUG_OP)
30 if (logfile) {
3594c774 31 fprintf(logfile, "%s: " TARGET_FMT_lx " - %08x " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
6af0bf9c
FB		 32 __func__, sav, tmp, T1, T0);
33 }
34#endif
35 RETURN();
36}
37
4ad40f36 38void glue(do_lwr, MEMSUFFIX) (uint32_t tmp)
6af0bf9c
FB		 39{
40#if defined (DEBUG_OP)
41 target_ulong sav = T0;
42#endif
6af0bf9c 43
9f25f11f 44 switch (GET_LMASK(T0)) {
6af0bf9c 45 case 0:
3a3f24fc 46 T0 = (int32_t)((tmp >> 24) | (T1 & 0xFFFFFF00));
6af0bf9c
FB		 47 break;
48 case 1:
3a3f24fc 49 T0 = (int32_t)((tmp >> 16) | (T1 & 0xFFFF0000));
6af0bf9c
FB		 50 break;
51 case 2:
3a3f24fc 52 T0 = (int32_t)((tmp >> 8) | (T1 & 0xFF000000));
6af0bf9c
FB		 53 break;
54 case 3:
3a3f24fc 55 T0 = (int32_t)tmp;
6af0bf9c
FB		 56 break;
57 }
58#if defined (DEBUG_OP)
59 if (logfile) {
3594c774 60 fprintf(logfile, "%s: " TARGET_FMT_lx " - %08x " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
6af0bf9c
FB		 61 __func__, sav, tmp, T1, T0);
62 }
63#endif
64 RETURN();
65}
66
4ad40f36 67uint32_t glue(do_swl, MEMSUFFIX) (uint32_t tmp)
6af0bf9c
FB		 68{
69#if defined (DEBUG_OP)
c570fd16 70 target_ulong sav = tmp;
6af0bf9c 71#endif
6af0bf9c 72
9f25f11f 73 switch (GET_LMASK(T0)) {
6af0bf9c 74 case 0:
3a3f24fc 75 tmp = (int32_t)T1;
6af0bf9c
FB		 76 break;
77 case 1:
3a3f24fc 78 tmp = (int32_t)((tmp & 0xFF000000) | ((uint32_t)T1 >> 8));
6af0bf9c
FB		 79 break;
80 case 2:
3a3f24fc 81 tmp = (int32_t)((tmp & 0xFFFF0000) | ((uint32_t)T1 >> 16));
6af0bf9c
FB		 82 break;
83 case 3:
3a3f24fc 84 tmp = (int32_t)((tmp & 0xFFFFFF00) | ((uint32_t)T1 >> 24));
6af0bf9c
FB		 85 break;
86 }
6af0bf9c
FB		 87#if defined (DEBUG_OP)
88 if (logfile) {
3594c774 89 fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => %08x\n",
6af0bf9c
FB		 90 __func__, T0, sav, T1, tmp);
91 }
92#endif
93 RETURN();
4ad40f36 94 return tmp;
6af0bf9c
FB		 95}
96
4ad40f36 97uint32_t glue(do_swr, MEMSUFFIX) (uint32_t tmp)
6af0bf9c
FB		 98{
99#if defined (DEBUG_OP)
c570fd16 100 target_ulong sav = tmp;
6af0bf9c 101#endif
6af0bf9c 102
9f25f11f 103 switch (GET_LMASK(T0)) {
6af0bf9c 104 case 0:
3a3f24fc 105 tmp = (int32_t)((tmp & 0x00FFFFFF) | (T1 << 24));
6af0bf9c
FB		 106 break;
107 case 1:
3a3f24fc 108 tmp = (int32_t)((tmp & 0x0000FFFF) | (T1 << 16));
6af0bf9c
FB		 109 break;
110 case 2:
3a3f24fc 111 tmp = (int32_t)((tmp & 0x000000FF) | (T1 << 8));
6af0bf9c
FB		 112 break;
113 case 3:
3a3f24fc 114 tmp = (int32_t)T1;
6af0bf9c
FB		 115 break;
116 }
6af0bf9c
FB		 117#if defined (DEBUG_OP)
118 if (logfile) {
3594c774 119 fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => %08x\n",
6af0bf9c
FB		 120 __func__, T0, sav, T1, tmp);
121 }
122#endif
123 RETURN();
4ad40f36 124 return tmp;
6af0bf9c 125}
c570fd16 126
60aa19ab 127#ifdef TARGET_MIPS64
c570fd16
TS		 128
129# ifdef TARGET_WORDS_BIGENDIAN
130#define GET_LMASK64(v) ((v) & 4)
131#else
132#define GET_LMASK64(v) (((v) & 4) ^ 4)
133#endif
134
135void glue(do_ldl, MEMSUFFIX) (uint64_t tmp)
136{
137#if defined (DEBUG_OP)
138 target_ulong sav = T0;
139#endif
140
141 switch (GET_LMASK64(T0)) {
142 case 0:
143 T0 = tmp;
144 break;
145 case 1:
146 T0 = (tmp << 8) | (T1 & 0x00000000000000FFULL);
147 break;
148 case 2:
149 T0 = (tmp << 16) | (T1 & 0x000000000000FFFFULL);
150 break;
151 case 3:
152 T0 = (tmp << 24) | (T1 & 0x0000000000FFFFFFULL);
153 break;
154 case 4:
155 T0 = (tmp << 32) | (T1 & 0x00000000FFFFFFFFULL);
156 break;
157 case 5:
158 T0 = (tmp << 40) | (T1 & 0x000000FFFFFFFFFFULL);
159 break;
160 case 6:
161 T0 = (tmp << 48) | (T1 & 0x0000FFFFFFFFFFFFULL);
162 break;
163 case 7:
164 T0 = (tmp << 56) | (T1 & 0x00FFFFFFFFFFFFFFULL);
165 break;
166 }
167#if defined (DEBUG_OP)
168 if (logfile) {
3594c774 169 fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
c570fd16
TS		 170 __func__, sav, tmp, T1, T0);
171 }
172#endif
173 RETURN();
174}
175
176void glue(do_ldr, MEMSUFFIX) (uint64_t tmp)
177{
178#if defined (DEBUG_OP)
179 target_ulong sav = T0;
180#endif
181
182 switch (GET_LMASK64(T0)) {
183 case 0:
184 T0 = (tmp >> 56) | (T1 & 0xFFFFFFFFFFFFFF00ULL);
185 break;
186 case 1:
187 T0 = (tmp >> 48) | (T1 & 0xFFFFFFFFFFFF0000ULL);
188 break;
189 case 2:
190 T0 = (tmp >> 40) | (T1 & 0xFFFFFFFFFF000000ULL);
191 break;
192 case 3:
193 T0 = (tmp >> 32) | (T1 & 0xFFFFFFFF00000000ULL);
194 break;
195 case 4:
196 T0 = (tmp >> 24) | (T1 & 0xFFFFFF0000000000ULL);
197 break;
198 case 5:
199 T0 = (tmp >> 16) | (T1 & 0xFFFF000000000000ULL);
200 break;
201 case 6:
202 T0 = (tmp >> 8) | (T1 & 0xFF00000000000000ULL);
203 break;
204 case 7:
205 T0 = tmp;
206 break;
207 }
208#if defined (DEBUG_OP)
209 if (logfile) {
3594c774 210 fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
c570fd16
TS		 211 __func__, sav, tmp, T1, T0);
212 }
213#endif
214 RETURN();
215}
216
217uint64_t glue(do_sdl, MEMSUFFIX) (uint64_t tmp)
218{
219#if defined (DEBUG_OP)
220 target_ulong sav = tmp;
221#endif
222
223 switch (GET_LMASK64(T0)) {
224 case 0:
225 tmp = T1;
226 break;
227 case 1:
228 tmp = (tmp & 0xFF00000000000000ULL) | (T1 >> 8);
229 break;
230 case 2:
231 tmp = (tmp & 0xFFFF000000000000ULL) | (T1 >> 16);
232 break;
233 case 3:
234 tmp = (tmp & 0xFFFFFF0000000000ULL) | (T1 >> 24);
235 break;
236 case 4:
237 tmp = (tmp & 0xFFFFFFFF00000000ULL) | (T1 >> 32);
238 break;
239 case 5:
240 tmp = (tmp & 0xFFFFFFFFFF000000ULL) | (T1 >> 40);
241 break;
242 case 6:
243 tmp = (tmp & 0xFFFFFFFFFFFF0000ULL) | (T1 >> 48);
244 break;
245 case 7:
246 tmp = (tmp & 0xFFFFFFFFFFFFFF00ULL) | (T1 >> 56);
247 break;
248 }
249#if defined (DEBUG_OP)
250 if (logfile) {
3594c774 251 fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
c570fd16
TS		 252 __func__, T0, sav, T1, tmp);
253 }
254#endif
255 RETURN();
256 return tmp;
257}
258
259uint64_t glue(do_sdr, MEMSUFFIX) (uint64_t tmp)
260{
261#if defined (DEBUG_OP)
262 target_ulong sav = tmp;
263#endif
264
265 switch (GET_LMASK64(T0)) {
266 case 0:
267 tmp = (tmp & 0x00FFFFFFFFFFFFFFULL) | (T1 << 56);
268 break;
269 case 1:
270 tmp = (tmp & 0x0000FFFFFFFFFFFFULL) | (T1 << 48);
271 break;
272 case 2:
273 tmp = (tmp & 0x000000FFFFFFFFFFULL) | (T1 << 40);
274 break;
275 case 3:
276 tmp = (tmp & 0x00000000FFFFFFFFULL) | (T1 << 32);
277 break;
278 case 4:
279 tmp = (tmp & 0x0000000000FFFFFFULL) | (T1 << 24);
280 break;
281 case 5:
282 tmp = (tmp & 0x000000000000FFFFULL) | (T1 << 16);
283 break;
284 case 6:
285 tmp = (tmp & 0x00000000000000FFULL) | (T1 << 8);
286 break;
287 case 7:
288 tmp = T1;
289 break;
290 }
291#if defined (DEBUG_OP)
292 if (logfile) {
3594c774 293 fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
c570fd16
TS		 294 __func__, T0, sav, T1, tmp);
295 }
296#endif
297 RETURN();
298 return tmp;
299}
300
60aa19ab 301#endif /* TARGET_MIPS64 */
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