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target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT
[qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
30f4b05b 25#include "qapi/error.h"
072ed5f2 26#include "qemu/error-report.h"
33c11879 27#include "cpu.h"
715d4b96 28#include "cpu-models.h"
1de7afc9 29#include "qemu/timer.h"
9c17d615 30#include "sysemu/sysemu.h"
b3946626 31#include "sysemu/hw_accel.h"
d76d1650 32#include "kvm_ppc.h"
9c17d615
PB		 33#include "sysemu/cpus.h"
34#include "sysemu/device_tree.h"
d5aea6f3 35#include "mmu-hash64.h"
d76d1650 36
f61b4bed 37#include "hw/sysbus.h"
0d09e41a 38#include "hw/ppc/spapr.h"
7ebaf795 39#include "hw/ppc/spapr_cpu_core.h"
98a8b524 40#include "hw/ppc/ppc.h"
31f2cb8f 41#include "sysemu/watchdog.h"
b36f100e 42#include "trace.h"
88365d17 43#include "exec/gdbstub.h"
4c663752 44#include "exec/memattrs.h"
9c607668 45#include "exec/ram_addr.h"
2d103aae 46#include "sysemu/hostmem.h"
f348b6d1 47#include "qemu/cutils.h"
9c607668 48#include "qemu/mmap-alloc.h"
f3d9f303 49#include "elf.h"
c64abd1f 50#include "sysemu/kvm_int.h"
f61b4bed 51
eadaada1
AG		 52#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
53
94a8d39a
JK		 54const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
55 KVM_CAP_LAST_INFO
56};
57
c995e942
DG		 58static int cap_interrupt_unset;
59static int cap_interrupt_level;
90dc8812 60static int cap_segstate;
90dc8812 61static int cap_booke_sregs;
e97c3636 62static int cap_ppc_smt;
fa98fbfc 63static int cap_ppc_smt_possible;
0f5cb298 64static int cap_spapr_tce;
d6ee2a7c 65static int cap_spapr_tce_64;
da95324e 66static int cap_spapr_multitce;
9bb62a07 67static int cap_spapr_vfio;
f1af19d7 68static int cap_hior;
d67d40ea 69static int cap_one_reg;
3b961124 70static int cap_epr;
31f2cb8f 71static int cap_ppc_watchdog;
9b00ea49 72static int cap_papr;
e68cb8b4 73static int cap_htab_fd;
87a91de6 74static int cap_fixup_hcalls;
bac3bf28 75static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 76static int cap_mmu_radix;
77static int cap_mmu_hash_v3;
38afd772 78static int cap_xive;
b55d295e 79static int cap_resize_hpt;
c363a37a 80static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 81static int cap_ppc_safe_cache;
82static int cap_ppc_safe_bounds_check;
83static int cap_ppc_safe_indirect_branch;
8ff43ee4 84static int cap_ppc_count_cache_flush_assist;
b9a477b7 85static int cap_ppc_nested_kvm_hv;
7d050527 86static int cap_large_decr;
fc87e185 87
3c902d44
BB		 88static uint32_t debug_inst_opcode;
89
c995e942
DG		 90/*
91 * XXX We have a race condition where we actually have a level triggered
c821c2bd
AG		 92 * interrupt, but the infrastructure can't expose that yet, so the guest
93 * takes but ignores it, goes to sleep and never gets notified that there's
94 * still an interrupt pending.
c6a94ba5 95 *
c821c2bd
AG		 96 * As a quick workaround, let's just wake up again 20 ms after we injected
97 * an interrupt. That way we can assure that we're always reinjecting
98 * interrupts in case the guest swallowed them.
c6a94ba5
AG		 99 */
100static QEMUTimer *idle_timer;
101
d5a68146 102static void kvm_kick_cpu(void *opaque)
c6a94ba5 103{
d5a68146 104 PowerPCCPU *cpu = opaque;
d5a68146 105
c08d7424 106 qemu_cpu_kick(CPU(cpu));
c6a94ba5
AG		 107}
108
c995e942
DG		 109/*
110 * Check whether we are running with KVM-PR (instead of KVM-HV). This
96c9cff0
TH		 111 * should only be used for fallback tests - generally we should use
112 * explicit capabilities for the features we want, rather than
c995e942
DG		 113 * assuming what is/isn't available depending on the KVM variant.
114 */
96c9cff0
TH		 115static bool kvmppc_is_pr(KVMState *ks)
116{
117 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 118 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 119}
120
2e9c10eb 121static int kvm_ppc_register_host_cpu_type(MachineState *ms);
8acc2ae5 122static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 123static int kvmppc_get_dec_bits(void);
5ba4576b 124
b16565b3 125int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 126{
fc87e185 127 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
fc87e185 128 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
90dc8812 129 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 130 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 131 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 132 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 133 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 134 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 135 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 136 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 137 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 138 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 139 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
c995e942
DG		 140 /*
141 * Note: we don't set cap_papr here, because this capability is
142 * only activated after this by kvmppc_set_papr()
143 */
6977afda 144 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 145 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 146 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 147 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 148 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
149 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
38afd772 150 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
b55d295e 151 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 152 kvmppc_get_cpu_characteristics(s);
b9a477b7 153 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 154 cap_large_decr = kvmppc_get_dec_bits();
c363a37a
DHB		 155 /*
156 * Note: setting it to false because there is not such capability
157 * in KVM at this moment.
158 *
159 * TODO: call kvm_vm_check_extension() with the right capability
c995e942
DG		 160 * after the kernel starts implementing it.
161 */
c363a37a 162 cap_ppc_pvr_compat = false;
fc87e185
AG		 163
164 if (!cap_interrupt_level) {
165 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
166 "VM to stall at times!\n");
167 }
168
2e9c10eb 169 kvm_ppc_register_host_cpu_type(ms);
5ba4576b 170
d76d1650
AJ		 171 return 0;
172}
173
d525ffab
PB		 174int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
175{
176 return 0;
177}
178
1bc22652 179static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 180{
1bc22652
AF		 181 CPUPPCState *cenv = &cpu->env;
182 CPUState *cs = CPU(cpu);
861bbc80 183 struct kvm_sregs sregs;
5666ca4a
SW		 184 int ret;
185
186 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
c995e942
DG		 187 /*
188 * What we're really trying to say is "if we're on BookE, we
189 * use the native PVR for now". This is the only sane way to
190 * check it though, so we potentially confuse users that they
191 * can run BookE guests on BookS. Let's hope nobody dares
192 * enough :)
193 */
5666ca4a
SW		 194 return 0;
195 } else {
90dc8812 196 if (!cap_segstate) {
64e07be5
AG		 197 fprintf(stderr, "kvm error: missing PVR setting capability\n");
198 return -ENOSYS;
5666ca4a 199 }
5666ca4a
SW		 200 }
201
1bc22652 202 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 203 if (ret) {
204 return ret;
205 }
861bbc80
AG		 206
207 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 208 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 209}
210
93dd5e85 211/* Set up a shared TLB array with KVM */
1bc22652 212static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 213{
1bc22652
AF		 214 CPUPPCState *env = &cpu->env;
215 CPUState *cs = CPU(cpu);
93dd5e85
SW		 216 struct kvm_book3e_206_tlb_params params = {};
217 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 218 unsigned int entries = 0;
219 int ret, i;
220
221 if (!kvm_enabled() ||
a60f24b5 222 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 223 return 0;
224 }
225
226 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
227
228 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
229 params.tlb_sizes[i] = booke206_tlb_size(env, i);
230 params.tlb_ways[i] = booke206_tlb_ways(env, i);
231 entries += params.tlb_sizes[i];
232 }
233
234 assert(entries == env->nb_tlb);
235 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
236
237 env->tlb_dirty = true;
238
239 cfg.array = (uintptr_t)env->tlb.tlbm;
240 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
241 cfg.params = (uintptr_t)&params;
242 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
243
48add816 244 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 245 if (ret < 0) {
246 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
247 __func__, strerror(-ret));
248 return ret;
249 }
250
251 env->kvm_sw_tlb = true;
252 return 0;
253}
254
4656e1f0
BH		 255
256#if defined(TARGET_PPC64)
ab256960 257static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 258{
71d0f1ea 259 int ret;
a60f24b5 260
ab256960
GK		 261 assert(kvm_state != NULL);
262
263 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 264 error_setg(errp, "KVM doesn't expose the MMU features it supports");
265 error_append_hint(errp, "Consider switching to a newer KVM\n");
266 return;
4656e1f0 267 }
4656e1f0 268
ab256960 269 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 270 if (ret == 0) {
271 return;
4656e1f0
BH		 272 }
273
71d0f1ea
GK		 274 error_setg_errno(errp, -ret,
275 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 276}
277
c64abd1f
SB		 278struct ppc_radix_page_info *kvm_get_radix_page_info(void)
279{
280 KVMState *s = KVM_STATE(current_machine->accelerator);
281 struct ppc_radix_page_info *radix_page_info;
282 struct kvm_ppc_rmmu_info rmmu_info;
283 int i;
284
285 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
286 return NULL;
287 }
288 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
289 return NULL;
290 }
291 radix_page_info = g_malloc0(sizeof(*radix_page_info));
292 radix_page_info->count = 0;
293 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
294 if (rmmu_info.ap_encodings[i]) {
295 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
296 radix_page_info->count++;
297 }
298 }
299 return radix_page_info;
300}
301
b4db5413
SJS		 302target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
303 bool radix, bool gtse,
304 uint64_t proc_tbl)
305{
306 CPUState *cs = CPU(cpu);
307 int ret;
308 uint64_t flags = 0;
309 struct kvm_ppc_mmuv3_cfg cfg = {
310 .process_table = proc_tbl,
311 };
312
313 if (radix) {
314 flags |= KVM_PPC_MMUV3_RADIX;
315 }
316 if (gtse) {
317 flags |= KVM_PPC_MMUV3_GTSE;
318 }
319 cfg.flags = flags;
320 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
321 switch (ret) {
322 case 0:
323 return H_SUCCESS;
324 case -EINVAL:
325 return H_PARAMETER;
326 case -ENODEV:
327 return H_NOT_AVAILABLE;
328 default:
329 return H_HARDWARE;
330 }
331}
332
24c6863c
DG		 333bool kvmppc_hpt_needs_host_contiguous_pages(void)
334{
24c6863c
DG		 335 static struct kvm_ppc_smmu_info smmu_info;
336
337 if (!kvm_enabled()) {
338 return false;
339 }
340
ab256960 341 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 342 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
343}
344
e5ca28ec 345void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 346{
e5ca28ec 347 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 348 int iq, ik, jq, jk;
71d0f1ea 349 Error *local_err = NULL;
4656e1f0 350
e5ca28ec
DG		 351 /* For now, we only have anything to check on hash64 MMUs */
352 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 353 return;
354 }
355
ab256960 356 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 357 if (local_err) {
358 error_propagate(errp, local_err);
359 return;
360 }
4656e1f0 361
e5ca28ec
DG		 362 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
363 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
364 error_setg(errp,
365 "KVM does not support 1TiB segments which guest expects");
366 return;
df587133 367 }
4656e1f0 368
e5ca28ec
DG		 369 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
370 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
371 smmu_info.slb_size, cpu->hash64_opts->slb_size);
372 return;
90da0d5a
BH		 373 }
374
08215d8f 375 /*
e5ca28ec
DG		 376 * Verify that every pagesize supported by the cpu model is
377 * supported by KVM with the same encodings
08215d8f 378 */
e5ca28ec 379 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 380 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 381 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 382
e5ca28ec
DG		 383 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
384 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 385 break;
386 }
387 }
e5ca28ec
DG		 388 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
389 error_setg(errp, "KVM doesn't support for base page shift %u",
390 qsps->page_shift);
391 return;
392 }
393
394 ksps = &smmu_info.sps[ik];
395 if (ksps->slb_enc != qsps->slb_enc) {
396 error_setg(errp,
397"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
398 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
399 return;
400 }
401
402 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
403 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
404 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
405 break;
406 }
407 }
408
409 if (jk >= ARRAY_SIZE(ksps->enc)) {
410 error_setg(errp, "KVM doesn't support page shift %u/%u",
411 qsps->enc[jq].page_shift, qsps->page_shift);
412 return;
413 }
414 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
415 error_setg(errp,
416"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
417 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
418 qsps->page_shift, qsps->enc[jq].pte_enc);
419 return;
420 }
4656e1f0
BH		 421 }
422 }
4656e1f0 423
e5ca28ec 424 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
c995e942
DG		 425 /*
426 * Mostly what guest pagesizes we can use are related to the
e5ca28ec
DG		 427 * host pages used to map guest RAM, which is handled in the
428 * platform code. Cache-Inhibited largepages (64k) however are
429 * used for I/O, so if they're mapped to the host at all it
430 * will be a normal mapping, not a special hugepage one used
c995e942
DG		 431 * for RAM.
432 */
e5ca28ec
DG		 433 if (getpagesize() < 0x10000) {
434 error_setg(errp,
435 "KVM can't supply 64kiB CI pages, which guest expects");
436 }
437 }
4656e1f0 438}
4656e1f0
BH		 439#endif /* !defined (TARGET_PPC64) */
440
b164e48e
EH		 441unsigned long kvm_arch_vcpu_id(CPUState *cpu)
442{
2e886fb3 443 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 444}
445
c995e942
DG		 446/*
447 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
448 * only 1 watchpoint, so array size of 4 is sufficient for now.
88365d17
BB		 449 */
450#define MAX_HW_BKPTS 4
451
452static struct HWBreakpoint {
453 target_ulong addr;
454 int type;
455} hw_debug_points[MAX_HW_BKPTS];
456
457static CPUWatchpoint hw_watchpoint;
458
459/* Default there is no breakpoint and watchpoint supported */
460static int max_hw_breakpoint;
461static int max_hw_watchpoint;
462static int nb_hw_breakpoint;
463static int nb_hw_watchpoint;
464
465static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
466{
467 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
468 max_hw_breakpoint = 2;
469 max_hw_watchpoint = 2;
470 }
471
472 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
473 fprintf(stderr, "Error initializing h/w breakpoints\n");
474 return;
475 }
476}
477
20d695a9 478int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 479{
20d695a9
AF		 480 PowerPCCPU *cpu = POWERPC_CPU(cs);
481 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 482 int ret;
483
4656e1f0 484 /* Synchronize sregs with kvm */
1bc22652 485 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 486 if (ret) {
388e47c7
TH		 487 if (ret == -EINVAL) {
488 error_report("Register sync failed... If you're using kvm-hv.ko,"
489 " only \"-cpu host\" is possible");
490 }
5666ca4a
SW		 491 return ret;
492 }
861bbc80 493
bc72ad67 494 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu);
c821c2bd 495
93dd5e85
SW		 496 switch (cenv->mmu_model) {
497 case POWERPC_MMU_BOOKE206:
7f516c96 498 /* This target supports access to KVM's guest TLB */
1bc22652 499 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 500 break;
7f516c96
TH		 501 case POWERPC_MMU_2_07:
502 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
c995e942
DG		 503 /*
504 * KVM-HV has transactional memory on POWER8 also without
505 * the KVM_CAP_PPC_HTM extension, so enable it here
506 * instead as long as it's availble to userspace on the
507 * host.
508 */
f3d9f303
SB		 509 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
510 cap_htm = true;
511 }
7f516c96
TH		 512 }
513 break;
93dd5e85
SW		 514 default:
515 break;
516 }
517
3c902d44 518 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 519 kvmppc_hw_debug_points_init(cenv);
3c902d44 520
861bbc80 521 return ret;
d76d1650
AJ		 522}
523
1bc22652 524static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 525{
1bc22652
AF		 526 CPUPPCState *env = &cpu->env;
527 CPUState *cs = CPU(cpu);
93dd5e85
SW		 528 struct kvm_dirty_tlb dirty_tlb;
529 unsigned char *bitmap;
530 int ret;
531
532 if (!env->kvm_sw_tlb) {
533 return;
534 }
535
536 bitmap = g_malloc((env->nb_tlb + 7) / 8);
537 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
538
539 dirty_tlb.bitmap = (uintptr_t)bitmap;
540 dirty_tlb.num_dirty = env->nb_tlb;
541
1bc22652 542 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 543 if (ret) {
544 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
545 __func__, strerror(-ret));
546 }
547
548 g_free(bitmap);
549}
550
d67d40ea
DG		 551static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
552{
553 PowerPCCPU *cpu = POWERPC_CPU(cs);
554 CPUPPCState *env = &cpu->env;
555 union {
556 uint32_t u32;
557 uint64_t u64;
558 } val;
559 struct kvm_one_reg reg = {
560 .id = id,
561 .addr = (uintptr_t) &val,
562 };
563 int ret;
564
565 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
566 if (ret != 0) {
b36f100e 567 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 568 } else {
569 switch (id & KVM_REG_SIZE_MASK) {
570 case KVM_REG_SIZE_U32:
571 env->spr[spr] = val.u32;
572 break;
573
574 case KVM_REG_SIZE_U64:
575 env->spr[spr] = val.u64;
576 break;
577
578 default:
579 /* Don't handle this size yet */
580 abort();
581 }
582 }
583}
584
585static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
586{
587 PowerPCCPU *cpu = POWERPC_CPU(cs);
588 CPUPPCState *env = &cpu->env;
589 union {
590 uint32_t u32;
591 uint64_t u64;
592 } val;
593 struct kvm_one_reg reg = {
594 .id = id,
595 .addr = (uintptr_t) &val,
596 };
597 int ret;
598
599 switch (id & KVM_REG_SIZE_MASK) {
600 case KVM_REG_SIZE_U32:
601 val.u32 = env->spr[spr];
602 break;
603
604 case KVM_REG_SIZE_U64:
605 val.u64 = env->spr[spr];
606 break;
607
608 default:
609 /* Don't handle this size yet */
610 abort();
611 }
612
613 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
614 if (ret != 0) {
b36f100e 615 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 616 }
617}
618
70b79849
DG		 619static int kvm_put_fp(CPUState *cs)
620{
621 PowerPCCPU *cpu = POWERPC_CPU(cs);
622 CPUPPCState *env = &cpu->env;
623 struct kvm_one_reg reg;
624 int i;
625 int ret;
626
627 if (env->insns_flags & PPC_FLOAT) {
628 uint64_t fpscr = env->fpscr;
629 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
630
631 reg.id = KVM_REG_PPC_FPSCR;
632 reg.addr = (uintptr_t)&fpscr;
633 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
634 if (ret < 0) {
8d83cbf1 635 trace_kvm_failed_fpscr_set(strerror(errno));
70b79849
DG		 636 return ret;
637 }
638
639 for (i = 0; i < 32; i++) {
640 uint64_t vsr[2];
ef96e3ae
MCA		 641 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
642 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 643
3a4b791b 644#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae
MCA		 645 vsr[0] = float64_val(*fpr);
646 vsr[1] = *vsrl;
3a4b791b 647#else
ef96e3ae
MCA		 648 vsr[0] = *vsrl;
649 vsr[1] = float64_val(*fpr);
3a4b791b 650#endif
70b79849
DG		 651 reg.addr = (uintptr_t) &vsr;
652 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
653
654 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
655 if (ret < 0) {
8d83cbf1
GK		 656 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
657 strerror(errno));
70b79849
DG		 658 return ret;
659 }
660 }
661 }
662
663 if (env->insns_flags & PPC_ALTIVEC) {
664 reg.id = KVM_REG_PPC_VSCR;
665 reg.addr = (uintptr_t)&env->vscr;
666 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
667 if (ret < 0) {
8d83cbf1 668 trace_kvm_failed_vscr_set(strerror(errno));
70b79849
DG		 669 return ret;
670 }
671
672 for (i = 0; i < 32; i++) {
673 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 674 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 675 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
676 if (ret < 0) {
8d83cbf1 677 trace_kvm_failed_vr_set(i, strerror(errno));
70b79849
DG		 678 return ret;
679 }
680 }
681 }
682
683 return 0;
684}
685
686static int kvm_get_fp(CPUState *cs)
687{
688 PowerPCCPU *cpu = POWERPC_CPU(cs);
689 CPUPPCState *env = &cpu->env;
690 struct kvm_one_reg reg;
691 int i;
692 int ret;
693
694 if (env->insns_flags & PPC_FLOAT) {
695 uint64_t fpscr;
696 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
697
698 reg.id = KVM_REG_PPC_FPSCR;
699 reg.addr = (uintptr_t)&fpscr;
700 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
701 if (ret < 0) {
8d83cbf1 702 trace_kvm_failed_fpscr_get(strerror(errno));
70b79849
DG		 703 return ret;
704 } else {
705 env->fpscr = fpscr;
706 }
707
708 for (i = 0; i < 32; i++) {
709 uint64_t vsr[2];
ef96e3ae
MCA		 710 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
711 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 712
713 reg.addr = (uintptr_t) &vsr;
714 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
715
716 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
717 if (ret < 0) {
8d83cbf1
GK		 718 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
719 strerror(errno));
70b79849
DG		 720 return ret;
721 } else {
3a4b791b 722#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae 723 *fpr = vsr[0];
70b79849 724 if (vsx) {
ef96e3ae 725 *vsrl = vsr[1];
70b79849 726 }
3a4b791b 727#else
ef96e3ae 728 *fpr = vsr[1];
3a4b791b 729 if (vsx) {
ef96e3ae 730 *vsrl = vsr[0];
3a4b791b
GK		 731 }
732#endif
70b79849
DG		 733 }
734 }
735 }
736
737 if (env->insns_flags & PPC_ALTIVEC) {
738 reg.id = KVM_REG_PPC_VSCR;
739 reg.addr = (uintptr_t)&env->vscr;
740 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
741 if (ret < 0) {
8d83cbf1 742 trace_kvm_failed_vscr_get(strerror(errno));
70b79849
DG		 743 return ret;
744 }
745
746 for (i = 0; i < 32; i++) {
747 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 748 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 749 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
750 if (ret < 0) {
8d83cbf1 751 trace_kvm_failed_vr_get(i, strerror(errno));
70b79849
DG		 752 return ret;
753 }
754 }
755 }
756
757 return 0;
758}
759
9b00ea49
DG		 760#if defined(TARGET_PPC64)
761static int kvm_get_vpa(CPUState *cs)
762{
763 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 764 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 765 struct kvm_one_reg reg;
766 int ret;
767
768 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 769 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 770 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
771 if (ret < 0) {
8d83cbf1 772 trace_kvm_failed_vpa_addr_get(strerror(errno));
9b00ea49
DG		 773 return ret;
774 }
775
7388efaf
DG		 776 assert((uintptr_t)&spapr_cpu->slb_shadow_size
777 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 778 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 779 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 780 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
781 if (ret < 0) {
8d83cbf1 782 trace_kvm_failed_slb_get(strerror(errno));
9b00ea49
DG		 783 return ret;
784 }
785
7388efaf
DG		 786 assert((uintptr_t)&spapr_cpu->dtl_size
787 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 788 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 789 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 790 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
791 if (ret < 0) {
8d83cbf1 792 trace_kvm_failed_dtl_get(strerror(errno));
9b00ea49
DG		 793 return ret;
794 }
795
796 return 0;
797}
798
799static int kvm_put_vpa(CPUState *cs)
800{
801 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 802 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 803 struct kvm_one_reg reg;
804 int ret;
805
c995e942
DG		 806 /*
807 * SLB shadow or DTL can't be registered unless a master VPA is
9b00ea49
DG		 808 * registered. That means when restoring state, if a VPA *is*
809 * registered, we need to set that up first. If not, we need to
c995e942
DG		 810 * deregister the others before deregistering the master VPA
811 */
7388efaf
DG		 812 assert(spapr_cpu->vpa_addr
813 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 814
7388efaf 815 if (spapr_cpu->vpa_addr) {
9b00ea49 816 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 817 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 818 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
819 if (ret < 0) {
8d83cbf1 820 trace_kvm_failed_vpa_addr_set(strerror(errno));
9b00ea49
DG		 821 return ret;
822 }
823 }
824
7388efaf
DG		 825 assert((uintptr_t)&spapr_cpu->slb_shadow_size
826 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 827 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 828 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 829 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
830 if (ret < 0) {
8d83cbf1 831 trace_kvm_failed_slb_set(strerror(errno));
9b00ea49
DG		 832 return ret;
833 }
834
7388efaf
DG		 835 assert((uintptr_t)&spapr_cpu->dtl_size
836 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 837 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 838 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 839 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
840 if (ret < 0) {
8d83cbf1 841 trace_kvm_failed_dtl_set(strerror(errno));
9b00ea49
DG		 842 return ret;
843 }
844
7388efaf 845 if (!spapr_cpu->vpa_addr) {
9b00ea49 846 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 847 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 848 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
849 if (ret < 0) {
8d83cbf1 850 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
9b00ea49
DG		 851 return ret;
852 }
853 }
854
855 return 0;
856}
857#endif /* TARGET_PPC64 */
858
e5c0d3ce 859int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 860{
861 CPUPPCState *env = &cpu->env;
862 struct kvm_sregs sregs;
863 int i;
864
865 sregs.pvr = env->spr[SPR_PVR];
866
1ec26c75
GK		 867 if (cpu->vhyp) {
868 PPCVirtualHypervisorClass *vhc =
869 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
870 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
871 } else {
872 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
873 }
a7a00a72
DG		 874
875 /* Sync SLB */
876#ifdef TARGET_PPC64
877 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
878 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
879 if (env->slb[i].esid & SLB_ESID_V) {
880 sregs.u.s.ppc64.slb[i].slbe |= i;
881 }
882 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
883 }
884#endif
885
886 /* Sync SRs */
887 for (i = 0; i < 16; i++) {
888 sregs.u.s.ppc32.sr[i] = env->sr[i];
889 }
890
891 /* Sync BATs */
892 for (i = 0; i < 8; i++) {
893 /* Beware. We have to swap upper and lower bits here */
894 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
895 | env->DBAT[1][i];
896 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
897 | env->IBAT[1][i];
898 }
899
900 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
901}
902
20d695a9 903int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 904{
20d695a9
AF		 905 PowerPCCPU *cpu = POWERPC_CPU(cs);
906 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 907 struct kvm_regs regs;
908 int ret;
909 int i;
910
1bc22652
AF		 911 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
912 if (ret < 0) {
d76d1650 913 return ret;
1bc22652 914 }
d76d1650
AJ		 915
916 regs.ctr = env->ctr;
917 regs.lr = env->lr;
da91a00f 918 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 919 regs.msr = env->msr;
920 regs.pc = env->nip;
921
922 regs.srr0 = env->spr[SPR_SRR0];
923 regs.srr1 = env->spr[SPR_SRR1];
924
925 regs.sprg0 = env->spr[SPR_SPRG0];
926 regs.sprg1 = env->spr[SPR_SPRG1];
927 regs.sprg2 = env->spr[SPR_SPRG2];
928 regs.sprg3 = env->spr[SPR_SPRG3];
929 regs.sprg4 = env->spr[SPR_SPRG4];
930 regs.sprg5 = env->spr[SPR_SPRG5];
931 regs.sprg6 = env->spr[SPR_SPRG6];
932 regs.sprg7 = env->spr[SPR_SPRG7];
933
90dc8812
SW		 934 regs.pid = env->spr[SPR_BOOKE_PID];
935
c995e942 936 for (i = 0; i < 32; i++) {
d76d1650 937 regs.gpr[i] = env->gpr[i];
c995e942 938 }
d76d1650 939
4bddaf55
AK		 940 regs.cr = 0;
941 for (i = 0; i < 8; i++) {
942 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
943 }
944
1bc22652 945 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
c995e942 946 if (ret < 0) {
d76d1650 947 return ret;
c995e942 948 }
d76d1650 949
70b79849
DG		 950 kvm_put_fp(cs);
951
93dd5e85 952 if (env->tlb_dirty) {
1bc22652 953 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 954 env->tlb_dirty = false;
955 }
956
f1af19d7 957 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 958 ret = kvmppc_put_books_sregs(cpu);
959 if (ret < 0) {
f1af19d7
DG		 960 return ret;
961 }
962 }
963
964 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 965 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
966 }
f1af19d7 967
d67d40ea
DG		 968 if (cap_one_reg) {
969 int i;
970
c995e942
DG		 971 /*
972 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 973 * the ONE_REG calls, but don't support the specific
974 * registers, there's a reasonable chance things will still
c995e942
DG		 975 * work, at least until we try to migrate.
976 */
d67d40ea
DG		 977 for (i = 0; i < 1024; i++) {
978 uint64_t id = env->spr_cb[i].one_reg_id;
979
980 if (id != 0) {
981 kvm_put_one_spr(cs, id, i);
982 }
f1af19d7 983 }
9b00ea49
DG		 984
985#ifdef TARGET_PPC64
80b3f79b
AK		 986 if (msr_ts) {
987 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
989 }
990 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
992 }
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
997 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
999 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1000 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1001 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1002 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1003 }
1004
9b00ea49
DG		 1005 if (cap_papr) {
1006 if (kvm_put_vpa(cs) < 0) {
8d83cbf1 1007 trace_kvm_failed_put_vpa();
9b00ea49
DG		 1008 }
1009 }
98a8b524
AK		 1010
1011 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1012#endif /* TARGET_PPC64 */
f1af19d7
DG		 1013 }
1014
d76d1650
AJ		 1015 return ret;
1016}
1017
c371c2e3
BB		 1018static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1019{
1020 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1021}
1022
a7a00a72
DG		 1023static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1024{
1025 CPUPPCState *env = &cpu->env;
1026 struct kvm_sregs sregs;
1027 int ret;
1028
1029 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1030 if (ret < 0) {
1031 return ret;
1032 }
1033
1034 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1035 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1036 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1037 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1038 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1039 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1040 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1041 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1042 env->spr[SPR_DECR] = sregs.u.e.dec;
1043 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1044 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1045 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1046 }
1047
1048 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1049 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1050 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1051 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1052 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1053 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1054 }
1055
1056 if (sregs.u.e.features & KVM_SREGS_E_64) {
1057 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1058 }
1059
1060 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1061 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1062 }
1063
1064 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1065 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1066 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1067 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1068 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1069 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1070 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1071 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1072 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1073 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1074 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1075 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1076 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1077 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1078 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1079 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1080 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1081 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1082 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1083 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1084 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1085 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1086 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1087 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1088 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1089 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1090 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1091 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1092 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1093 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1094 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1095 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1096 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1097
1098 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1099 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1100 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1101 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1102 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1103 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1104 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1105 }
1106
1107 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1108 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1109 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1110 }
1111
1112 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1113 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1114 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1115 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1116 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1117 }
1118 }
1119
1120 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1121 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1122 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1123 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1124 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1125 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1126 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1127 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1128 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1129 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1130 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1131 }
1132
1133 if (sregs.u.e.features & KVM_SREGS_EXP) {
1134 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1135 }
1136
1137 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1138 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1139 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1140 }
1141
1142 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1143 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1144 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1145 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1146
1147 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1148 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1149 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1150 }
1151 }
1152
1153 return 0;
1154}
1155
1156static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1157{
1158 CPUPPCState *env = &cpu->env;
1159 struct kvm_sregs sregs;
1160 int ret;
1161 int i;
1162
1163 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1164 if (ret < 0) {
1165 return ret;
1166 }
1167
e57ca75c 1168 if (!cpu->vhyp) {
a7a00a72
DG		 1169 ppc_store_sdr1(env, sregs.u.s.sdr1);
1170 }
1171
1172 /* Sync SLB */
1173#ifdef TARGET_PPC64
1174 /*
1175 * The packed SLB array we get from KVM_GET_SREGS only contains
1176 * information about valid entries. So we flush our internal copy
1177 * to get rid of stale ones, then put all valid SLB entries back
1178 * in.
1179 */
1180 memset(env->slb, 0, sizeof(env->slb));
1181 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1182 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1183 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1184 /*
1185 * Only restore valid entries
1186 */
1187 if (rb & SLB_ESID_V) {
1188 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1189 }
1190 }
1191#endif
1192
1193 /* Sync SRs */
1194 for (i = 0; i < 16; i++) {
1195 env->sr[i] = sregs.u.s.ppc32.sr[i];
1196 }
1197
1198 /* Sync BATs */
1199 for (i = 0; i < 8; i++) {
1200 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1201 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1202 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1203 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1204 }
1205
1206 return 0;
1207}
1208
20d695a9 1209int kvm_arch_get_registers(CPUState *cs)
d76d1650 1210{
20d695a9
AF		 1211 PowerPCCPU *cpu = POWERPC_CPU(cs);
1212 CPUPPCState *env = &cpu->env;
d76d1650 1213 struct kvm_regs regs;
90dc8812 1214 uint32_t cr;
138b38b6 1215 int i, ret;
d76d1650 1216
1bc22652 1217 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
c995e942 1218 if (ret < 0) {
d76d1650 1219 return ret;
c995e942 1220 }
d76d1650 1221
90dc8812
SW		 1222 cr = regs.cr;
1223 for (i = 7; i >= 0; i--) {
1224 env->crf[i] = cr & 15;
1225 cr >>= 4;
1226 }
ba5e5090 1227
d76d1650
AJ		 1228 env->ctr = regs.ctr;
1229 env->lr = regs.lr;
da91a00f 1230 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1231 env->msr = regs.msr;
1232 env->nip = regs.pc;
1233
1234 env->spr[SPR_SRR0] = regs.srr0;
1235 env->spr[SPR_SRR1] = regs.srr1;
1236
1237 env->spr[SPR_SPRG0] = regs.sprg0;
1238 env->spr[SPR_SPRG1] = regs.sprg1;
1239 env->spr[SPR_SPRG2] = regs.sprg2;
1240 env->spr[SPR_SPRG3] = regs.sprg3;
1241 env->spr[SPR_SPRG4] = regs.sprg4;
1242 env->spr[SPR_SPRG5] = regs.sprg5;
1243 env->spr[SPR_SPRG6] = regs.sprg6;
1244 env->spr[SPR_SPRG7] = regs.sprg7;
1245
90dc8812
SW		 1246 env->spr[SPR_BOOKE_PID] = regs.pid;
1247
c995e942 1248 for (i = 0; i < 32; i++) {
d76d1650 1249 env->gpr[i] = regs.gpr[i];
c995e942 1250 }
d76d1650 1251
70b79849
DG		 1252 kvm_get_fp(cs);
1253
90dc8812 1254 if (cap_booke_sregs) {
a7a00a72 1255 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1256 if (ret < 0) {
1257 return ret;
1258 }
fafc0b6a 1259 }
90dc8812 1260
90dc8812 1261 if (cap_segstate) {
a7a00a72 1262 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1263 if (ret < 0) {
1264 return ret;
1265 }
fafc0b6a 1266 }
ba5e5090 1267
d67d40ea
DG		 1268 if (cap_hior) {
1269 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1270 }
1271
1272 if (cap_one_reg) {
1273 int i;
1274
c995e942
DG		 1275 /*
1276 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 1277 * the ONE_REG calls, but don't support the specific
1278 * registers, there's a reasonable chance things will still
c995e942
DG		 1279 * work, at least until we try to migrate.
1280 */
d67d40ea
DG		 1281 for (i = 0; i < 1024; i++) {
1282 uint64_t id = env->spr_cb[i].one_reg_id;
1283
1284 if (id != 0) {
1285 kvm_get_one_spr(cs, id, i);
1286 }
1287 }
9b00ea49
DG		 1288
1289#ifdef TARGET_PPC64
80b3f79b
AK		 1290 if (msr_ts) {
1291 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1293 }
1294 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1296 }
1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1301 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1302 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1303 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1304 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1305 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1306 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1307 }
1308
9b00ea49
DG		 1309 if (cap_papr) {
1310 if (kvm_get_vpa(cs) < 0) {
8d83cbf1 1311 trace_kvm_failed_get_vpa();
9b00ea49
DG		 1312 }
1313 }
98a8b524
AK		 1314
1315 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1316#endif
d67d40ea
DG		 1317 }
1318
d76d1650
AJ		 1319 return 0;
1320}
1321
1bc22652 1322int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1323{
1324 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1325
1326 if (irq != PPC_INTERRUPT_EXT) {
1327 return 0;
1328 }
1329
1330 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
1331 return 0;
1332 }
1333
1bc22652 1334 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1335
1336 return 0;
1337}
1338
a69dc537 1339#if defined(TARGET_PPC64)
16415335
AG		 1340#define PPC_INPUT_INT PPC970_INPUT_INT
1341#else
1342#define PPC_INPUT_INT PPC6xx_INPUT_INT
1343#endif
1344
20d695a9 1345void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1346{
20d695a9
AF		 1347 PowerPCCPU *cpu = POWERPC_CPU(cs);
1348 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 1349 int r;
1350 unsigned irq;
1351
4b8523ee
JK		 1352 qemu_mutex_lock_iothread();
1353
c995e942
DG		 1354 /*
1355 * PowerPC QEMU tracks the various core input pins (interrupt,
1356 * critical interrupt, reset, etc) in PPC-specific
1357 * env->irq_input_state.
1358 */
fc87e185
AG		 1359 if (!cap_interrupt_level &&
1360 run->ready_for_interrupt_injection &&
259186a7 1361 (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
c995e942 1362 (env->irq_input_state & (1 << PPC_INPUT_INT)))
d76d1650 1363 {
c995e942
DG		 1364 /*
1365 * For now KVM disregards the 'irq' argument. However, in the
1366 * future KVM could cache it in-kernel to avoid a heavyweight
1367 * exit when reading the UIC.
d76d1650 1368 */
fc87e185 1369 irq = KVM_INTERRUPT_SET;
d76d1650 1370
8d83cbf1 1371 trace_kvm_injected_interrupt(irq);
1bc22652 1372 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);
55e5c285
AF		 1373 if (r < 0) {
1374 printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
1375 }
c821c2bd
AG		 1376
1377 /* Always wake up soon in case the interrupt was level based */
bc72ad67 1378 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 1379 (NANOSECONDS_PER_SECOND / 50));
d76d1650
AJ		 1380 }
1381
c995e942
DG		 1382 /*
1383 * We don't know if there are more interrupts pending after
1384 * this. However, the guest will return to userspace in the course
1385 * of handling this one anyways, so we will get a chance to
1386 * deliver the rest.
1387 */
4b8523ee
JK		 1388
1389 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1390}
1391
4c663752 1392MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1393{
4c663752 1394 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1395}
1396
20d695a9 1397int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1398{
259186a7 1399 return cs->halted;
0af691d7
MT		 1400}
1401
259186a7 1402static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1403{
259186a7
AF		 1404 CPUState *cs = CPU(cpu);
1405 CPUPPCState *env = &cpu->env;
1406
1407 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1408 cs->halted = 1;
27103424 1409 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1410 }
1411
bb4ea393 1412 return 0;
d76d1650
AJ		 1413}
1414
1415/* map dcr access to existing qemu dcr emulation */
c995e942
DG		 1416static int kvmppc_handle_dcr_read(CPUPPCState *env,
1417 uint32_t dcrn, uint32_t *data)
d76d1650 1418{
c995e942 1419 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
d76d1650 1420 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
c995e942 1421 }
d76d1650 1422
bb4ea393 1423 return 0;
d76d1650
AJ		 1424}
1425
c995e942
DG		 1426static int kvmppc_handle_dcr_write(CPUPPCState *env,
1427 uint32_t dcrn, uint32_t data)
d76d1650 1428{
c995e942 1429 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
d76d1650 1430 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
c995e942 1431 }
d76d1650 1432
bb4ea393 1433 return 0;
d76d1650
AJ		 1434}
1435
8a0548f9
BB		 1436int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1437{
1438 /* Mixed endian case is not handled */
1439 uint32_t sc = debug_inst_opcode;
1440
1441 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1442 sizeof(sc), 0) ||
1443 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1444 return -EINVAL;
1445 }
1446
1447 return 0;
1448}
1449
1450int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1451{
1452 uint32_t sc;
1453
1454 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1455 sc != debug_inst_opcode ||
1456 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1457 sizeof(sc), 1)) {
1458 return -EINVAL;
1459 }
1460
1461 return 0;
1462}
1463
88365d17
BB		 1464static int find_hw_breakpoint(target_ulong addr, int type)
1465{
1466 int n;
1467
1468 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1469 <= ARRAY_SIZE(hw_debug_points));
1470
1471 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1472 if (hw_debug_points[n].addr == addr &&
1473 hw_debug_points[n].type == type) {
1474 return n;
1475 }
1476 }
1477
1478 return -1;
1479}
1480
1481static int find_hw_watchpoint(target_ulong addr, int *flag)
1482{
1483 int n;
1484
1485 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1486 if (n >= 0) {
1487 *flag = BP_MEM_ACCESS;
1488 return n;
1489 }
1490
1491 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1492 if (n >= 0) {
1493 *flag = BP_MEM_WRITE;
1494 return n;
1495 }
1496
1497 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1498 if (n >= 0) {
1499 *flag = BP_MEM_READ;
1500 return n;
1501 }
1502
1503 return -1;
1504}
1505
1506int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1507 target_ulong len, int type)
1508{
1509 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1510 return -ENOBUFS;
1511 }
1512
1513 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1514 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1515
1516 switch (type) {
1517 case GDB_BREAKPOINT_HW:
1518 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1519 return -ENOBUFS;
1520 }
1521
1522 if (find_hw_breakpoint(addr, type) >= 0) {
1523 return -EEXIST;
1524 }
1525
1526 nb_hw_breakpoint++;
1527 break;
1528
1529 case GDB_WATCHPOINT_WRITE:
1530 case GDB_WATCHPOINT_READ:
1531 case GDB_WATCHPOINT_ACCESS:
1532 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1533 return -ENOBUFS;
1534 }
1535
1536 if (find_hw_breakpoint(addr, type) >= 0) {
1537 return -EEXIST;
1538 }
1539
1540 nb_hw_watchpoint++;
1541 break;
1542
1543 default:
1544 return -ENOSYS;
1545 }
1546
1547 return 0;
1548}
1549
1550int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1551 target_ulong len, int type)
1552{
1553 int n;
1554
1555 n = find_hw_breakpoint(addr, type);
1556 if (n < 0) {
1557 return -ENOENT;
1558 }
1559
1560 switch (type) {
1561 case GDB_BREAKPOINT_HW:
1562 nb_hw_breakpoint--;
1563 break;
1564
1565 case GDB_WATCHPOINT_WRITE:
1566 case GDB_WATCHPOINT_READ:
1567 case GDB_WATCHPOINT_ACCESS:
1568 nb_hw_watchpoint--;
1569 break;
1570
1571 default:
1572 return -ENOSYS;
1573 }
1574 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1575
1576 return 0;
1577}
1578
1579void kvm_arch_remove_all_hw_breakpoints(void)
1580{
1581 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1582}
1583
8a0548f9
BB		 1584void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1585{
88365d17
BB		 1586 int n;
1587
8a0548f9
BB		 1588 /* Software Breakpoint updates */
1589 if (kvm_sw_breakpoints_active(cs)) {
1590 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1591 }
88365d17
BB		 1592
1593 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1594 <= ARRAY_SIZE(hw_debug_points));
1595 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1596
1597 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1598 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1599 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1600 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1601 switch (hw_debug_points[n].type) {
1602 case GDB_BREAKPOINT_HW:
1603 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1604 break;
1605 case GDB_WATCHPOINT_WRITE:
1606 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1607 break;
1608 case GDB_WATCHPOINT_READ:
1609 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1610 break;
1611 case GDB_WATCHPOINT_ACCESS:
1612 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1613 KVMPPC_DEBUG_WATCH_READ;
1614 break;
1615 default:
1616 cpu_abort(cs, "Unsupported breakpoint type\n");
1617 }
1618 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1619 }
1620 }
8a0548f9
BB		 1621}
1622
2cbd1581
FR		 1623static int kvm_handle_hw_breakpoint(CPUState *cs,
1624 struct kvm_debug_exit_arch *arch_info)
1625{
1626 int handle = 0;
1627 int n;
1628 int flag = 0;
1629
1630 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1631 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1632 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1633 if (n >= 0) {
1634 handle = 1;
1635 }
1636 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1637 KVMPPC_DEBUG_WATCH_WRITE)) {
1638 n = find_hw_watchpoint(arch_info->address, &flag);
1639 if (n >= 0) {
1640 handle = 1;
1641 cs->watchpoint_hit = &hw_watchpoint;
1642 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1643 hw_watchpoint.flags = flag;
1644 }
1645 }
1646 }
1647 return handle;
1648}
1649
468e3a1a
FR		 1650static int kvm_handle_singlestep(void)
1651{
1652 return 1;
1653}
1654
1655static int kvm_handle_sw_breakpoint(void)
1656{
1657 return 1;
1658}
1659
8a0548f9
BB		 1660static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1661{
1662 CPUState *cs = CPU(cpu);
1663 CPUPPCState *env = &cpu->env;
1664 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
8a0548f9 1665
88365d17 1666 if (cs->singlestep_enabled) {
468e3a1a
FR		 1667 return kvm_handle_singlestep();
1668 }
8a0548f9 1669
468e3a1a
FR		 1670 if (arch_info->status) {
1671 return kvm_handle_hw_breakpoint(cs, arch_info);
8a0548f9
BB		 1672 }
1673
468e3a1a
FR		 1674 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1675 return kvm_handle_sw_breakpoint();
1676 }
1677
1678 /*
1679 * QEMU is not able to handle debug exception, so inject
1680 * program exception to guest;
1681 * Yes program exception NOT debug exception !!
1682 * When QEMU is using debug resources then debug exception must
1683 * be always set. To achieve this we set MSR_DE and also set
1684 * MSRP_DEP so guest cannot change MSR_DE.
1685 * When emulating debug resource for guest we want guest
1686 * to control MSR_DE (enable/disable debug interrupt on need).
1687 * Supporting both configurations are NOT possible.
1688 * So the result is that we cannot share debug resources
1689 * between QEMU and Guest on BOOKE architecture.
1690 * In the current design QEMU gets the priority over guest,
1691 * this means that if QEMU is using debug resources then guest
1692 * cannot use them;
1693 * For software breakpoint QEMU uses a privileged instruction;
1694 * So there cannot be any reason that we are here for guest
1695 * set debug exception, only possibility is guest executed a
1696 * privileged / illegal instruction and that's why we are
1697 * injecting a program interrupt.
1698 */
1699 cpu_synchronize_state(cs);
1700 /*
1701 * env->nip is PC, so increment this by 4 to use
1702 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1703 */
1704 env->nip += 4;
1705 cs->exception_index = POWERPC_EXCP_PROGRAM;
1706 env->error_code = POWERPC_EXCP_INVAL;
1707 ppc_cpu_do_interrupt(cs);
1708
1709 return 0;
8a0548f9
BB		 1710}
1711
20d695a9 1712int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1713{
20d695a9
AF		 1714 PowerPCCPU *cpu = POWERPC_CPU(cs);
1715 CPUPPCState *env = &cpu->env;
bb4ea393 1716 int ret;
d76d1650 1717
4b8523ee
JK		 1718 qemu_mutex_lock_iothread();
1719
d76d1650
AJ		 1720 switch (run->exit_reason) {
1721 case KVM_EXIT_DCR:
1722 if (run->dcr.is_write) {
8d83cbf1 1723 trace_kvm_handle_dcr_write();
d76d1650
AJ		 1724 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1725 } else {
228152c2 1726 trace_kvm_handle_dcr_read();
d76d1650
AJ		 1727 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1728 }
1729 break;
1730 case KVM_EXIT_HLT:
8d83cbf1 1731 trace_kvm_handle_halt();
259186a7 1732 ret = kvmppc_handle_halt(cpu);
d76d1650 1733 break;
c6304a4a 1734#if defined(TARGET_PPC64)
f61b4bed 1735 case KVM_EXIT_PAPR_HCALL:
8d83cbf1 1736 trace_kvm_handle_papr_hcall();
20d695a9 1737 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1738 run->papr_hcall.nr,
f61b4bed 1739 run->papr_hcall.args);
78e8fde2 1740 ret = 0;
f61b4bed
AG		 1741 break;
1742#endif
5b95b8b9 1743 case KVM_EXIT_EPR:
8d83cbf1 1744 trace_kvm_handle_epr();
933b19ea 1745 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1746 ret = 0;
1747 break;
31f2cb8f 1748 case KVM_EXIT_WATCHDOG:
8d83cbf1 1749 trace_kvm_handle_watchdog_expiry();
31f2cb8f
BB		 1750 watchdog_perform_action();
1751 ret = 0;
1752 break;
1753
8a0548f9 1754 case KVM_EXIT_DEBUG:
8d83cbf1 1755 trace_kvm_handle_debug_exception();
8a0548f9
BB		 1756 if (kvm_handle_debug(cpu, run)) {
1757 ret = EXCP_DEBUG;
1758 break;
1759 }
1760 /* re-enter, this exception was guest-internal */
1761 ret = 0;
1762 break;
1763
73aaec4a
JK		 1764 default:
1765 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1766 ret = -1;
1767 break;
d76d1650
AJ		 1768 }
1769
4b8523ee 1770 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1771 return ret;
1772}
1773
31f2cb8f
BB		 1774int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1775{
1776 CPUState *cs = CPU(cpu);
1777 uint32_t bits = tsr_bits;
1778 struct kvm_one_reg reg = {
1779 .id = KVM_REG_PPC_OR_TSR,
1780 .addr = (uintptr_t) &bits,
1781 };
1782
1783 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1784}
1785
1786int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1787{
1788
1789 CPUState *cs = CPU(cpu);
1790 uint32_t bits = tsr_bits;
1791 struct kvm_one_reg reg = {
1792 .id = KVM_REG_PPC_CLEAR_TSR,
1793 .addr = (uintptr_t) &bits,
1794 };
1795
1796 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1797}
1798
1799int kvmppc_set_tcr(PowerPCCPU *cpu)
1800{
1801 CPUState *cs = CPU(cpu);
1802 CPUPPCState *env = &cpu->env;
1803 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1804
1805 struct kvm_one_reg reg = {
1806 .id = KVM_REG_PPC_TCR,
1807 .addr = (uintptr_t) &tcr,
1808 };
1809
1810 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1811}
1812
1813int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1814{
1815 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1816 int ret;
1817
1818 if (!kvm_enabled()) {
1819 return -1;
1820 }
1821
1822 if (!cap_ppc_watchdog) {
1823 printf("warning: KVM does not support watchdog");
1824 return -1;
1825 }
1826
48add816 1827 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1828 if (ret < 0) {
1829 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1830 __func__, strerror(-ret));
1831 return ret;
1832 }
1833
1834 return ret;
1835}
1836
dc333cd6
AG		 1837static int read_cpuinfo(const char *field, char *value, int len)
1838{
1839 FILE *f;
1840 int ret = -1;
1841 int field_len = strlen(field);
1842 char line[512];
1843
1844 f = fopen("/proc/cpuinfo", "r");
1845 if (!f) {
1846 return -1;
1847 }
1848
1849 do {
ef951443 1850 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1851 break;
1852 }
1853 if (!strncmp(line, field, field_len)) {
ae215068 1854 pstrcpy(value, len, line);
dc333cd6
AG		 1855 ret = 0;
1856 break;
1857 }
c995e942 1858 } while (*line);
dc333cd6
AG		 1859
1860 fclose(f);
1861
1862 return ret;
1863}
1864
1865uint32_t kvmppc_get_tbfreq(void)
1866{
1867 char line[512];
1868 char *ns;
73bcb24d 1869 uint32_t retval = NANOSECONDS_PER_SECOND;
dc333cd6
AG		 1870
1871 if (read_cpuinfo("timebase", line, sizeof(line))) {
1872 return retval;
1873 }
1874
c995e942
DG		 1875 ns = strchr(line, ':');
1876 if (!ns) {
dc333cd6
AG		 1877 return retval;
1878 }
1879
1880 ns++;
1881
f9b8e7f6 1882 return atoi(ns);
dc333cd6 1883}
4513d923 1884
ef951443
ND		 1885bool kvmppc_get_host_serial(char **value)
1886{
1887 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1888 NULL);
1889}
1890
1891bool kvmppc_get_host_model(char **value)
1892{
1893 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1894}
1895
eadaada1
AG		 1896/* Try to find a device tree node for a CPU with clock-frequency property */
1897static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1898{
1899 struct dirent *dirp;
1900 DIR *dp;
1901
c995e942
DG		 1902 dp = opendir(PROC_DEVTREE_CPU);
1903 if (!dp) {
eadaada1
AG		 1904 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1905 return -1;
1906 }
1907
1908 buf[0] = '\0';
1909 while ((dirp = readdir(dp)) != NULL) {
1910 FILE *f;
1911 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1912 dirp->d_name);
1913 f = fopen(buf, "r");
1914 if (f) {
1915 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1916 fclose(f);
1917 break;
1918 }
1919 buf[0] = '\0';
1920 }
1921 closedir(dp);
1922 if (buf[0] == '\0') {
1923 printf("Unknown host!\n");
1924 return -1;
1925 }
1926
1927 return 0;
1928}
1929
7d94a30b 1930static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1931{
9bc884b7
DG		 1932 union {
1933 uint32_t v32;
1934 uint64_t v64;
1935 } u;
eadaada1
AG		 1936 FILE *f;
1937 int len;
1938
7d94a30b 1939 f = fopen(filename, "rb");
eadaada1
AG		 1940 if (!f) {
1941 return -1;
1942 }
1943
9bc884b7 1944 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1945 fclose(f);
1946 switch (len) {
9bc884b7
DG		 1947 case 4:
1948 /* property is a 32-bit quantity */
1949 return be32_to_cpu(u.v32);
1950 case 8:
1951 return be64_to_cpu(u.v64);
eadaada1
AG		 1952 }
1953
1954 return 0;
1955}
1956
c995e942
DG		 1957/*
1958 * Read a CPU node property from the host device tree that's a single
7d94a30b 1959 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
c995e942
DG		 1960 * (can't find or open the property, or doesn't understand the format)
1961 */
7d94a30b
SB		 1962static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1963{
1964 char buf[PATH_MAX], *tmp;
1965 uint64_t val;
1966
1967 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1968 return -1;
1969 }
1970
1971 tmp = g_strdup_printf("%s/%s", buf, propname);
1972 val = kvmppc_read_int_dt(tmp);
1973 g_free(tmp);
1974
1975 return val;
1976}
1977
9bc884b7
DG		 1978uint64_t kvmppc_get_clockfreq(void)
1979{
1980 return kvmppc_read_int_cpu_dt("clock-frequency");
1981}
1982
7d050527
SJS		 1983static int kvmppc_get_dec_bits(void)
1984{
1985 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1986
1987 if (nr_bits > 0) {
1988 return nr_bits;
1989 }
1990 return 0;
1991}
1992
1a61a9ae 1993static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
db70b311
RH		 1994{
1995 CPUState *cs = env_cpu(env);
1a61a9ae 1996
6fd33a75 1997 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1998 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1999 return 0;
2000 }
2001
2002 return 1;
2003}
2004
2005int kvmppc_get_hasidle(CPUPPCState *env)
2006{
2007 struct kvm_ppc_pvinfo pvinfo;
2008
2009 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
2010 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
2011 return 1;
2012 }
2013
2014 return 0;
2015}
2016
1328c2bf 2017int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09 2018{
c995e942 2019 uint32_t *hc = (uint32_t *)buf;
45024f09
AG		 2020 struct kvm_ppc_pvinfo pvinfo;
2021
1a61a9ae 2022 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 2023 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 2024 return 0;
2025 }
45024f09
AG		 2026
2027 /*
d13fc32e 2028 * Fallback to always fail hypercalls regardless of endianness:
45024f09 2029 *
d13fc32e 2030 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 2031 * li r3, -1
d13fc32e
AG		 2032 * b .+8 (becomes nop in wrong endian)
2033 * bswap32(li r3, -1)
45024f09
AG		 2034 */
2035
d13fc32e
AG		 2036 hc[0] = cpu_to_be32(0x08000048);
2037 hc[1] = cpu_to_be32(0x3860ffff);
2038 hc[2] = cpu_to_be32(0x48000008);
2039 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 2040
0ddbd053 2041 return 1;
45024f09
AG		 2042}
2043
026bfd89
DG		 2044static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2045{
2046 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2047}
2048
2049void kvmppc_enable_logical_ci_hcalls(void)
2050{
2051 /*
2052 * FIXME: it would be nice if we could detect the cases where
2053 * we're using a device which requires the in kernel
2054 * implementation of these hcalls, but the kernel lacks them and
2055 * produce a warning.
2056 */
2057 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2058 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2059}
2060
ef9971dd
AK		 2061void kvmppc_enable_set_mode_hcall(void)
2062{
2063 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2064}
2065
5145ad4f
NW		 2066void kvmppc_enable_clear_ref_mod_hcalls(void)
2067{
2068 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2069 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2070}
2071
68f9f708
SJS		 2072void kvmppc_enable_h_page_init(void)
2073{
2074 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2075}
2076
1bc22652 2077void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2078{
1bc22652 2079 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2080 int ret;
2081
da20aed1
DG		 2082 if (!kvm_enabled()) {
2083 return;
2084 }
2085
48add816 2086 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2087 if (ret) {
072ed5f2
TH		 2088 error_report("This vCPU type or KVM version does not support PAPR");
2089 exit(1);
94135e81 2090 }
9b00ea49 2091
c995e942
DG		 2092 /*
2093 * Update the capability flag so we sync the right information
2094 * with kvm
2095 */
9b00ea49 2096 cap_papr = 1;
f61b4bed
AG		 2097}
2098
d6e166c0 2099int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2100{
d6e166c0 2101 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2102}
2103
5b95b8b9
AG		 2104void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2105{
5b95b8b9 2106 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2107 int ret;
2108
48add816 2109 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2110 if (ret && mpic_proxy) {
072ed5f2
TH		 2111 error_report("This KVM version does not support EPR");
2112 exit(1);
5b95b8b9
AG		 2113 }
2114}
2115
e97c3636
DG		 2116int kvmppc_smt_threads(void)
2117{
2118 return cap_ppc_smt ? cap_ppc_smt : 1;
2119}
2120
fa98fbfc
SB		 2121int kvmppc_set_smt_threads(int smt)
2122{
2123 int ret;
2124
2125 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2126 if (!ret) {
2127 cap_ppc_smt = smt;
2128 }
2129 return ret;
2130}
2131
2132void kvmppc_hint_smt_possible(Error **errp)
2133{
2134 int i;
2135 GString *g;
2136 char *s;
2137
2138 assert(kvm_enabled());
2139 if (cap_ppc_smt_possible) {
2140 g = g_string_new("Available VSMT modes:");
2141 for (i = 63; i >= 0; i--) {
2142 if ((1UL << i) & cap_ppc_smt_possible) {
2143 g_string_append_printf(g, " %lu", (1UL << i));
2144 }
2145 }
2146 s = g_string_free(g, false);
2147 error_append_hint(errp, "%s.\n", s);
2148 g_free(s);
2149 } else {
2150 error_append_hint(errp,
2151 "This KVM seems to be too old to support VSMT.\n");
2152 }
2153}
2154
2155
7f763a5d 2156#ifdef TARGET_PPC64
7f763a5d
DG		 2157uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2158{
f36951c1
DG		 2159 struct kvm_ppc_smmu_info info;
2160 long rampagesize, best_page_shift;
2161 int i;
2162
c995e942
DG		 2163 /*
2164 * Find the largest hardware supported page size that's less than
2165 * or equal to the (logical) backing page size of guest RAM
2166 */
ab256960 2167 kvm_get_smmu_info(&info, &error_fatal);
905b7ee4 2168 rampagesize = qemu_minrampagesize();
f36951c1
DG		 2169 best_page_shift = 0;
2170
2171 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2172 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2173
2174 if (!sps->page_shift) {
2175 continue;
2176 }
2177
2178 if ((sps->page_shift > best_page_shift)
2179 && ((1UL << sps->page_shift) <= rampagesize)) {
2180 best_page_shift = sps->page_shift;
2181 }
2182 }
2183
7f763a5d 2184 return MIN(current_size,
f36951c1 2185 1ULL << (best_page_shift + hash_shift - 7));
7f763a5d
DG		 2186}
2187#endif
2188
da95324e
AK		 2189bool kvmppc_spapr_use_multitce(void)
2190{
2191 return cap_spapr_multitce;
2192}
2193
3dc410ae
AK		 2194int kvmppc_spapr_enable_inkernel_multitce(void)
2195{
2196 int ret;
2197
2198 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2199 H_PUT_TCE_INDIRECT, 1);
2200 if (!ret) {
2201 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2202 H_STUFF_TCE, 1);
2203 }
2204
2205 return ret;
2206}
2207
d6ee2a7c
AK		 2208void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2209 uint64_t bus_offset, uint32_t nb_table,
2210 int *pfd, bool need_vfio)
0f5cb298 2211{
0f5cb298
DG		 2212 long len;
2213 int fd;
2214 void *table;
2215
c995e942
DG		 2216 /*
2217 * Must set fd to -1 so we don't try to munmap when called for
b5aec396
DG		 2218 * destroying the table, which the upper layers -will- do
2219 */
2220 *pfd = -1;
6a81dd17 2221 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2222 return NULL;
2223 }
2224
d6ee2a7c
AK		 2225 if (cap_spapr_tce_64) {
2226 struct kvm_create_spapr_tce_64 args = {
2227 .liobn = liobn,
2228 .page_shift = page_shift,
2229 .offset = bus_offset >> page_shift,
2230 .size = nb_table,
2231 .flags = 0
2232 };
2233 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2234 if (fd < 0) {
2235 fprintf(stderr,
2236 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2237 liobn);
2238 return NULL;
2239 }
2240 } else if (cap_spapr_tce) {
2241 uint64_t window_size = (uint64_t) nb_table << page_shift;
2242 struct kvm_create_spapr_tce args = {
2243 .liobn = liobn,
2244 .window_size = window_size,
2245 };
2246 if ((window_size != args.window_size) || bus_offset) {
2247 return NULL;
2248 }
2249 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2250 if (fd < 0) {
2251 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2252 liobn);
2253 return NULL;
2254 }
2255 } else {
0f5cb298
DG		 2256 return NULL;
2257 }
2258
d6ee2a7c 2259 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2260 /* FIXME: round this up to page size */
2261
c995e942 2262 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2263 if (table == MAP_FAILED) {
b5aec396
DG		 2264 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2265 liobn);
0f5cb298
DG		 2266 close(fd);
2267 return NULL;
2268 }
2269
2270 *pfd = fd;
2271 return table;
2272}
2273
523e7b8a 2274int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2275{
2276 long len;
2277
2278 if (fd < 0) {
2279 return -1;
2280 }
2281
523e7b8a 2282 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2283 if ((munmap(table, len) < 0) ||
2284 (close(fd) < 0)) {
b5aec396
DG		 2285 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2286 strerror(errno));
0f5cb298
DG		 2287 /* Leak the table */
2288 }
2289
2290 return 0;
2291}
2292
7f763a5d
DG		 2293int kvmppc_reset_htab(int shift_hint)
2294{
2295 uint32_t shift = shift_hint;
2296
ace9a2cb
DG		 2297 if (!kvm_enabled()) {
2298 /* Full emulation, tell caller to allocate htab itself */
2299 return 0;
2300 }
6977afda 2301 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2302 int ret;
2303 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb 2304 if (ret == -ENOTTY) {
c995e942
DG		 2305 /*
2306 * At least some versions of PR KVM advertise the
ace9a2cb
DG		 2307 * capability, but don't implement the ioctl(). Oops.
2308 * Return 0 so that we allocate the htab in qemu, as is
c995e942
DG		 2309 * correct for PR.
2310 */
ace9a2cb
DG		 2311 return 0;
2312 } else if (ret < 0) {
7f763a5d
DG		 2313 return ret;
2314 }
2315 return shift;
2316 }
2317
c995e942
DG		 2318 /*
2319 * We have a kernel that predates the htab reset calls. For PR
ace9a2cb 2320 * KVM, we need to allocate the htab ourselves, for an HV KVM of
c995e942
DG		 2321 * this era, it has allocated a 16MB fixed size hash table
2322 * already.
2323 */
96c9cff0 2324 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2325 /* PR - tell caller to allocate htab */
2326 return 0;
2327 } else {
2328 /* HV - assume 16MB kernel allocated htab */
2329 return 24;
2330 }
7f763a5d
DG		 2331}
2332
a1e98583
DG		 2333static inline uint32_t mfpvr(void)
2334{
2335 uint32_t pvr;
2336
2337 asm ("mfpvr %0"
2338 : "=r"(pvr));
2339 return pvr;
2340}
2341
a7342588
DG		 2342static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2343{
2344 if (on) {
2345 *word |= flags;
2346 } else {
2347 *word &= ~flags;
2348 }
2349}
2350
2985b86b
AF		 2351static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2352{
2353 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2354 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2355 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2356
cfe34f44 2357 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2358 pcc->pvr = mfpvr();
a7342588 2359
3f2ca480
DG		 2360 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2361 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2362 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2363 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2364 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2365 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2366
2367 if (dcache_size != -1) {
2368 pcc->l1_dcache_size = dcache_size;
2369 }
2370
2371 if (icache_size != -1) {
2372 pcc->l1_icache_size = icache_size;
2373 }
c64abd1f
SB		 2374
2375#if defined(TARGET_PPC64)
2376 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2377
2378 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2379 /*
2380 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2381 * compliant. More importantly, advertising ISA 3.00
2382 * architected mode may prevent guests from activating
2383 * necessary DD1 workarounds.
2384 */
2385 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2386 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2387 }
c64abd1f 2388#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2389}
2390
3b961124
SY		 2391bool kvmppc_has_cap_epr(void)
2392{
2393 return cap_epr;
2394}
2395
87a91de6
AG		 2396bool kvmppc_has_cap_fixup_hcalls(void)
2397{
2398 return cap_fixup_hcalls;
2399}
2400
bac3bf28
TH		 2401bool kvmppc_has_cap_htm(void)
2402{
2403 return cap_htm;
2404}
2405
cf1c4cce
SB		 2406bool kvmppc_has_cap_mmu_radix(void)
2407{
2408 return cap_mmu_radix;
2409}
2410
2411bool kvmppc_has_cap_mmu_hash_v3(void)
2412{
2413 return cap_mmu_hash_v3;
2414}
2415
072f416a
SJS		 2416static bool kvmppc_power8_host(void)
2417{
2418 bool ret = false;
2419#ifdef TARGET_PPC64
2420 {
2421 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2422 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2423 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2424 (base_pvr == CPU_POWERPC_POWER8_BASE);
2425 }
2426#endif /* TARGET_PPC64 */
2427 return ret;
2428}
2429
8fea7044
SJS		 2430static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2431{
072f416a
SJS		 2432 bool l1d_thread_priv_req = !kvmppc_power8_host();
2433
8fea7044
SJS		 2434 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2435 return 2;
072f416a
SJS		 2436 } else if ((!l1d_thread_priv_req ||
2437 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2438 (c.character & c.character_mask
2439 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2440 return 1;
2441 }
2442
2443 return 0;
2444}
2445
2446static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2447{
2448 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2449 return 2;
2450 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2451 return 1;
2452 }
2453
2454 return 0;
2455}
2456
2457static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2458{
399b2896
SJS		 2459 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2460 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2461 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2462 return SPAPR_CAP_FIXED_NA;
2463 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2464 return SPAPR_CAP_WORKAROUND;
2465 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2466 return SPAPR_CAP_FIXED_CCD;
2467 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2468 return SPAPR_CAP_FIXED_IBS;
2469 }
2470
2471 return 0;
2472}
2473
8ff43ee4
SJS		 2474static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2475{
2476 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2477 return 1;
2478 }
2479 return 0;
2480}
2481
38afd772
CLG		 2482bool kvmppc_has_cap_xive(void)
2483{
2484 return cap_xive;
2485}
2486
8acc2ae5
SJS		 2487static void kvmppc_get_cpu_characteristics(KVMState *s)
2488{
2489 struct kvm_ppc_cpu_char c;
2490 int ret;
2491
2492 /* Assume broken */
2493 cap_ppc_safe_cache = 0;
2494 cap_ppc_safe_bounds_check = 0;
2495 cap_ppc_safe_indirect_branch = 0;
2496
2497 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2498 if (!ret) {
2499 return;
2500 }
2501 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2502 if (ret < 0) {
2503 return;
2504 }
8fea7044
SJS		 2505
2506 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2507 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2508 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2509 cap_ppc_count_cache_flush_assist =
2510 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2511}
2512
2513int kvmppc_get_cap_safe_cache(void)
2514{
2515 return cap_ppc_safe_cache;
2516}
2517
2518int kvmppc_get_cap_safe_bounds_check(void)
2519{
2520 return cap_ppc_safe_bounds_check;
2521}
2522
2523int kvmppc_get_cap_safe_indirect_branch(void)
2524{
2525 return cap_ppc_safe_indirect_branch;
2526}
2527
8ff43ee4
SJS		 2528int kvmppc_get_cap_count_cache_flush_assist(void)
2529{
2530 return cap_ppc_count_cache_flush_assist;
2531}
2532
b9a477b7
SJS		 2533bool kvmppc_has_cap_nested_kvm_hv(void)
2534{
2535 return !!cap_ppc_nested_kvm_hv;
2536}
2537
2538int kvmppc_set_cap_nested_kvm_hv(int enable)
2539{
2540 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2541}
2542
9ded780c
AK		 2543bool kvmppc_has_cap_spapr_vfio(void)
2544{
2545 return cap_spapr_vfio;
2546}
2547
7d050527
SJS		 2548int kvmppc_get_cap_large_decr(void)
2549{
2550 return cap_large_decr;
2551}
2552
2553int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2554{
2555 CPUState *cs = CPU(cpu);
2556 uint64_t lpcr;
2557
2558 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2559 /* Do we need to modify the LPCR? */
2560 if (!!(lpcr & LPCR_LD) != !!enable) {
2561 if (enable) {
2562 lpcr |= LPCR_LD;
2563 } else {
2564 lpcr &= ~LPCR_LD;
2565 }
2566 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2567 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2568
2569 if (!!(lpcr & LPCR_LD) != !!enable) {
2570 return -1;
2571 }
2572 }
2573
2574 return 0;
2575}
2576
52b2519c
TH		 2577PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2578{
2579 uint32_t host_pvr = mfpvr();
2580 PowerPCCPUClass *pvr_pcc;
2581
2582 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2583 if (pvr_pcc == NULL) {
2584 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2585 }
2586
2587 return pvr_pcc;
2588}
2589
2e9c10eb 2590static int kvm_ppc_register_host_cpu_type(MachineState *ms)
5ba4576b
AF		 2591{
2592 TypeInfo type_info = {
2593 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2594 .class_init = kvmppc_host_cpu_class_init,
2595 };
2e9c10eb 2596 MachineClass *mc = MACHINE_GET_CLASS(ms);
5ba4576b 2597 PowerPCCPUClass *pvr_pcc;
92e926e1 2598 ObjectClass *oc;
5b79b1ca 2599 DeviceClass *dc;
715d4b96 2600 int i;
5ba4576b 2601
52b2519c 2602 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2603 if (pvr_pcc == NULL) {
2604 return -1;
2605 }
2606 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2607 type_register(&type_info);
2e9c10eb
IM		 2608 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2609 /* override TCG default cpu type with 'host' cpu model */
2610 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2611 }
5b79b1ca 2612
92e926e1
GK		 2613 oc = object_class_by_name(type_info.name);
2614 g_assert(oc);
2615
715d4b96
TH		 2616 /*
2617 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2618 * we want "POWER8" to be a "family" alias that points to the current
2619 * host CPU type, too)
2620 */
2621 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2622 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2623 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2624 char *suffix;
2625
2626 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2627 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2628 if (suffix) {
2629 *suffix = 0;
2630 }
715d4b96
TH		 2631 break;
2632 }
2633 }
2634
5ba4576b
AF		 2635 return 0;
2636}
2637
feaa64c4
DG		 2638int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2639{
2640 struct kvm_rtas_token_args args = {
2641 .token = token,
2642 };
2643
2644 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2645 return -ENOENT;
2646 }
2647
2648 strncpy(args.name, function, sizeof(args.name));
2649
2650 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2651}
12b1143b 2652
14b0d748 2653int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2654{
2655 struct kvm_get_htab_fd s = {
2656 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2657 .start_index = index,
e68cb8b4 2658 };
82be8e73 2659 int ret;
e68cb8b4
AK		 2660
2661 if (!cap_htab_fd) {
14b0d748
GK		 2662 error_setg(errp, "KVM version doesn't support %s the HPT",
2663 write ? "writing" : "reading");
82be8e73
GK		 2664 return -ENOTSUP;
2665 }
2666
2667 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2668 if (ret < 0) {
14b0d748
GK		 2669 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2670 write ? "writing" : "reading", write ? "to" : "from",
2671 strerror(errno));
82be8e73 2672 return -errno;
e68cb8b4
AK		 2673 }
2674
82be8e73 2675 return ret;
e68cb8b4
AK		 2676}
2677
2678int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2679{
bc72ad67 2680 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2681 uint8_t buf[bufsize];
2682 ssize_t rc;
2683
2684 do {
2685 rc = read(fd, buf, bufsize);
2686 if (rc < 0) {
2687 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2688 strerror(errno));
2689 return rc;
2690 } else if (rc) {
e094c4c1
CLG		 2691 uint8_t *buffer = buf;
2692 ssize_t n = rc;
2693 while (n) {
2694 struct kvm_get_htab_header *head =
2695 (struct kvm_get_htab_header *) buffer;
2696 size_t chunksize = sizeof(*head) +
2697 HASH_PTE_SIZE_64 * head->n_valid;
2698
2699 qemu_put_be32(f, head->index);
2700 qemu_put_be16(f, head->n_valid);
2701 qemu_put_be16(f, head->n_invalid);
2702 qemu_put_buffer(f, (void *)(head + 1),
2703 HASH_PTE_SIZE_64 * head->n_valid);
2704
2705 buffer += chunksize;
2706 n -= chunksize;
2707 }
e68cb8b4
AK		 2708 }
2709 } while ((rc != 0)
c995e942
DG		 2710 && ((max_ns < 0) ||
2711 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2712
2713 return (rc == 0) ? 1 : 0;
2714}
2715
2716int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2717 uint16_t n_valid, uint16_t n_invalid)
2718{
2719 struct kvm_get_htab_header *buf;
c995e942 2720 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
e68cb8b4
AK		 2721 ssize_t rc;
2722
2723 buf = alloca(chunksize);
e68cb8b4
AK		 2724 buf->index = index;
2725 buf->n_valid = n_valid;
2726 buf->n_invalid = n_invalid;
2727
c995e942 2728 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
e68cb8b4
AK		 2729
2730 rc = write(fd, buf, chunksize);
2731 if (rc < 0) {
2732 fprintf(stderr, "Error writing KVM hash table: %s\n",
2733 strerror(errno));
2734 return rc;
2735 }
2736 if (rc != chunksize) {
2737 /* We should never get a short write on a single chunk */
2738 fprintf(stderr, "Short write, restoring KVM hash table\n");
2739 return -1;
2740 }
2741 return 0;
2742}
2743
20d695a9 2744bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2745{
2746 return true;
2747}
a1b87fe0 2748
82169660
SW		 2749void kvm_arch_init_irq_routing(KVMState *s)
2750{
2751}
c65f9a07 2752
1ad9f0a4 2753void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2754{
1ad9f0a4
DG		 2755 int fd, rc;
2756 int i;
7c43bca0 2757
14b0d748 2758 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2759
1ad9f0a4
DG		 2760 i = 0;
2761 while (i < n) {
2762 struct kvm_get_htab_header *hdr;
2763 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2764 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2765
1ad9f0a4
DG		 2766 rc = read(fd, buf, sizeof(buf));
2767 if (rc < 0) {
2768 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2769 }
7c43bca0 2770
1ad9f0a4
DG		 2771 hdr = (struct kvm_get_htab_header *)buf;
2772 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2773 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2774
1ad9f0a4
DG		 2775 if (hdr->index != (ptex + i)) {
2776 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2777 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2778 }
2779
a36593e1
AK		 2780 if (n - i < valid) {
2781 valid = n - i;
2782 }
2783 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2784 i += valid;
7c43bca0 2785
1ad9f0a4
DG		 2786 if ((n - i) < invalid) {
2787 invalid = n - i;
2788 }
2789 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2790 i += invalid;
1ad9f0a4
DG		 2791
2792 hdr = (struct kvm_get_htab_header *)
2793 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2794 }
2795 }
2796
2797 close(fd);
7c43bca0 2798}
c1385933 2799
1ad9f0a4 2800void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2801{
1ad9f0a4 2802 int fd, rc;
1ad9f0a4
DG		 2803 struct {
2804 struct kvm_get_htab_header hdr;
2805 uint64_t pte0;
2806 uint64_t pte1;
2807 } buf;
c1385933 2808
14b0d748 2809 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2810
1ad9f0a4
DG		 2811 buf.hdr.n_valid = 1;
2812 buf.hdr.n_invalid = 0;
2813 buf.hdr.index = ptex;
2814 buf.pte0 = cpu_to_be64(pte0);
2815 buf.pte1 = cpu_to_be64(pte1);
c1385933 2816
1ad9f0a4
DG		 2817 rc = write(fd, &buf, sizeof(buf));
2818 if (rc != sizeof(buf)) {
2819 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2820 }
2821 close(fd);
c1385933 2822}
9e03a040
FB		 2823
2824int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2825 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2826{
2827 return 0;
2828}
1850b6b7 2829
38d87493
PX		 2830int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2831 int vector, PCIDevice *dev)
2832{
2833 return 0;
2834}
2835
2836int kvm_arch_release_virq_post(int virq)
2837{
2838 return 0;
2839}
2840
1850b6b7
EA		 2841int kvm_arch_msi_data_to_gsi(uint32_t data)
2842{
2843 return data & 0xffff;
2844}
4d9392be
TH		 2845
2846int kvmppc_enable_hwrng(void)
2847{
2848 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2849 return -1;
2850 }
2851
2852 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2853}
30f4b05b
DG		 2854
2855void kvmppc_check_papr_resize_hpt(Error **errp)
2856{
2857 if (!kvm_enabled()) {
b55d295e
DG		 2858 return; /* No KVM, we're good */
2859 }
2860
2861 if (cap_resize_hpt) {
2862 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2863 }
2864
b55d295e
DG		 2865 /* Otherwise fallback on looking for PR KVM */
2866 if (kvmppc_is_pr(kvm_state)) {
2867 return;
2868 }
30f4b05b
DG		 2869
2870 error_setg(errp,
2871 "Hash page table resizing not available with this KVM version");
2872}
b55d295e
DG		 2873
2874int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2875{
2876 CPUState *cs = CPU(cpu);
2877 struct kvm_ppc_resize_hpt rhpt = {
2878 .flags = flags,
2879 .shift = shift,
2880 };
2881
2882 if (!cap_resize_hpt) {
2883 return -ENOSYS;
2884 }
2885
2886 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2887}
2888
2889int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2890{
2891 CPUState *cs = CPU(cpu);
2892 struct kvm_ppc_resize_hpt rhpt = {
2893 .flags = flags,
2894 .shift = shift,
2895 };
2896
2897 if (!cap_resize_hpt) {
2898 return -ENOSYS;
2899 }
2900
2901 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2902}
2903
c363a37a
DHB		 2904/*
2905 * This is a helper function to detect a post migration scenario
2906 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2907 * the guest kernel can't handle a PVR value other than the actual host
2908 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2909 *
2910 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2911 * (so, we're HV), return true. The workaround itself is done in
2912 * cpu_post_load.
2913 *
2914 * The order here is important: we'll only check for KVM PR as a
2915 * fallback if the guest kernel can't handle the situation itself.
2916 * We need to avoid as much as possible querying the running KVM type
2917 * in QEMU level.
2918 */
2919bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2920{
2921 CPUState *cs = CPU(cpu);
2922
2923 if (!kvm_enabled()) {
2924 return false;
2925 }
2926
2927 if (cap_ppc_pvr_compat) {
2928 return false;
2929 }
2930
2931 return !kvmppc_is_pr(cs->kvm_state);
2932}
a84f7179
ND		 2933
2934void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2935{
2936 CPUState *cs = CPU(cpu);
2937
2938 if (kvm_enabled()) {
2939 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2940 }
2941}
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