[qemu.git] / target-i386 / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/pc.h"
#include "hw/isa.h"
#include "host-utils.h"

#include "exec-all.h"
#include "kvm.h"

static const VMStateDescription vmstate_segment = {
    .name = "segment",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(selector, SegmentCache),
        VMSTATE_UINTTL(base, SegmentCache),
        VMSTATE_UINT32(limit, SegmentCache),
        VMSTATE_UINT32(flags, SegmentCache),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_SEGMENT(_field, _state) {                            \
    .name       = (stringify(_field)),                               \
    .size       = sizeof(SegmentCache),                              \
    .vmsd       = &vmstate_segment,                                  \
    .flags      = VMS_STRUCT,                                        \
    .offset     = offsetof(_state, _field)                           \
            + type_check(SegmentCache,typeof_field(_state, _field))  \
}

#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)

static const VMStateDescription vmstate_xmm_reg = {
    .name = "xmm_reg",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(XMM_Q(0), XMMReg),
        VMSTATE_UINT64(XMM_Q(1), XMMReg),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_XMM_REGS(_field, _state, _n)                         \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)

static const VMStateDescription vmstate_mtrr_var = {
    .name = "mtrr_var",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(base, MTRRVar),
        VMSTATE_UINT64(mask, MTRRVar),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)

static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
{
    fprintf(stderr, "call put_fpreg() with invalid arguments\n");
    exit(0);
}

#ifdef USE_X86LDOUBLE
/* XXX: add that in a FPU generic layer */
union x86_longdouble {
    uint64_t mant;
    uint16_t exp;
};

#define MANTD1(fp)	(fp & ((1LL << 52) - 1))
#define EXPBIAS1 1023
#define EXPD1(fp)	((fp >> 52) & 0x7FF)
#define SIGND1(fp)	((fp >> 32) & 0x80000000)

static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
{
    int e;
    /* mantissa */
    p->mant = (MANTD1(temp) << 11) | (1LL << 63);
    /* exponent + sign */
    e = EXPD1(temp) - EXPBIAS1 + 16383;
    e |= SIGND1(temp) >> 16;
    p->exp = e;
}

static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    uint64_t mant;
    uint16_t exp;

    qemu_get_be64s(f, &mant);
    qemu_get_be16s(f, &exp);
    fp_reg->d = cpu_set_fp80(mant, exp);
    return 0;
}

static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    uint64_t mant;
    uint16_t exp;
    /* we save the real CPU data (in case of MMX usage only 'mant'
       contains the MMX register */
    cpu_get_fp80(&mant, &exp, fp_reg->d);
    qemu_put_be64s(f, &mant);
    qemu_put_be16s(f, &exp);
}

const VMStateInfo vmstate_fpreg = {
    .name = "fpreg",
    .get  = get_fpreg,
    .put  = put_fpreg,
};

static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
{
    union x86_longdouble *p = opaque;
    uint64_t mant;

    qemu_get_be64s(f, &mant);
    p->mant = mant;
    p->exp = 0xffff;
    return 0;
}

const VMStateInfo vmstate_fpreg_1_mmx = {
    .name = "fpreg_1_mmx",
    .get  = get_fpreg_1_mmx,
    .put  = put_fpreg_error,
};

static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
{
    union x86_longdouble *p = opaque;
    uint64_t mant;

    qemu_get_be64s(f, &mant);
    fp64_to_fp80(p, mant);
    return 0;
}

const VMStateInfo vmstate_fpreg_1_no_mmx = {
    .name = "fpreg_1_no_mmx",
    .get  = get_fpreg_1_no_mmx,
    .put  = put_fpreg_error,
};

static bool fpregs_is_0(void *opaque, int version_id)
{
    CPUState *env = opaque;

    return (env->fpregs_format_vmstate == 0);
}

static bool fpregs_is_1_mmx(void *opaque, int version_id)
{
    CPUState *env = opaque;
    int guess_mmx;

    guess_mmx = ((env->fptag_vmstate == 0xff) &&
                 (env->fpus_vmstate & 0x3800) == 0);
    return (guess_mmx && (env->fpregs_format_vmstate == 1));
}

static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
{
    CPUState *env = opaque;
    int guess_mmx;

    guess_mmx = ((env->fptag_vmstate == 0xff) &&
                 (env->fpus_vmstate & 0x3800) == 0);
    return (!guess_mmx && (env->fpregs_format_vmstate == 1));
}

#define VMSTATE_FP_REGS(_field, _state, _n)                               \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)

#else
static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;

    qemu_get_be64s(f, &fp_reg->mmx.MMX_Q(0));
    return 0;
}

static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    /* if we use doubles for float emulation, we save the doubles to
       avoid losing information in case of MMX usage. It can give
       problems if the image is restored on a CPU where long
       doubles are used instead. */
    qemu_put_be64s(f, &fp_reg->mmx.MMX_Q(0));
}

const VMStateInfo vmstate_fpreg = {
    .name = "fpreg",
    .get  = get_fpreg,
    .put  = put_fpreg,
};

static int get_fpreg_0_mmx(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    uint64_t mant;
    uint16_t exp;

    qemu_get_be64s(f, &mant);
    qemu_get_be16s(f, &exp);
    fp_reg->mmx.MMX_Q(0) = mant;
    return 0;
}

const VMStateInfo vmstate_fpreg_0_mmx = {
    .name = "fpreg_0_mmx",
    .get  = get_fpreg_0_mmx,
    .put  = put_fpreg_error,
};

static int get_fpreg_0_no_mmx(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    uint64_t mant;
    uint16_t exp;

    qemu_get_be64s(f, &mant);
    qemu_get_be16s(f, &exp);

    fp_reg->d = cpu_set_fp80(mant, exp);
    return 0;
}

const VMStateInfo vmstate_fpreg_0_no_mmx = {
    .name = "fpreg_0_no_mmx",
    .get  = get_fpreg_0_no_mmx,
    .put  = put_fpreg_error,
};

static bool fpregs_is_1(void *opaque, int version_id)
{
    CPUState *env = opaque;

    return env->fpregs_format_vmstate == 1;
}

static bool fpregs_is_0_mmx(void *opaque, int version_id)
{
    CPUState *env = opaque;
    int guess_mmx;

    guess_mmx = ((env->fptag_vmstate == 0xff) &&
                 (env->fpus_vmstate & 0x3800) == 0);
    return guess_mmx && env->fpregs_format_vmstate == 0;
}

static bool fpregs_is_0_no_mmx(void *opaque, int version_id)
{
    CPUState *env = opaque;
    int guess_mmx;

    guess_mmx = ((env->fptag_vmstate == 0xff) &&
                 (env->fpus_vmstate & 0x3800) == 0);
    return !guess_mmx && env->fpregs_format_vmstate == 0;
}

#define VMSTATE_FP_REGS(_field, _state, _n)                               \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1, vmstate_fpreg, FPReg), \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0_mmx, vmstate_fpreg_0_mmx, FPReg), \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0_no_mmx, vmstate_fpreg_0_no_mmx, FPReg)

#endif /* USE_X86LDOUBLE */

static bool version_is_5(void *opaque, int version_id)
{
    return version_id == 5;
}

#ifdef TARGET_X86_64
static bool less_than_7(void *opaque, int version_id)
{
    return version_id < 7;
}

static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
{
    uint64_t *v = pv;
    *v = qemu_get_be32(f);
    return 0;
}

static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
{
    uint64_t *v = pv;
    qemu_put_be32(f, *v);
}

const VMStateInfo vmstate_hack_uint64_as_uint32 = {
    .name = "uint64_as_uint32",
    .get  = get_uint64_as_uint32,
    .put  = put_uint64_as_uint32,
};

#define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
    VMSTATE_SINGLE_TEST(_f, _s, _t, vmstate_hack_uint64_as_uint32, uint64_t)
#endif

static void cpu_pre_save(void *opaque)
{
    CPUState *env = opaque;
    int i, bit;

    cpu_synchronize_state(env);

    /* FPU */
    env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
    env->fptag_vmstate = 0;
    for(i = 0; i < 8; i++) {
        env->fptag_vmstate |= ((!env->fptags[i]) << i);
    }

#ifdef USE_X86LDOUBLE
    env->fpregs_format_vmstate = 0;
#else
    env->fpregs_format_vmstate = 1;
#endif

    /* There can only be one pending IRQ set in the bitmap at a time, so try
       to find it and save its number instead (-1 for none). */
    env->pending_irq_vmstate = -1;
    for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
        if (env->interrupt_bitmap[i]) {
            bit = ctz64(env->interrupt_bitmap[i]);
            env->pending_irq_vmstate = i * 64 + bit;
            break;
        }
    }
}

static int cpu_pre_load(void *opaque)
{
    CPUState *env = opaque;

    cpu_synchronize_state(env);
    return 0;
}

static int cpu_post_load(void *opaque, int version_id)
{
    CPUState *env = opaque;
    int i;

    /* XXX: restore FPU round state */
    env->fpstt = (env->fpus_vmstate >> 11) & 7;
    env->fpus = env->fpus_vmstate & ~0x3800;
    env->fptag_vmstate ^= 0xff;
    for(i = 0; i < 8; i++) {
        env->fptags[i] = (env->fptag_vmstate >> i) & 1;
    }

    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
    for (i = 0; i < 4; i++)
        hw_breakpoint_insert(env, i);

    if (version_id >= 9) {
        memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
        if (env->pending_irq_vmstate >= 0) {
            env->interrupt_bitmap[env->pending_irq_vmstate / 64] |=
                (uint64_t)1 << (env->pending_irq_vmstate % 64);
        }
    }

    return cpu_post_load(env, version_id);
}

const VMStateDescription vmstate_cpu = {
    .name = "cpu",
    .version_id = CPU_SAVE_VERSION,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .pre_save = cpu_pre_save,
    .pre_load = cpu_pre_load,
    .post_load = cpu_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(regs, CPUState, CPU_NB_REGS),
        VMSTATE_UINTTL(eip, CPUState),
        VMSTATE_UINTTL(eflags, CPUState),
        VMSTATE_UINT32(hflags, CPUState),
        /* FPU */
        VMSTATE_UINT16(fpuc, CPUState),
        VMSTATE_UINT16(fpus_vmstate, CPUState),
        VMSTATE_UINT16(fptag_vmstate, CPUState),
        VMSTATE_UINT16(fpregs_format_vmstate, CPUState),
        VMSTATE_FP_REGS(fpregs, CPUState, 8),

        VMSTATE_SEGMENT_ARRAY(segs, CPUState, 6),
        VMSTATE_SEGMENT(ldt, CPUState),
        VMSTATE_SEGMENT(tr, CPUState),
        VMSTATE_SEGMENT(gdt, CPUState),
        VMSTATE_SEGMENT(idt, CPUState),

        VMSTATE_UINT32(sysenter_cs, CPUState),
#ifdef TARGET_X86_64
        /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
        VMSTATE_HACK_UINT32(sysenter_esp, CPUState, less_than_7),
        VMSTATE_HACK_UINT32(sysenter_eip, CPUState, less_than_7),
        VMSTATE_UINTTL_V(sysenter_esp, CPUState, 7),
        VMSTATE_UINTTL_V(sysenter_eip, CPUState, 7),
#else
        VMSTATE_UINTTL(sysenter_esp, CPUState),
        VMSTATE_UINTTL(sysenter_eip, CPUState),
#endif

        VMSTATE_UINTTL(cr[0], CPUState),
        VMSTATE_UINTTL(cr[2], CPUState),
        VMSTATE_UINTTL(cr[3], CPUState),
        VMSTATE_UINTTL(cr[4], CPUState),
        VMSTATE_UINTTL_ARRAY(dr, CPUState, 8),
        /* MMU */
        VMSTATE_INT32(a20_mask, CPUState),
        /* XMM */
        VMSTATE_UINT32(mxcsr, CPUState),
        VMSTATE_XMM_REGS(xmm_regs, CPUState, CPU_NB_REGS),

#ifdef TARGET_X86_64
        VMSTATE_UINT64(efer, CPUState),
        VMSTATE_UINT64(star, CPUState),
        VMSTATE_UINT64(lstar, CPUState),
        VMSTATE_UINT64(cstar, CPUState),
        VMSTATE_UINT64(fmask, CPUState),
        VMSTATE_UINT64(kernelgsbase, CPUState),
#endif
        VMSTATE_UINT32_V(smbase, CPUState, 4),

        VMSTATE_UINT64_V(pat, CPUState, 5),
        VMSTATE_UINT32_V(hflags2, CPUState, 5),

        VMSTATE_UINT32_TEST(halted, CPUState, version_is_5),
        VMSTATE_UINT64_V(vm_hsave, CPUState, 5),
        VMSTATE_UINT64_V(vm_vmcb, CPUState, 5),
        VMSTATE_UINT64_V(tsc_offset, CPUState, 5),
        VMSTATE_UINT64_V(intercept, CPUState, 5),
        VMSTATE_UINT16_V(intercept_cr_read, CPUState, 5),
        VMSTATE_UINT16_V(intercept_cr_write, CPUState, 5),
        VMSTATE_UINT16_V(intercept_dr_read, CPUState, 5),
        VMSTATE_UINT16_V(intercept_dr_write, CPUState, 5),
        VMSTATE_UINT32_V(intercept_exceptions, CPUState, 5),
        VMSTATE_UINT8_V(v_tpr, CPUState, 5),
        /* MTRRs */
        VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUState, 11, 8),
        VMSTATE_UINT64_V(mtrr_deftype, CPUState, 8),
        VMSTATE_MTRR_VARS(mtrr_var, CPUState, 8, 8),
        /* KVM-related states */
        VMSTATE_INT32_V(pending_irq_vmstate, CPUState, 9),
        VMSTATE_UINT32_V(mp_state, CPUState, 9),
        VMSTATE_UINT64_V(tsc, CPUState, 9),
        /* MCE */
        VMSTATE_UINT64_V(mcg_cap, CPUState, 10),
        VMSTATE_UINT64_V(mcg_status, CPUState, 10),
        VMSTATE_UINT64_V(mcg_ctl, CPUState, 10),
        VMSTATE_UINT64_ARRAY_V(mce_banks, CPUState, MCE_BANKS_DEF *4, 10),
        /* rdtscp */
        VMSTATE_UINT64_V(tsc_aux, CPUState, 11),
        VMSTATE_END_OF_LIST()
    }
};

void cpu_save(QEMUFile *f, void *opaque)
{
    vmstate_save_state(f, &vmstate_cpu, opaque);
}

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3	#include "hw/pc.h"
	4	#include "hw/isa.h"
6ad8702a	5	#include "host-utils.h"
8dd3dca3 AJ	6
8dd3dca3 AJ	7	#include "exec-all.h"
b0a46a33	8	#include "kvm.h"
8dd3dca3	9
66e6d55b JQ	10	static const VMStateDescription vmstate_segment = {
	11	.name = "segment",
	12	.version_id = 1,
	13	.minimum_version_id = 1,
	14	.minimum_version_id_old = 1,
	15	.fields = (VMStateField []) {
	16	VMSTATE_UINT32(selector, SegmentCache),
	17	VMSTATE_UINTTL(base, SegmentCache),
	18	VMSTATE_UINT32(limit, SegmentCache),
	19	VMSTATE_UINT32(flags, SegmentCache),
	20	VMSTATE_END_OF_LIST()
	21	}
	22	};
	23
0cb892aa JQ	24	#define VMSTATE_SEGMENT(_field, _state) { \
	25	.name = (stringify(_field)), \
	26	.size = sizeof(SegmentCache), \
	27	.vmsd = &vmstate_segment, \
	28	.flags = VMS_STRUCT, \
	29	.offset = offsetof(_state, _field) \
	30	+ type_check(SegmentCache,typeof_field(_state, _field)) \
8dd3dca3 AJ	31	}
8dd3dca3 AJ	32
0cb892aa JQ	33	#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
0cb892aa JQ	34	VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
8dd3dca3	35
fc3b0aa2 JQ	36	static const VMStateDescription vmstate_xmm_reg = {
	37	.name = "xmm_reg",
	38	.version_id = 1,
	39	.minimum_version_id = 1,
	40	.minimum_version_id_old = 1,
	41	.fields = (VMStateField []) {
	42	VMSTATE_UINT64(XMM_Q(0), XMMReg),
	43	VMSTATE_UINT64(XMM_Q(1), XMMReg),
	44	VMSTATE_END_OF_LIST()
	45	}
	46	};
	47
0cb892aa JQ	48	#define VMSTATE_XMM_REGS(_field, _state, _n) \
0cb892aa JQ	49	VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
fc3b0aa2	50
216c07c3 JQ	51	static const VMStateDescription vmstate_mtrr_var = {
	52	.name = "mtrr_var",
	53	.version_id = 1,
	54	.minimum_version_id = 1,
	55	.minimum_version_id_old = 1,
	56	.fields = (VMStateField []) {
	57	VMSTATE_UINT64(base, MTRRVar),
	58	VMSTATE_UINT64(mask, MTRRVar),
	59	VMSTATE_END_OF_LIST()
	60	}
	61	};
	62
0cb892aa JQ	63	#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
0cb892aa JQ	64	VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
216c07c3	65
0cb892aa	66	static void put_fpreg_error(QEMUFile f, void opaque, size_t size)
216c07c3	67	{
0cb892aa JQ	68	fprintf(stderr, "call put_fpreg() with invalid arguments\n");
0cb892aa JQ	69	exit(0);
216c07c3 JQ	70	}
216c07c3 JQ	71
3c8ce630 JQ	72	#ifdef USE_X86LDOUBLE
	73	/* XXX: add that in a FPU generic layer */
	74	union x86_longdouble {
	75	uint64_t mant;
	76	uint16_t exp;
	77	};
	78
	79	#define MANTD1(fp) (fp & ((1LL << 52) - 1))
	80	#define EXPBIAS1 1023
	81	#define EXPD1(fp) ((fp >> 52) & 0x7FF)
	82	#define SIGND1(fp) ((fp >> 32) & 0x80000000)
	83
	84	static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
	85	{
	86	int e;
	87	/* mantissa */
	88	p->mant = (MANTD1(temp) << 11) \| (1LL << 63);
	89	/* exponent + sign */
	90	e = EXPD1(temp) - EXPBIAS1 + 16383;
	91	e \|= SIGND1(temp) >> 16;
	92	p->exp = e;
	93	}
	94
	95	static int get_fpreg(QEMUFile f, void opaque, size_t size)
	96	{
	97	FPReg *fp_reg = opaque;
	98	uint64_t mant;
	99	uint16_t exp;
	100
	101	qemu_get_be64s(f, &mant);
	102	qemu_get_be16s(f, &exp);
	103	fp_reg->d = cpu_set_fp80(mant, exp);
	104	return 0;
	105	}
	106
	107	static void put_fpreg(QEMUFile f, void opaque, size_t size)
	108	{
	109	FPReg *fp_reg = opaque;
	110	uint64_t mant;
	111	uint16_t exp;
	112	/* we save the real CPU data (in case of MMX usage only 'mant'
	113	contains the MMX register */
	114	cpu_get_fp80(&mant, &exp, fp_reg->d);
	115	qemu_put_be64s(f, &mant);
	116	qemu_put_be16s(f, &exp);
	117	}
	118
0cb892aa JQ	119	const VMStateInfo vmstate_fpreg = {
	120	.name = "fpreg",
	121	.get = get_fpreg,
	122	.put = put_fpreg,
	123	};
	124
3c8ce630 JQ	125	static int get_fpreg_1_mmx(QEMUFile f, void opaque, size_t size)
	126	{
	127	union x86_longdouble *p = opaque;
	128	uint64_t mant;
	129
	130	qemu_get_be64s(f, &mant);
	131	p->mant = mant;
	132	p->exp = 0xffff;
	133	return 0;
	134	}
	135
0cb892aa JQ	136	const VMStateInfo vmstate_fpreg_1_mmx = {
	137	.name = "fpreg_1_mmx",
	138	.get = get_fpreg_1_mmx,
	139	.put = put_fpreg_error,
	140	};
	141
3c8ce630 JQ	142	static int get_fpreg_1_no_mmx(QEMUFile f, void opaque, size_t size)
	143	{
	144	union x86_longdouble *p = opaque;
	145	uint64_t mant;
	146
	147	qemu_get_be64s(f, &mant);
	148	fp64_to_fp80(p, mant);
	149	return 0;
	150	}
	151
0cb892aa JQ	152	const VMStateInfo vmstate_fpreg_1_no_mmx = {
	153	.name = "fpreg_1_no_mmx",
	154	.get = get_fpreg_1_no_mmx,
	155	.put = put_fpreg_error,
	156	};
	157
	158	static bool fpregs_is_0(void *opaque, int version_id)
	159	{
	160	CPUState *env = opaque;
	161
	162	return (env->fpregs_format_vmstate == 0);
	163	}
	164
	165	static bool fpregs_is_1_mmx(void *opaque, int version_id)
	166	{
	167	CPUState *env = opaque;
	168	int guess_mmx;
	169
	170	guess_mmx = ((env->fptag_vmstate == 0xff) &&
	171	(env->fpus_vmstate & 0x3800) == 0);
	172	return (guess_mmx && (env->fpregs_format_vmstate == 1));
	173	}
	174
	175	static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
	176	{
	177	CPUState *env = opaque;
	178	int guess_mmx;
	179
	180	guess_mmx = ((env->fptag_vmstate == 0xff) &&
	181	(env->fpus_vmstate & 0x3800) == 0);
	182	return (!guess_mmx && (env->fpregs_format_vmstate == 1));
	183	}
	184
	185	#define VMSTATE_FP_REGS(_field, _state, _n) \
	186	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
	187	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
	188	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
	189
3c8ce630 JQ	190	#else
	191	static int get_fpreg(QEMUFile f, void opaque, size_t size)
	192	{
	193	FPReg *fp_reg = opaque;
	194
	195	qemu_get_be64s(f, &fp_reg->mmx.MMX_Q(0));
	196	return 0;
	197	}
	198
	199	static void put_fpreg(QEMUFile f, void opaque, size_t size)
	200	{
	201	FPReg *fp_reg = opaque;
	202	/* if we use doubles for float emulation, we save the doubles to
	203	avoid losing information in case of MMX usage. It can give
	204	problems if the image is restored on a CPU where long
	205	doubles are used instead. */
	206	qemu_put_be64s(f, &fp_reg->mmx.MMX_Q(0));
	207	}
	208
0cb892aa JQ	209	const VMStateInfo vmstate_fpreg = {
	210	.name = "fpreg",
	211	.get = get_fpreg,
	212	.put = put_fpreg,
	213	};
	214
3c8ce630 JQ	215	static int get_fpreg_0_mmx(QEMUFile f, void opaque, size_t size)
	216	{
	217	FPReg *fp_reg = opaque;
	218	uint64_t mant;
	219	uint16_t exp;
	220
	221	qemu_get_be64s(f, &mant);
	222	qemu_get_be16s(f, &exp);
	223	fp_reg->mmx.MMX_Q(0) = mant;
	224	return 0;
	225	}
	226
0cb892aa JQ	227	const VMStateInfo vmstate_fpreg_0_mmx = {
	228	.name = "fpreg_0_mmx",
	229	.get = get_fpreg_0_mmx,
	230	.put = put_fpreg_error,
	231	};
	232
3c8ce630 JQ	233	static int get_fpreg_0_no_mmx(QEMUFile f, void opaque, size_t size)
	234	{
	235	FPReg *fp_reg = opaque;
	236	uint64_t mant;
	237	uint16_t exp;
	238
	239	qemu_get_be64s(f, &mant);
	240	qemu_get_be16s(f, &exp);
	241
	242	fp_reg->d = cpu_set_fp80(mant, exp);
	243	return 0;
	244	}
	245
0cb892aa JQ	246	const VMStateInfo vmstate_fpreg_0_no_mmx = {
	247	.name = "fpreg_0_no_mmx",
	248	.get = get_fpreg_0_no_mmx,
	249	.put = put_fpreg_error,
	250	};
	251
	252	static bool fpregs_is_1(void *opaque, int version_id)
	253	{
	254	CPUState *env = opaque;
	255
	256	return env->fpregs_format_vmstate == 1;
	257	}
	258
	259	static bool fpregs_is_0_mmx(void *opaque, int version_id)
	260	{
	261	CPUState *env = opaque;
	262	int guess_mmx;
	263
	264	guess_mmx = ((env->fptag_vmstate == 0xff) &&
	265	(env->fpus_vmstate & 0x3800) == 0);
	266	return guess_mmx && env->fpregs_format_vmstate == 0;
	267	}
	268
	269	static bool fpregs_is_0_no_mmx(void *opaque, int version_id)
	270	{
	271	CPUState *env = opaque;
	272	int guess_mmx;
	273
	274	guess_mmx = ((env->fptag_vmstate == 0xff) &&
	275	(env->fpus_vmstate & 0x3800) == 0);
	276	return !guess_mmx && env->fpregs_format_vmstate == 0;
	277	}
	278
	279	#define VMSTATE_FP_REGS(_field, _state, _n) \
	280	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1, vmstate_fpreg, FPReg), \
	281	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0_mmx, vmstate_fpreg_0_mmx, FPReg), \
	282	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0_no_mmx, vmstate_fpreg_0_no_mmx, FPReg)
	283
3c8ce630 JQ	284	#endif /* USE_X86LDOUBLE */
3c8ce630 JQ	285
0cb892aa JQ	286	static bool version_is_5(void *opaque, int version_id)
	287	{
	288	return version_id == 5;
	289	}
	290
	291	#ifdef TARGET_X86_64
	292	static bool less_than_7(void *opaque, int version_id)
	293	{
	294	return version_id < 7;
	295	}
	296
	297	static int get_uint64_as_uint32(QEMUFile f, void pv, size_t size)
	298	{
	299	uint64_t *v = pv;
	300	*v = qemu_get_be32(f);
	301	return 0;
	302	}
	303
	304	static void put_uint64_as_uint32(QEMUFile f, void pv, size_t size)
	305	{
	306	uint64_t *v = pv;
	307	qemu_put_be32(f, *v);
	308	}
	309
	310	const VMStateInfo vmstate_hack_uint64_as_uint32 = {
	311	.name = "uint64_as_uint32",
	312	.get = get_uint64_as_uint32,
	313	.put = put_uint64_as_uint32,
	314	};
	315
	316	#define VMSTATE_HACK_UINT32(_f, _s, _t) \
	317	VMSTATE_SINGLE_TEST(_f, _s, _t, vmstate_hack_uint64_as_uint32, uint64_t)
	318	#endif
	319
c4c38c8c	320	static void cpu_pre_save(void *opaque)
8dd3dca3 AJ	321	{
8dd3dca3 AJ	322	CPUState *env = opaque;
059b8b1e	323	int i, bit;
8dd3dca3	324
4c0960c0	325	cpu_synchronize_state(env);
b0a46a33	326
8dd3dca3	327	/* FPU */
67b8f419	328	env->fpus_vmstate = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
cdc0c58f	329	env->fptag_vmstate = 0;
8dd3dca3	330	for(i = 0; i < 8; i++) {
cdc0c58f	331	env->fptag_vmstate \|= ((!env->fptags[i]) << i);
8dd3dca3 AJ	332	}
8dd3dca3 AJ	333
8dd3dca3	334	#ifdef USE_X86LDOUBLE
60a902f1	335	env->fpregs_format_vmstate = 0;
8dd3dca3	336	#else
60a902f1	337	env->fpregs_format_vmstate = 1;
8dd3dca3	338	#endif
c4c38c8c JQ	339
	340	/* There can only be one pending IRQ set in the bitmap at a time, so try
	341	to find it and save its number instead (-1 for none). */
	342	env->pending_irq_vmstate = -1;
	343	for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
	344	if (env->interrupt_bitmap[i]) {
	345	bit = ctz64(env->interrupt_bitmap[i]);
	346	env->pending_irq_vmstate = i * 64 + bit;
	347	break;
	348	}
	349	}
	350	}
	351
468f6581 JQ	352	static int cpu_pre_load(void *opaque)
	353	{
	354	CPUState *env = opaque;
	355
	356	cpu_synchronize_state(env);
	357	return 0;
	358	}
	359
	360	static int cpu_post_load(void *opaque, int version_id)
	361	{
	362	CPUState *env = opaque;
	363	int i;
	364
	365	/* XXX: restore FPU round state */
	366	env->fpstt = (env->fpus_vmstate >> 11) & 7;
	367	env->fpus = env->fpus_vmstate & ~0x3800;
	368	env->fptag_vmstate ^= 0xff;
	369	for(i = 0; i < 8; i++) {
	370	env->fptags[i] = (env->fptag_vmstate >> i) & 1;
	371	}
	372
	373	cpu_breakpoint_remove_all(env, BP_CPU);
	374	cpu_watchpoint_remove_all(env, BP_CPU);
	375	for (i = 0; i < 4; i++)
	376	hw_breakpoint_insert(env, i);
	377
	378	if (version_id >= 9) {
	379	memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
	380	if (env->pending_irq_vmstate >= 0) {
	381	env->interrupt_bitmap[env->pending_irq_vmstate / 64] \|=
	382	(uint64_t)1 << (env->pending_irq_vmstate % 64);
	383	}
	384	}
	385
	386	return cpu_post_load(env, version_id);
	387	}
	388
0cb892aa JQ	389	const VMStateDescription vmstate_cpu = {
	390	.name = "cpu",
	391	.version_id = CPU_SAVE_VERSION,
	392	.minimum_version_id = 3,
	393	.minimum_version_id_old = 3,
	394	.pre_save = cpu_pre_save,
	395	.pre_load = cpu_pre_load,
	396	.post_load = cpu_post_load,
	397	.fields = (VMStateField []) {
	398	VMSTATE_UINTTL_ARRAY(regs, CPUState, CPU_NB_REGS),
	399	VMSTATE_UINTTL(eip, CPUState),
	400	VMSTATE_UINTTL(eflags, CPUState),
	401	VMSTATE_UINT32(hflags, CPUState),
	402	/* FPU */
	403	VMSTATE_UINT16(fpuc, CPUState),
	404	VMSTATE_UINT16(fpus_vmstate, CPUState),
	405	VMSTATE_UINT16(fptag_vmstate, CPUState),
	406	VMSTATE_UINT16(fpregs_format_vmstate, CPUState),
	407	VMSTATE_FP_REGS(fpregs, CPUState, 8),
	408
	409	VMSTATE_SEGMENT_ARRAY(segs, CPUState, 6),
	410	VMSTATE_SEGMENT(ldt, CPUState),
	411	VMSTATE_SEGMENT(tr, CPUState),
	412	VMSTATE_SEGMENT(gdt, CPUState),
	413	VMSTATE_SEGMENT(idt, CPUState),
	414
	415	VMSTATE_UINT32(sysenter_cs, CPUState),
	416	#ifdef TARGET_X86_64
	417	/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
	418	VMSTATE_HACK_UINT32(sysenter_esp, CPUState, less_than_7),
	419	VMSTATE_HACK_UINT32(sysenter_eip, CPUState, less_than_7),
	420	VMSTATE_UINTTL_V(sysenter_esp, CPUState, 7),
	421	VMSTATE_UINTTL_V(sysenter_eip, CPUState, 7),
8dd3dca3	422	#else
0cb892aa JQ	423	VMSTATE_UINTTL(sysenter_esp, CPUState),
0cb892aa JQ	424	VMSTATE_UINTTL(sysenter_eip, CPUState),
3c8ce630	425	#endif
8dd3dca3	426
0cb892aa JQ	427	VMSTATE_UINTTL(cr[0], CPUState),
	428	VMSTATE_UINTTL(cr[2], CPUState),
	429	VMSTATE_UINTTL(cr[3], CPUState),
	430	VMSTATE_UINTTL(cr[4], CPUState),
	431	VMSTATE_UINTTL_ARRAY(dr, CPUState, 8),
	432	/* MMU */
	433	VMSTATE_INT32(a20_mask, CPUState),
	434	/* XMM */
	435	VMSTATE_UINT32(mxcsr, CPUState),
	436	VMSTATE_XMM_REGS(xmm_regs, CPUState, CPU_NB_REGS),
8dd3dca3 AJ	437
8dd3dca3 AJ	438	#ifdef TARGET_X86_64
0cb892aa JQ	439	VMSTATE_UINT64(efer, CPUState),
	440	VMSTATE_UINT64(star, CPUState),
	441	VMSTATE_UINT64(lstar, CPUState),
	442	VMSTATE_UINT64(cstar, CPUState),
	443	VMSTATE_UINT64(fmask, CPUState),
	444	VMSTATE_UINT64(kernelgsbase, CPUState),
8dd3dca3	445	#endif
0cb892aa JQ	446	VMSTATE_UINT32_V(smbase, CPUState, 4),
	447
	448	VMSTATE_UINT64_V(pat, CPUState, 5),
	449	VMSTATE_UINT32_V(hflags2, CPUState, 5),
	450
	451	VMSTATE_UINT32_TEST(halted, CPUState, version_is_5),
	452	VMSTATE_UINT64_V(vm_hsave, CPUState, 5),
	453	VMSTATE_UINT64_V(vm_vmcb, CPUState, 5),
	454	VMSTATE_UINT64_V(tsc_offset, CPUState, 5),
	455	VMSTATE_UINT64_V(intercept, CPUState, 5),
	456	VMSTATE_UINT16_V(intercept_cr_read, CPUState, 5),
	457	VMSTATE_UINT16_V(intercept_cr_write, CPUState, 5),
	458	VMSTATE_UINT16_V(intercept_dr_read, CPUState, 5),
	459	VMSTATE_UINT16_V(intercept_dr_write, CPUState, 5),
	460	VMSTATE_UINT32_V(intercept_exceptions, CPUState, 5),
	461	VMSTATE_UINT8_V(v_tpr, CPUState, 5),
dd5e3b17	462	/* MTRRs */
0cb892aa JQ	463	VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUState, 11, 8),
	464	VMSTATE_UINT64_V(mtrr_deftype, CPUState, 8),
	465	VMSTATE_MTRR_VARS(mtrr_var, CPUState, 8, 8),
	466	/* KVM-related states */
	467	VMSTATE_INT32_V(pending_irq_vmstate, CPUState, 9),
	468	VMSTATE_UINT32_V(mp_state, CPUState, 9),
	469	VMSTATE_UINT64_V(tsc, CPUState, 9),
	470	/* MCE */
	471	VMSTATE_UINT64_V(mcg_cap, CPUState, 10),
	472	VMSTATE_UINT64_V(mcg_status, CPUState, 10),
	473	VMSTATE_UINT64_V(mcg_ctl, CPUState, 10),
	474	VMSTATE_UINT64_ARRAY_V(mce_banks, CPUState, MCE_BANKS_DEF *4, 10),
	475	/* rdtscp */
	476	VMSTATE_UINT64_V(tsc_aux, CPUState, 11),
	477	VMSTATE_END_OF_LIST()
79c4f6b0	478	}
0cb892aa	479	};
79c4f6b0	480
0cb892aa JQ	481	void cpu_save(QEMUFile f, void opaque)
	482	{
	483	vmstate_save_state(f, &vmstate_cpu, opaque);
	484	}
1f76b9b9	485
0cb892aa JQ	486	int cpu_load(QEMUFile f, void opaque, int version_id)
	487	{
	488	return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
8dd3dca3	489	}