[qemu.git] / hw / apic_common.c

/*
 *  APIC support - common bits of emulated and KVM kernel model
 *
 *  Copyright (c) 2004-2005 Fabrice Bellard
 *  Copyright (c) 2011      Jan Kiszka, Siemens AG
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 */
#include "apic.h"
#include "apic_internal.h"
#include "trace.h"

static int apic_irq_delivered;

void cpu_set_apic_base(DeviceState *d, uint64_t val)
{
    trace_cpu_set_apic_base(val);

    if (d) {
        APICCommonState *s = APIC_COMMON(d);
        APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
        info->set_base(s, val);
    }
}

uint64_t cpu_get_apic_base(DeviceState *d)
{
    if (d) {
        APICCommonState *s = APIC_COMMON(d);
        trace_cpu_get_apic_base((uint64_t)s->apicbase);
        return s->apicbase;
    } else {
        trace_cpu_get_apic_base(0);
        return 0;
    }
}

void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
{
    APICCommonState *s;
    APICCommonClass *info;

    if (!d) {
        return;
    }

    s = APIC_COMMON(d);
    info = APIC_COMMON_GET_CLASS(s);

    info->set_tpr(s, val);
}

uint8_t cpu_get_apic_tpr(DeviceState *d)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);

    return s ? s->tpr >> 4 : 0;
}

void apic_report_irq_delivered(int delivered)
{
    apic_irq_delivered += delivered;

    trace_apic_report_irq_delivered(apic_irq_delivered);
}

void apic_reset_irq_delivered(void)
{
    trace_apic_reset_irq_delivered(apic_irq_delivered);

    apic_irq_delivered = 0;
}

int apic_get_irq_delivered(void)
{
    trace_apic_get_irq_delivered(apic_irq_delivered);

    return apic_irq_delivered;
}

void apic_deliver_nmi(DeviceState *d)
{
    APICCommonState *s = APIC_COMMON(d);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    info->external_nmi(s);
}

bool apic_next_timer(APICCommonState *s, int64_t current_time)
{
    int64_t d;

    /* We need to store the timer state separately to support APIC
     * implementations that maintain a non-QEMU timer, e.g. inside the
     * host kernel. This open-coded state allows us to migrate between
     * both models. */
    s->timer_expiry = -1;

    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
        return false;
    }

    d = (current_time - s->initial_count_load_time) >> s->count_shift;

    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
        if (!s->initial_count) {
            return false;
        }
        d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
            ((uint64_t)s->initial_count + 1);
    } else {
        if (d >= s->initial_count) {
            return false;
        }
        d = (uint64_t)s->initial_count + 1;
    }
    s->next_time = s->initial_count_load_time + (d << s->count_shift);
    s->timer_expiry = s->next_time;
    return true;
}

void apic_init_reset(DeviceState *d)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
    int i;

    if (!s) {
        return;
    }
    s->tpr = 0;
    s->spurious_vec = 0xff;
    s->log_dest = 0;
    s->dest_mode = 0xf;
    memset(s->isr, 0, sizeof(s->isr));
    memset(s->tmr, 0, sizeof(s->tmr));
    memset(s->irr, 0, sizeof(s->irr));
    for (i = 0; i < APIC_LVT_NB; i++) {
        s->lvt[i] = APIC_LVT_MASKED;
    }
    s->esr = 0;
    memset(s->icr, 0, sizeof(s->icr));
    s->divide_conf = 0;
    s->count_shift = 0;
    s->initial_count = 0;
    s->initial_count_load_time = 0;
    s->next_time = 0;
    s->wait_for_sipi = 1;

    if (s->timer) {
        qemu_del_timer(s->timer);
    }
    s->timer_expiry = -1;
}

static void apic_reset_common(DeviceState *d)
{
    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
    bool bsp;

    bsp = cpu_is_bsp(s->cpu_env);
    s->apicbase = 0xfee00000 |
        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;

    apic_init_reset(d);

    if (bsp) {
        /*
         * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
         * time typically by BIOS, so PIC interrupt can be delivered to the
         * processor when local APIC is enabled.
         */
        s->lvt[APIC_LVT_LINT0] = 0x700;
    }
}

/* This function is only used for old state version 1 and 2 */
static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
{
    APICCommonState *s = opaque;
    int i;

    if (version_id > 2) {
        return -EINVAL;
    }

    /* XXX: what if the base changes? (registered memory regions) */
    qemu_get_be32s(f, &s->apicbase);
    qemu_get_8s(f, &s->id);
    qemu_get_8s(f, &s->arb_id);
    qemu_get_8s(f, &s->tpr);
    qemu_get_be32s(f, &s->spurious_vec);
    qemu_get_8s(f, &s->log_dest);
    qemu_get_8s(f, &s->dest_mode);
    for (i = 0; i < 8; i++) {
        qemu_get_be32s(f, &s->isr[i]);
        qemu_get_be32s(f, &s->tmr[i]);
        qemu_get_be32s(f, &s->irr[i]);
    }
    for (i = 0; i < APIC_LVT_NB; i++) {
        qemu_get_be32s(f, &s->lvt[i]);
    }
    qemu_get_be32s(f, &s->esr);
    qemu_get_be32s(f, &s->icr[0]);
    qemu_get_be32s(f, &s->icr[1]);
    qemu_get_be32s(f, &s->divide_conf);
    s->count_shift = qemu_get_be32(f);
    qemu_get_be32s(f, &s->initial_count);
    s->initial_count_load_time = qemu_get_be64(f);
    s->next_time = qemu_get_be64(f);

    if (version_id >= 2) {
        qemu_get_timer(f, s->timer);
    }
    return 0;
}

static int apic_init_common(SysBusDevice *dev)
{
    APICCommonState *s = APIC_COMMON(dev);
    APICCommonClass *info;
    static int apic_no;

    if (apic_no >= MAX_APICS) {
        return -1;
    }
    s->idx = apic_no++;

    info = APIC_COMMON_GET_CLASS(s);
    info->init(s);

    sysbus_init_mmio(&s->busdev, &s->io_memory);
    return 0;
}

static int apic_dispatch_post_load(void *opaque, int version_id)
{
    APICCommonState *s = APIC_COMMON(opaque);
    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    if (info->post_load) {
        info->post_load(s);
    }
    return 0;
}

static const VMStateDescription vmstate_apic_common = {
    .name = "apic",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = apic_load_old,
    .post_load = apic_dispatch_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(apicbase, APICCommonState),
        VMSTATE_UINT8(id, APICCommonState),
        VMSTATE_UINT8(arb_id, APICCommonState),
        VMSTATE_UINT8(tpr, APICCommonState),
        VMSTATE_UINT32(spurious_vec, APICCommonState),
        VMSTATE_UINT8(log_dest, APICCommonState),
        VMSTATE_UINT8(dest_mode, APICCommonState),
        VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
        VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
        VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
        VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
        VMSTATE_UINT32(esr, APICCommonState),
        VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
        VMSTATE_UINT32(divide_conf, APICCommonState),
        VMSTATE_INT32(count_shift, APICCommonState),
        VMSTATE_UINT32(initial_count, APICCommonState),
        VMSTATE_INT64(initial_count_load_time, APICCommonState),
        VMSTATE_INT64(next_time, APICCommonState),
        VMSTATE_INT64(timer_expiry,
                      APICCommonState), /* open-coded timer state */
        VMSTATE_END_OF_LIST()
    }
};

static Property apic_properties_common[] = {
    DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
    DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
    DEFINE_PROP_END_OF_LIST(),
};

static void apic_common_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_apic_common;
    dc->reset = apic_reset_common;
    dc->no_user = 1;
    dc->props = apic_properties_common;
    sc->init = apic_init_common;
}

static TypeInfo apic_common_type = {
    .name = TYPE_APIC_COMMON,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(APICCommonState),
    .class_size = sizeof(APICCommonClass),
    .class_init = apic_common_class_init,
    .abstract = true,
};

static void register_devices(void)
{
    type_register_static(&apic_common_type);
}

device_init(register_devices);
Commit	Line	Data
dae01685 JK	1	/*
	2	* APIC support - common bits of emulated and KVM kernel model
	3	*
	4	* Copyright (c) 2004-2005 Fabrice Bellard
	5	* Copyright (c) 2011 Jan Kiszka, Siemens AG
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>
	19	*/
	20	#include "apic.h"
	21	#include "apic_internal.h"
	22	#include "trace.h"
	23
	24	static int apic_irq_delivered;
	25
	26	void cpu_set_apic_base(DeviceState *d, uint64_t val)
	27	{
dae01685 JK	28	trace_cpu_set_apic_base(val);
dae01685 JK	29
999e12bb AL	30	if (d) {
	31	APICCommonState *s = APIC_COMMON(d);
	32	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685 JK	33	info->set_base(s, val);
	34	}
	35	}
	36
	37	uint64_t cpu_get_apic_base(DeviceState *d)
	38	{
999e12bb AL	39	if (d) {
	40	APICCommonState *s = APIC_COMMON(d);
	41	trace_cpu_get_apic_base((uint64_t)s->apicbase);
	42	return s->apicbase;
	43	} else {
	44	trace_cpu_get_apic_base(0);
	45	return 0;
	46	}
dae01685 JK	47	}
	48
	49	void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
	50	{
999e12bb AL	51	APICCommonState *s;
999e12bb AL	52	APICCommonClass *info;
dae01685	53
999e12bb AL	54	if (!d) {
999e12bb AL	55	return;
dae01685	56	}
999e12bb AL	57
	58	s = APIC_COMMON(d);
	59	info = APIC_COMMON_GET_CLASS(s);
	60
	61	info->set_tpr(s, val);
dae01685 JK	62	}
	63
	64	uint8_t cpu_get_apic_tpr(DeviceState *d)
	65	{
	66	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
	67
	68	return s ? s->tpr >> 4 : 0;
	69	}
	70
	71	void apic_report_irq_delivered(int delivered)
	72	{
	73	apic_irq_delivered += delivered;
	74
	75	trace_apic_report_irq_delivered(apic_irq_delivered);
	76	}
	77
	78	void apic_reset_irq_delivered(void)
	79	{
	80	trace_apic_reset_irq_delivered(apic_irq_delivered);
	81
	82	apic_irq_delivered = 0;
	83	}
	84
	85	int apic_get_irq_delivered(void)
	86	{
	87	trace_apic_get_irq_delivered(apic_irq_delivered);
	88
	89	return apic_irq_delivered;
	90	}
	91
	92	void apic_deliver_nmi(DeviceState *d)
	93	{
999e12bb AL	94	APICCommonState *s = APIC_COMMON(d);
999e12bb AL	95	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
dae01685	96
dae01685 JK	97	info->external_nmi(s);
	98	}
	99
7a380ca3 JK	100	bool apic_next_timer(APICCommonState *s, int64_t current_time)
	101	{
	102	int64_t d;
	103
	104	/* We need to store the timer state separately to support APIC
	105	* implementations that maintain a non-QEMU timer, e.g. inside the
	106	* host kernel. This open-coded state allows us to migrate between
	107	* both models. */
	108	s->timer_expiry = -1;
	109
	110	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
	111	return false;
	112	}
	113
	114	d = (current_time - s->initial_count_load_time) >> s->count_shift;
	115
	116	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
	117	if (!s->initial_count) {
	118	return false;
	119	}
	120	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
	121	((uint64_t)s->initial_count + 1);
	122	} else {
	123	if (d >= s->initial_count) {
	124	return false;
	125	}
	126	d = (uint64_t)s->initial_count + 1;
	127	}
	128	s->next_time = s->initial_count_load_time + (d << s->count_shift);
	129	s->timer_expiry = s->next_time;
	130	return true;
	131	}
	132
dae01685 JK	133	void apic_init_reset(DeviceState *d)
	134	{
	135	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
	136	int i;
	137
	138	if (!s) {
	139	return;
	140	}
	141	s->tpr = 0;
	142	s->spurious_vec = 0xff;
	143	s->log_dest = 0;
	144	s->dest_mode = 0xf;
	145	memset(s->isr, 0, sizeof(s->isr));
	146	memset(s->tmr, 0, sizeof(s->tmr));
	147	memset(s->irr, 0, sizeof(s->irr));
	148	for (i = 0; i < APIC_LVT_NB; i++) {
	149	s->lvt[i] = APIC_LVT_MASKED;
	150	}
	151	s->esr = 0;
	152	memset(s->icr, 0, sizeof(s->icr));
	153	s->divide_conf = 0;
	154	s->count_shift = 0;
	155	s->initial_count = 0;
	156	s->initial_count_load_time = 0;
	157	s->next_time = 0;
	158	s->wait_for_sipi = 1;
	159
7a380ca3 JK	160	if (s->timer) {
	161	qemu_del_timer(s->timer);
	162	}
	163	s->timer_expiry = -1;
dae01685 JK	164	}
	165
	166	static void apic_reset_common(DeviceState *d)
	167	{
	168	APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
	169	bool bsp;
	170
	171	bsp = cpu_is_bsp(s->cpu_env);
	172	s->apicbase = 0xfee00000 \|
	173	(bsp ? MSR_IA32_APICBASE_BSP : 0) \| MSR_IA32_APICBASE_ENABLE;
	174
	175	apic_init_reset(d);
	176
	177	if (bsp) {
	178	/*
	179	* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
	180	* time typically by BIOS, so PIC interrupt can be delivered to the
	181	* processor when local APIC is enabled.
	182	*/
	183	s->lvt[APIC_LVT_LINT0] = 0x700;
	184	}
	185	}
	186
	187	/* This function is only used for old state version 1 and 2 */
	188	static int apic_load_old(QEMUFile f, void opaque, int version_id)
	189	{
	190	APICCommonState *s = opaque;
	191	int i;
	192
	193	if (version_id > 2) {
	194	return -EINVAL;
	195	}
	196
	197	/* XXX: what if the base changes? (registered memory regions) */
	198	qemu_get_be32s(f, &s->apicbase);
	199	qemu_get_8s(f, &s->id);
	200	qemu_get_8s(f, &s->arb_id);
	201	qemu_get_8s(f, &s->tpr);
	202	qemu_get_be32s(f, &s->spurious_vec);
	203	qemu_get_8s(f, &s->log_dest);
	204	qemu_get_8s(f, &s->dest_mode);
	205	for (i = 0; i < 8; i++) {
	206	qemu_get_be32s(f, &s->isr[i]);
	207	qemu_get_be32s(f, &s->tmr[i]);
	208	qemu_get_be32s(f, &s->irr[i]);
	209	}
	210	for (i = 0; i < APIC_LVT_NB; i++) {
	211	qemu_get_be32s(f, &s->lvt[i]);
	212	}
	213	qemu_get_be32s(f, &s->esr);
	214	qemu_get_be32s(f, &s->icr[0]);
	215	qemu_get_be32s(f, &s->icr[1]);
	216	qemu_get_be32s(f, &s->divide_conf);
	217	s->count_shift = qemu_get_be32(f);
	218	qemu_get_be32s(f, &s->initial_count);
	219	s->initial_count_load_time = qemu_get_be64(f);
	220	s->next_time = qemu_get_be64(f);
	221
	222	if (version_id >= 2) {
	223	qemu_get_timer(f, s->timer);
	224	}
	225	return 0;
	226	}
	227
228	static int apic_init_common(SysBusDevice *dev)
229	{
999e12bb AL	230	APICCommonState *s = APIC_COMMON(dev);
999e12bb AL	231	APICCommonClass *info;
dae01685 JK	232	static int apic_no;
	233
	234	if (apic_no >= MAX_APICS) {
	235	return -1;
	236	}
	237	s->idx = apic_no++;
	238
999e12bb	239	info = APIC_COMMON_GET_CLASS(s);
dae01685 JK	240	info->init(s);
	241
	242	sysbus_init_mmio(&s->busdev, &s->io_memory);
	243	return 0;
	244	}
	245
7a380ca3 JK	246	static int apic_dispatch_post_load(void *opaque, int version_id)
7a380ca3 JK	247	{
999e12bb AL	248	APICCommonState *s = APIC_COMMON(opaque);
999e12bb AL	249	APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
7a380ca3 JK	250
	251	if (info->post_load) {
	252	info->post_load(s);
	253	}
	254	return 0;
	255	}
	256
dae01685 JK	257	static const VMStateDescription vmstate_apic_common = {
	258	.name = "apic",
	259	.version_id = 3,
	260	.minimum_version_id = 3,
	261	.minimum_version_id_old = 1,
	262	.load_state_old = apic_load_old,
7a380ca3	263	.post_load = apic_dispatch_post_load,
dae01685 JK	264	.fields = (VMStateField[]) {
	265	VMSTATE_UINT32(apicbase, APICCommonState),
	266	VMSTATE_UINT8(id, APICCommonState),
	267	VMSTATE_UINT8(arb_id, APICCommonState),
	268	VMSTATE_UINT8(tpr, APICCommonState),
	269	VMSTATE_UINT32(spurious_vec, APICCommonState),
	270	VMSTATE_UINT8(log_dest, APICCommonState),
	271	VMSTATE_UINT8(dest_mode, APICCommonState),
	272	VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
	273	VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
	274	VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
	275	VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
	276	VMSTATE_UINT32(esr, APICCommonState),
	277	VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
	278	VMSTATE_UINT32(divide_conf, APICCommonState),
	279	VMSTATE_INT32(count_shift, APICCommonState),
	280	VMSTATE_UINT32(initial_count, APICCommonState),
	281	VMSTATE_INT64(initial_count_load_time, APICCommonState),
	282	VMSTATE_INT64(next_time, APICCommonState),
7a380ca3 JK	283	VMSTATE_INT64(timer_expiry,
7a380ca3 JK	284	APICCommonState), /* open-coded timer state */
dae01685 JK	285	VMSTATE_END_OF_LIST()
	286	}
	287	};
	288
	289	static Property apic_properties_common[] = {
	290	DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
	291	DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
	292	DEFINE_PROP_END_OF_LIST(),
	293	};
	294
999e12bb AL	295	static void apic_common_class_init(ObjectClass klass, void data)
	296	{
	297	SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	298	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	299
39bffca2 AL	300	dc->vmsd = &vmstate_apic_common;
	301	dc->reset = apic_reset_common;
	302	dc->no_user = 1;
	303	dc->props = apic_properties_common;
999e12bb AL	304	sc->init = apic_init_common;
999e12bb AL	305	}
dae01685	306
999e12bb AL	307	static TypeInfo apic_common_type = {
	308	.name = TYPE_APIC_COMMON,
	309	.parent = TYPE_SYS_BUS_DEVICE,
	310	.instance_size = sizeof(APICCommonState),
	311	.class_size = sizeof(APICCommonClass),
	312	.class_init = apic_common_class_init,
	313	.abstract = true,
	314	};
	315
999e12bb AL	316	static void register_devices(void)
	317	{
	318	type_register_static(&apic_common_type);
	319	}
	320
	321	device_init(register_devices);