[qemu.git] / pc-bios / canyonlands.dts

/*
 * Device Tree Source for AMCC Canyonlands (460EX)
 *
 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <[email protected]>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <1>;
	model = "amcc,canyonlands";
	compatible = "amcc,canyonlands";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,460EX";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
			dcr-controller;
			dcr-access-method = "native";
			next-level-cache = <&L2C0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller0 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC3: interrupt-controller3 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <3>;
		dcr-reg = <0x0f0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	SDR0: sdr {
		compatible = "ibm,sdr-460ex";
		dcr-reg = <0x00e 0x002>;
	};

	CPR0: cpr {
		compatible = "ibm,cpr-460ex";
		dcr-reg = <0x00c 0x002>;
	};

	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x160 0x003>;
		unused-units = <0x00000100>;
		idle-doze = <0x02000000>;
		standby = <0xfeff791d>;
	};

	L2C0: l2c {
		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
			   0x030 0x008>;	/* L2 cache DCR's */
		cache-line-size = <32>;		/* 32 bytes */
		cache-size = <262144>;		/* L2, 256K */
		interrupt-parent = <&UIC1>;
		interrupts = <11 1>;
	};

	plb {
		compatible = "ibm,plb-460ex", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: sdram {
			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
			dcr-reg = <0x010 0x002>;
		};

		CRYPTO: crypto@180000 {
			compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
			reg = <4 0x00180000 0x80400>;
			interrupt-parent = <&UIC0>;
			interrupts = <0x1d 0x4>;
		};

		HWRNG: hwrng@110000 {
			compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
			reg = <4 0x00110000 0x50>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <16>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-parent = <&UIC2>;
			interrupts = <	/*TXEOB*/ 0x6 0x4
					/*RXEOB*/ 0x7 0x4
					/*SERR*/  0x3 0x4
					/*TXDE*/  0x4 0x4
					/*RXDE*/  0x5 0x4>;
		};

		USB0: ehci@bffd0400 {
			compatible = "ibm,usb-ehci-460ex", "usb-ehci";
			interrupt-parent = <&UIC2>;
			interrupts = <0x1d 4>;
			reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
		};

		USB1: usb@bffd0000 {
			compatible = "ohci-le";
			reg = <4 0xbffd0000 0x60>;
			interrupt-parent = <&UIC2>;
			interrupts = <0x1e 4>;
		};

		USBOTG0: usbotg@bff80000 {
			compatible = "amcc,dwc-otg";
			reg = <0x4 0xbff80000 0x10000>;
			interrupt-parent = <&USBOTG0>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupts = <0x0 0x1 0x2>;
			interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
					 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
					 /* DMA */ 0x2 &UIC0 0xc 0x4>;
		};

		AHBDMA: dma@bffd0800 {
			compatible = "snps,dma-spear1340";
			reg = <4 0xbffd0800 0x400>;
			interrupt-parent = <&UIC3>;
			interrupts = <0x5 0x4>;
			#dma-cells = <3>;
		};

		SATA0: sata@bffd1000 {
			compatible = "amcc,sata-460ex";
			reg = <4 0xbffd1000 0x800>;
			interrupt-parent = <&UIC3>;
			interrupts = <0x0 0x4>;
			dmas = <&AHBDMA 0 1 0>;
			dma-names = "sata-dma";
		};

		POB0: opb {
			compatible = "ibm,opb-460ex", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-460ex", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <0x6 0x4>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0x00000000 0x00000000 0x04000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0x00000000 0x001e0000>;
					};
					partition@1e0000 {
						label = "dtb";
						reg = <0x001e0000 0x00020000>;
					};
					partition@200000 {
						label = "ramdisk";
						reg = <0x00200000 0x01400000>;
					};
					partition@1600000 {
						label = "jffs2";
						reg = <0x01600000 0x00400000>;
					};
					partition@1a00000 {
						label = "user";
						reg = <0x01a00000 0x02560000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <0x03f60000 0x00040000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <0x03fa0000 0x00060000>;
					};
				};

				cpld@2,0 {
					compatible = "amcc,ppc460ex-bcsr";
					reg = <2 0x0 0x9>;
				};

				ndfc@3,0 {
					compatible = "ibm,ndfc";
					reg = <0x00000003 0x00000000 0x00002000>;
					ccr = <0x00001000>;
					bank-settings = <0x80002222>;
					#address-cells = <1>;
					#size-cells = <1>;

					nand {
						#address-cells = <1>;
						#size-cells = <1>;

						partition@0 {
							label = "u-boot";
							reg = <0x00000000 0x00100000>;
						};
						partition@100000 {
							label = "user";
							reg = <0x00000000 0x03f00000>;
						};
					};
				};
			};

			UART0: serial@ef600300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600300 0x00000008>;
				virtual-reg = <0xef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <0x1 0x4>;
			};

			UART1: serial@ef600400 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600400 0x00000008>;
				virtual-reg = <0xef600400>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};

			IIC0: i2c@ef600700 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600700 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
				#address-cells = <1>;
				#size-cells = <0>;
                                rtc@68 {
                                        compatible = "st,m41t80";
                                        reg = <0x68>;
					interrupt-parent = <&UIC2>;
					interrupts = <0x19 0x8>;
                                };
                                sttm@48 {
                                        compatible = "ad,ad7414";
                                        reg = <0x48>;
					interrupt-parent = <&UIC1>;
					interrupts = <0x14 0x8>;
                                };
			};

			IIC1: i2c@ef600800 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600800 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x3 0x4>;
			};

			GPIO0: gpio@ef600b00 {
				compatible = "ibm,ppc4xx-gpio";
				reg = <0xef600b00 0x00000048>;
				gpio-controller;
			};

			ZMII0: emac-zmii@ef600d00 {
				compatible = "ibm,zmii-460ex", "ibm,zmii";
				reg = <0xef600d00 0x0000000c>;
			};

			RGMII0: emac-rgmii@ef601500 {
				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
				reg = <0xef601500 0x00000008>;
				has-mdio;
			};

			TAH0: emac-tah@ef601350 {
				compatible = "ibm,tah-460ex", "ibm,tah";
				reg = <0xef601350 0x00000030>;
			};

			TAH1: emac-tah@ef601450 {
				compatible = "ibm,tah-460ex", "ibm,tah";
				reg = <0xef601450 0x00000030>;
			};

			EMAC0: ethernet@ef600e00 {
				device_type = "network";
				compatible = "ibm,emac-460ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC0>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
				reg = <0xef600e00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				rx-fifo-size-gige = <16384>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				tah-device = <&TAH0>;
				tah-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};

			EMAC1: ethernet@ef600f00 {
				device_type = "network";
				compatible = "ibm,emac-460ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC1>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
				reg = <0xef600f00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <1>;
				mal-rx-channel = <8>;
				cell-index = <1>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				rx-fifo-size-gige = <16384>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <1>;
				tah-device = <&TAH1>;
				tah-channel = <1>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
				mdio-device = <&EMAC0>;
			};
		};

		PCIX0: pci@c0ec00000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
			primary;
			large-inbound-windows;
			enable-msi-hole;
			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0 to 0x3f */
			bus-range = <0x0 0x3f>;

			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
		};

		PCIE0: pciex@d00000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
			dcr-reg = <0x100 0x020>;
			sdr-base = <0x300>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 40 to 0x7f */
			bus-range = <0x40 0x7f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@d20000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
			dcr-reg = <0x120 0x020>;
			sdr-base = <0x340>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 80 to 0xbf */
			bus-range = <0x80 0xbf>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
		};

		MSI: ppc4xx-msi@C10000000 {
			compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
			reg = < 0xC 0x10000000 0x100>;
			sdr-base = <0x36C>;
			msi-data = <0x00000000>;
			msi-mask = <0x44440000>;
			interrupt-count = <3>;
			interrupts = <0 1 2 3>;
			interrupt-parent = <&UIC3>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &UIC3 0x18 1
					1 &UIC3 0x19 1
					2 &UIC3 0x1A 1
					3 &UIC3 0x1B 1>;
		};
	};
};
Commit	Line	Data
4b387f9e BZ	1	/*
	2	* Device Tree Source for AMCC Canyonlands (460EX)
	3	*
	4	* Copyright 2008-2009 DENX Software Engineering, Stefan Roese <[email protected]>
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without
	8	* any warranty of any kind, whether express or implied.
	9	*/
	10
	11	/dts-v1/;
	12
	13	/ {
	14	#address-cells = <2>;
	15	#size-cells = <1>;
	16	model = "amcc,canyonlands";
	17	compatible = "amcc,canyonlands";
	18	dcr-parent = <&{/cpus/cpu@0}>;
	19
	20	aliases {
	21	ethernet0 = &EMAC0;
	22	ethernet1 = &EMAC1;
	23	serial0 = &UART0;
	24	serial1 = &UART1;
	25	};
	26
	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	cpu@0 {
	32	device_type = "cpu";
	33	model = "PowerPC,460EX";
	34	reg = <0x00000000>;
	35	clock-frequency = <0>; /* Filled in by U-Boot */
	36	timebase-frequency = <0>; /* Filled in by U-Boot */
	37	i-cache-line-size = <32>;
	38	d-cache-line-size = <32>;
	39	i-cache-size = <32768>;
	40	d-cache-size = <32768>;
	41	dcr-controller;
	42	dcr-access-method = "native";
	43	next-level-cache = <&L2C0>;
	44	};
	45	};
	46
	47	memory {
	48	device_type = "memory";
	49	reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
	50	};
	51
	52	UIC0: interrupt-controller0 {
	53	compatible = "ibm,uic-460ex","ibm,uic";
	54	interrupt-controller;
	55	cell-index = <0>;
	56	dcr-reg = <0x0c0 0x009>;
	57	#address-cells = <0>;
	58	#size-cells = <0>;
	59	#interrupt-cells = <2>;
	60	};
	61
	62	UIC1: interrupt-controller1 {
	63	compatible = "ibm,uic-460ex","ibm,uic";
	64	interrupt-controller;
65	cell-index = <1>;
66	dcr-reg = <0x0d0 0x009>;
67	#address-cells = <0>;
68	#size-cells = <0>;
69	#interrupt-cells = <2>;
70	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71	interrupt-parent = <&UIC0>;
72	};
73
74	UIC2: interrupt-controller2 {
75	compatible = "ibm,uic-460ex","ibm,uic";
76	interrupt-controller;
77	cell-index = <2>;
78	dcr-reg = <0x0e0 0x009>;
79	#address-cells = <0>;
80	#size-cells = <0>;
81	#interrupt-cells = <2>;
82	interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83	interrupt-parent = <&UIC0>;
84	};
85
86	UIC3: interrupt-controller3 {
87	compatible = "ibm,uic-460ex","ibm,uic";
88	interrupt-controller;
89	cell-index = <3>;
90	dcr-reg = <0x0f0 0x009>;
91	#address-cells = <0>;
92	#size-cells = <0>;
93	#interrupt-cells = <2>;
94	interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95	interrupt-parent = <&UIC0>;
96	};
97
98	SDR0: sdr {
99	compatible = "ibm,sdr-460ex";
100	dcr-reg = <0x00e 0x002>;
101	};
102
103	CPR0: cpr {
104	compatible = "ibm,cpr-460ex";
105	dcr-reg = <0x00c 0x002>;
106	};
107
108	CPM0: cpm {
109	compatible = "ibm,cpm";
110	dcr-access-method = "native";
111	dcr-reg = <0x160 0x003>;
112	unused-units = <0x00000100>;
113	idle-doze = <0x02000000>;
114	standby = <0xfeff791d>;
115	};
116
117	L2C0: l2c {
118	compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
119	dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
120	0x030 0x008>; /* L2 cache DCR's */
121	cache-line-size = <32>; /* 32 bytes */
122	cache-size = <262144>; /* L2, 256K */
123	interrupt-parent = <&UIC1>;
124	interrupts = <11 1>;
125	};
126
127	plb {
128	compatible = "ibm,plb-460ex", "ibm,plb4";
129	#address-cells = <2>;
130	#size-cells = <1>;
131	ranges;
132	clock-frequency = <0>; /* Filled in by U-Boot */
133
134	SDRAM0: sdram {
135	compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
136	dcr-reg = <0x010 0x002>;
137	};
138
139	CRYPTO: crypto@180000 {
140	compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
141	reg = <4 0x00180000 0x80400>;
142	interrupt-parent = <&UIC0>;
143	interrupts = <0x1d 0x4>;
144	};
145
146	HWRNG: hwrng@110000 {
147	compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
148	reg = <4 0x00110000 0x50>;
149	};
150
151	MAL0: mcmal {
152	compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
153	dcr-reg = <0x180 0x062>;
154	num-tx-chans = <2>;
155	num-rx-chans = <16>;
156	#address-cells = <0>;
157	#size-cells = <0>;
158	interrupt-parent = <&UIC2>;
159	interrupts = < /TXEOB/ 0x6 0x4
160	/RXEOB/ 0x7 0x4
161	/SERR/ 0x3 0x4
162	/TXDE/ 0x4 0x4
163	/RXDE/ 0x5 0x4>;
164	};
165
166	USB0: ehci@bffd0400 {
167	compatible = "ibm,usb-ehci-460ex", "usb-ehci";
168	interrupt-parent = <&UIC2>;
169	interrupts = <0x1d 4>;
170	reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
171	};
172
173	USB1: usb@bffd0000 {
174	compatible = "ohci-le";
175	reg = <4 0xbffd0000 0x60>;
176	interrupt-parent = <&UIC2>;
177	interrupts = <0x1e 4>;
178	};
179
180	USBOTG0: usbotg@bff80000 {
181	compatible = "amcc,dwc-otg";
182	reg = <0x4 0xbff80000 0x10000>;
183	interrupt-parent = <&USBOTG0>;
184	#interrupt-cells = <1>;
185	#address-cells = <0>;
186	#size-cells = <0>;
187	interrupts = <0x0 0x1 0x2>;
188	interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
189	/* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
190	/* DMA */ 0x2 &UIC0 0xc 0x4>;
191	};
192
193	AHBDMA: dma@bffd0800 {
194	compatible = "snps,dma-spear1340";
195	reg = <4 0xbffd0800 0x400>;
196	interrupt-parent = <&UIC3>;
197	interrupts = <0x5 0x4>;
198	#dma-cells = <3>;
199	};
200
201	SATA0: sata@bffd1000 {
202	compatible = "amcc,sata-460ex";
203	reg = <4 0xbffd1000 0x800>;
204	interrupt-parent = <&UIC3>;
205	interrupts = <0x0 0x4>;
206	dmas = <&AHBDMA 0 1 0>;
207	dma-names = "sata-dma";
208	};
209
210	POB0: opb {
211	compatible = "ibm,opb-460ex", "ibm,opb";
212	#address-cells = <1>;
213	#size-cells = <1>;
214	ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
215	clock-frequency = <0>; /* Filled in by U-Boot */
216
217	EBC0: ebc {
218	compatible = "ibm,ebc-460ex", "ibm,ebc";
219	dcr-reg = <0x012 0x002>;
220	#address-cells = <2>;
221	#size-cells = <1>;
222	clock-frequency = <0>; /* Filled in by U-Boot */
223	/* ranges property is supplied by U-Boot */
224	interrupts = <0x6 0x4>;
225	interrupt-parent = <&UIC1>;
226
227	nor_flash@0,0 {
228	compatible = "amd,s29gl512n", "cfi-flash";
229	bank-width = <2>;
230	reg = <0x00000000 0x00000000 0x04000000>;
231	#address-cells = <1>;
232	#size-cells = <1>;
233	partition@0 {
234	label = "kernel";
235	reg = <0x00000000 0x001e0000>;
236	};
237	partition@1e0000 {
238	label = "dtb";
239	reg = <0x001e0000 0x00020000>;
240	};
241	partition@200000 {
242	label = "ramdisk";
243	reg = <0x00200000 0x01400000>;
244	};
245	partition@1600000 {
246	label = "jffs2";
247	reg = <0x01600000 0x00400000>;
248	};
249	partition@1a00000 {
250	label = "user";
251	reg = <0x01a00000 0x02560000>;
252	};
253	partition@3f60000 {
254	label = "env";
255	reg = <0x03f60000 0x00040000>;
256	};
257	partition@3fa0000 {
258	label = "u-boot";
259	reg = <0x03fa0000 0x00060000>;
260	};
261	};
262
263	cpld@2,0 {
264	compatible = "amcc,ppc460ex-bcsr";
265	reg = <2 0x0 0x9>;
266	};
267
268	ndfc@3,0 {
269	compatible = "ibm,ndfc";
270	reg = <0x00000003 0x00000000 0x00002000>;
271	ccr = <0x00001000>;
272	bank-settings = <0x80002222>;
273	#address-cells = <1>;
274	#size-cells = <1>;
275
276	nand {
277	#address-cells = <1>;
278	#size-cells = <1>;
279
280	partition@0 {
281	label = "u-boot";
282	reg = <0x00000000 0x00100000>;
283	};
284	partition@100000 {
285	label = "user";
286	reg = <0x00000000 0x03f00000>;
287	};
288	};
289	};
290	};
291
292	UART0: serial@ef600300 {
293	device_type = "serial";
294	compatible = "ns16550";
295	reg = <0xef600300 0x00000008>;
296	virtual-reg = <0xef600300>;
297	clock-frequency = <0>; /* Filled in by U-Boot */
298	current-speed = <0>; /* Filled in by U-Boot */
299	interrupt-parent = <&UIC1>;
300	interrupts = <0x1 0x4>;
301	};
302
303	UART1: serial@ef600400 {
304	device_type = "serial";
305	compatible = "ns16550";
306	reg = <0xef600400 0x00000008>;
307	virtual-reg = <0xef600400>;
308	clock-frequency = <0>; /* Filled in by U-Boot */
309	current-speed = <0>; /* Filled in by U-Boot */
310	interrupt-parent = <&UIC0>;
311	interrupts = <0x1 0x4>;
312	};
313
314	IIC0: i2c@ef600700 {
315	compatible = "ibm,iic-460ex", "ibm,iic";
316	reg = <0xef600700 0x00000014>;
317	interrupt-parent = <&UIC0>;
318	interrupts = <0x2 0x4>;
319	#address-cells = <1>;
320	#size-cells = <0>;
321	rtc@68 {
322	compatible = "st,m41t80";
323	reg = <0x68>;
324	interrupt-parent = <&UIC2>;
325	interrupts = <0x19 0x8>;
326	};
327	sttm@48 {
328	compatible = "ad,ad7414";
329	reg = <0x48>;
330	interrupt-parent = <&UIC1>;
331	interrupts = <0x14 0x8>;
332	};
333	};
334
335	IIC1: i2c@ef600800 {
336	compatible = "ibm,iic-460ex", "ibm,iic";
337	reg = <0xef600800 0x00000014>;
338	interrupt-parent = <&UIC0>;
339	interrupts = <0x3 0x4>;
340	};
341
342	GPIO0: gpio@ef600b00 {
343	compatible = "ibm,ppc4xx-gpio";
344	reg = <0xef600b00 0x00000048>;
345	gpio-controller;
346	};
347
348	ZMII0: emac-zmii@ef600d00 {
349	compatible = "ibm,zmii-460ex", "ibm,zmii";
350	reg = <0xef600d00 0x0000000c>;
351	};
352
353	RGMII0: emac-rgmii@ef601500 {
354	compatible = "ibm,rgmii-460ex", "ibm,rgmii";
355	reg = <0xef601500 0x00000008>;
356	has-mdio;
357	};
358
359	TAH0: emac-tah@ef601350 {
360	compatible = "ibm,tah-460ex", "ibm,tah";
361	reg = <0xef601350 0x00000030>;
362	};
363
364	TAH1: emac-tah@ef601450 {
365	compatible = "ibm,tah-460ex", "ibm,tah";
366	reg = <0xef601450 0x00000030>;
367	};
368
369	EMAC0: ethernet@ef600e00 {
370	device_type = "network";
371	compatible = "ibm,emac-460ex", "ibm,emac4sync";
372	interrupt-parent = <&EMAC0>;
373	interrupts = <0x0 0x1>;
374	#interrupt-cells = <1>;
375	#address-cells = <0>;
376	#size-cells = <0>;
377	interrupt-map = </Status/ 0x0 &UIC2 0x10 0x4
378	/Wake/ 0x1 &UIC2 0x14 0x4>;
379	reg = <0xef600e00 0x000000c4>;
380	local-mac-address = [000000000000]; /* Filled in by U-Boot */
381	mal-device = <&MAL0>;
382	mal-tx-channel = <0>;
383	mal-rx-channel = <0>;
384	cell-index = <0>;
385	max-frame-size = <9000>;
386	rx-fifo-size = <4096>;
387	tx-fifo-size = <2048>;
388	rx-fifo-size-gige = <16384>;
389	phy-mode = "rgmii";
390	phy-map = <0x00000000>;
391	rgmii-device = <&RGMII0>;
392	rgmii-channel = <0>;
393	tah-device = <&TAH0>;
394	tah-channel = <0>;
395	has-inverted-stacr-oc;
396	has-new-stacr-staopc;
397	};
398
399	EMAC1: ethernet@ef600f00 {
400	device_type = "network";
401	compatible = "ibm,emac-460ex", "ibm,emac4sync";
402	interrupt-parent = <&EMAC1>;
403	interrupts = <0x0 0x1>;
404	#interrupt-cells = <1>;
405	#address-cells = <0>;
406	#size-cells = <0>;
407	interrupt-map = </Status/ 0x0 &UIC2 0x11 0x4
408	/Wake/ 0x1 &UIC2 0x15 0x4>;
409	reg = <0xef600f00 0x000000c4>;
410	local-mac-address = [000000000000]; /* Filled in by U-Boot */
411	mal-device = <&MAL0>;
412	mal-tx-channel = <1>;
413	mal-rx-channel = <8>;
414	cell-index = <1>;
415	max-frame-size = <9000>;
416	rx-fifo-size = <4096>;
417	tx-fifo-size = <2048>;
418	rx-fifo-size-gige = <16384>;
419	phy-mode = "rgmii";
420	phy-map = <0x00000000>;
421	rgmii-device = <&RGMII0>;
422	rgmii-channel = <1>;
423	tah-device = <&TAH1>;
424	tah-channel = <1>;
425	has-inverted-stacr-oc;
426	has-new-stacr-staopc;
427	mdio-device = <&EMAC0>;
428	};
429	};
430
431	PCIX0: pci@c0ec00000 {
432	device_type = "pci";
433	#interrupt-cells = <1>;
434	#size-cells = <2>;
435	#address-cells = <3>;
436	compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
437	primary;
438	large-inbound-windows;
439	enable-msi-hole;
440	reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
441	0x00000000 0x00000000 0x00000000 /* no IACK cycles */
442	0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
443	0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
444	0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
445
446	/* Outbound ranges, one memory and one IO,
447	* later cannot be changed
448	*/
449	ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
450	0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
451	0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
452
453	/* Inbound 2GB range starting at 0 */
454	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
455
456	/* This drives busses 0 to 0x3f */
457	bus-range = <0x0 0x3f>;
458
459	/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
460	interrupt-map-mask = <0x0 0x0 0x0 0x0>;
461	interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
462	};
463
464	PCIE0: pciex@d00000000 {
465	device_type = "pci";
466	#interrupt-cells = <1>;
467	#size-cells = <2>;
468	#address-cells = <3>;
469	compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
470	primary;
471	port = <0x0>; /* port number */
472	reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
473	0x0000000c 0x08010000 0x00001000>; /* Registers */
474	dcr-reg = <0x100 0x020>;
475	sdr-base = <0x300>;
476
477	/* Outbound ranges, one memory and one IO,
478	* later cannot be changed
479	*/
480	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
481	0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
482	0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
483
484	/* Inbound 2GB range starting at 0 */
485	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
486
487	/* This drives busses 40 to 0x7f */
488	bus-range = <0x40 0x7f>;
489
490	/* Legacy interrupts (note the weird polarity, the bridge seems
491	* to invert PCIe legacy interrupts).
492	* We are de-swizzling here because the numbers are actually for
493	* port of the root complex virtual P2P bridge. But I want
494	* to avoid putting a node for it in the tree, so the numbers
495	* below are basically de-swizzled numbers.
496	* The real slot is on idsel 0, so the swizzling is 1:1
497	*/
498	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
499	interrupt-map = <
500	0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
501	0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
502	0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
503	0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
504	};
505
506	PCIE1: pciex@d20000000 {
507	device_type = "pci";
508	#interrupt-cells = <1>;
509	#size-cells = <2>;
510	#address-cells = <3>;
511	compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
512	primary;
513	port = <0x1>; /* port number */
514	reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
515	0x0000000c 0x08011000 0x00001000>; /* Registers */
516	dcr-reg = <0x120 0x020>;
517	sdr-base = <0x340>;
518
519	/* Outbound ranges, one memory and one IO,
520	* later cannot be changed
521	*/
522	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
523	0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
524	0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
525
526	/* Inbound 2GB range starting at 0 */
527	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
528
529	/* This drives busses 80 to 0xbf */
530	bus-range = <0x80 0xbf>;
531
532	/* Legacy interrupts (note the weird polarity, the bridge seems
533	* to invert PCIe legacy interrupts).
534	* We are de-swizzling here because the numbers are actually for
535	* port of the root complex virtual P2P bridge. But I want
536	* to avoid putting a node for it in the tree, so the numbers
537	* below are basically de-swizzled numbers.
538	* The real slot is on idsel 0, so the swizzling is 1:1
539	*/
540	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
541	interrupt-map = <
542	0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
543	0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
544	0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
545	0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
546	};
547
548	MSI: ppc4xx-msi@C10000000 {
549	compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
550	reg = < 0xC 0x10000000 0x100>;
551	sdr-base = <0x36C>;
552	msi-data = <0x00000000>;
553	msi-mask = <0x44440000>;
554	interrupt-count = <3>;
555	interrupts = <0 1 2 3>;
556	interrupt-parent = <&UIC3>;
557	#interrupt-cells = <1>;
558	#address-cells = <0>;
559	#size-cells = <0>;
560	interrupt-map = <0 &UIC3 0x18 1
561	1 &UIC3 0x19 1
562	2 &UIC3 0x1A 1
563	3 &UIC3 0x1B 1>;
564	};
565	};
566	};