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Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
1d93f0f0 24#include "qemu-barrier.h"
7d13299d 25
fbf9eeb3
FB		 26#if !defined(CONFIG_SOFTMMU)
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
84778508 37#ifdef __linux__
fbf9eeb3
FB		 38#include <sys/ucontext.h>
39#endif
84778508 40#endif
fbf9eeb3 41
dfe5fff3 42#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 43// Work around ugly bugs in glibc that mangle global register contents
44#undef env
45#define env cpu_single_env
46#endif
47
36bdbe54
FB		 48int tb_invalidated_flag;
49
f0667e66 50//#define CONFIG_DEBUG_EXEC
9de5e440 51//#define DEBUG_SIGNAL
7d13299d 52
6a4955a8
AL		 53int qemu_cpu_has_work(CPUState *env)
54{
55 return cpu_has_work(env);
56}
57
e4533c7a
FB		 58void cpu_loop_exit(void)
59{
1c3569fe 60 env->current_tb = NULL;
e4533c7a
FB		 61 longjmp(env->jmp_env, 1);
62}
bfed01fc 63
fbf9eeb3
FB		 64/* exit the current TB from a signal handler. The host registers are
65 restored in a state compatible with the CPU emulator
66 */
5fafdf24 67void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 68{
69#if !defined(CONFIG_SOFTMMU)
84778508 70#ifdef __linux__
fbf9eeb3 71 struct ucontext *uc = puc;
84778508
BS		 72#elif defined(__OpenBSD__)
73 struct sigcontext *uc = puc;
74#endif
fbf9eeb3
FB		 75#endif
76
77 env = env1;
78
79 /* XXX: restore cpu registers saved in host registers */
80
81#if !defined(CONFIG_SOFTMMU)
82 if (puc) {
83 /* XXX: use siglongjmp ? */
84778508 84#ifdef __linux__
60e99246
AJ		 85#ifdef __ia64
86 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
87#else
fbf9eeb3 88 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
60e99246 89#endif
84778508
BS		 90#elif defined(__OpenBSD__)
91 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
92#endif
fbf9eeb3
FB		 93 }
94#endif
9a3ea654 95 env->exception_index = -1;
fbf9eeb3
FB		 96 longjmp(env->jmp_env, 1);
97}
98
2e70f6ef
PB		 99/* Execute the code without caching the generated code. An interpreter
100 could be used if available. */
101static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
102{
103 unsigned long next_tb;
104 TranslationBlock *tb;
105
106 /* Should never happen.
107 We only end up here when an existing TB is too long. */
108 if (max_cycles > CF_COUNT_MASK)
109 max_cycles = CF_COUNT_MASK;
110
111 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
112 max_cycles);
113 env->current_tb = tb;
114 /* execute the generated code */
115 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
1c3569fe 116 env->current_tb = NULL;
2e70f6ef
PB		 117
118 if ((next_tb & 3) == 2) {
119 /* Restore PC. This may happen if async event occurs before
120 the TB starts executing. */
622ed360 121 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 122 }
123 tb_phys_invalidate(tb, -1);
124 tb_free(tb);
125}
126
8a40a180
FB		 127static TranslationBlock *tb_find_slow(target_ulong pc,
128 target_ulong cs_base,
c068688b 129 uint64_t flags)
8a40a180
FB		 130{
131 TranslationBlock *tb, **ptb1;
8a40a180 132 unsigned int h;
41c1b1c9
PB		 133 tb_page_addr_t phys_pc, phys_page1, phys_page2;
134 target_ulong virt_page2;
3b46e624 135
8a40a180 136 tb_invalidated_flag = 0;
3b46e624 137
8a40a180 138 /* find translated block using physical mappings */
41c1b1c9 139 phys_pc = get_page_addr_code(env, pc);
8a40a180
FB		 140 phys_page1 = phys_pc & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 h = tb_phys_hash_func(phys_pc);
143 ptb1 = &tb_phys_hash[h];
144 for(;;) {
145 tb = *ptb1;
146 if (!tb)
147 goto not_found;
5fafdf24 148 if (tb->pc == pc &&
8a40a180 149 tb->page_addr[0] == phys_page1 &&
5fafdf24 150 tb->cs_base == cs_base &&
8a40a180
FB		 151 tb->flags == flags) {
152 /* check next page if needed */
153 if (tb->page_addr[1] != -1) {
5fafdf24 154 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 155 TARGET_PAGE_SIZE;
41c1b1c9 156 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 157 if (tb->page_addr[1] == phys_page2)
158 goto found;
159 } else {
160 goto found;
161 }
162 }
163 ptb1 = &tb->phys_hash_next;
164 }
165 not_found:
2e70f6ef
PB		 166 /* if no translated code available, then translate it now */
167 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 168
8a40a180 169 found:
2c90fe2b
KB		 170 /* Move the last found TB to the head of the list */
171 if (likely(*ptb1)) {
172 *ptb1 = tb->phys_hash_next;
173 tb->phys_hash_next = tb_phys_hash[h];
174 tb_phys_hash[h] = tb;
175 }
8a40a180
FB		 176 /* we add the TB in the virtual pc hash table */
177 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 178 return tb;
179}
180
181static inline TranslationBlock *tb_find_fast(void)
182{
183 TranslationBlock *tb;
184 target_ulong cs_base, pc;
6b917547 185 int flags;
8a40a180
FB		 186
187 /* we record a subset of the CPU state. It will
188 always be the same before a given translated block
189 is executed. */
6b917547 190 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 191 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 192 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
193 tb->flags != flags)) {
8a40a180
FB		 194 tb = tb_find_slow(pc, cs_base, flags);
195 }
196 return tb;
197}
198
1009d2ed
JK		 199static CPUDebugExcpHandler *debug_excp_handler;
200
201CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
202{
203 CPUDebugExcpHandler *old_handler = debug_excp_handler;
204
205 debug_excp_handler = handler;
206 return old_handler;
207}
208
209static void cpu_handle_debug_exception(CPUState *env)
210{
211 CPUWatchpoint *wp;
212
213 if (!env->watchpoint_hit) {
214 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
215 wp->flags &= ~BP_WATCHPOINT_HIT;
216 }
217 }
218 if (debug_excp_handler) {
219 debug_excp_handler(env);
220 }
221}
222
7d13299d
FB		 223/* main execution loop */
224
1a28cac3
MT		 225volatile sig_atomic_t exit_request;
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
1d9000e8 229 volatile host_reg_t saved_env_reg;
8a40a180 230 int ret, interrupt_request;
8a40a180 231 TranslationBlock *tb;
c27004ec 232 uint8_t *tc_ptr;
d5975363 233 unsigned long next_tb;
8c6939c0 234
eda48c34
PB		 235 if (env1->halted) {
236 if (!cpu_has_work(env1)) {
237 return EXCP_HALTED;
238 }
239
240 env1->halted = 0;
241 }
5a1e3cfc 242
5fafdf24 243 cpu_single_env = env1;
6a00d601 244
24ebf5f3
PB		 245 /* the access to env below is actually saving the global register's
246 value, so that files not including target-xyz/exec.h are free to
247 use it. */
248 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
249 saved_env_reg = (host_reg_t) env;
1d93f0f0 250 barrier();
c27004ec 251 env = env1;
e4533c7a 252
c629a4bc 253 if (unlikely(exit_request)) {
1a28cac3 254 env->exit_request = 1;
1a28cac3
MT		 255 }
256
ecb644f4 257#if defined(TARGET_I386)
6792a57b
JK		 258 /* put eflags in CPU temporary format */
259 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
260 DF = 1 - (2 * ((env->eflags >> 10) & 1));
261 CC_OP = CC_OP_EFLAGS;
262 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 263#elif defined(TARGET_SPARC)
e6e5906b
PB		 264#elif defined(TARGET_M68K)
265 env->cc_op = CC_OP_FLAGS;
266 env->cc_dest = env->sr & 0xf;
267 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 268#elif defined(TARGET_ALPHA)
269#elif defined(TARGET_ARM)
d2fbca94 270#elif defined(TARGET_UNICORE32)
ecb644f4 271#elif defined(TARGET_PPC)
81ea0e13 272#elif defined(TARGET_LM32)
b779e29e 273#elif defined(TARGET_MICROBLAZE)
6af0bf9c 274#elif defined(TARGET_MIPS)
fdf9b3e8 275#elif defined(TARGET_SH4)
f1ccf904 276#elif defined(TARGET_CRIS)
10ec5117 277#elif defined(TARGET_S390X)
fdf9b3e8 278 /* XXXXX */
e4533c7a
FB		 279#else
280#error unsupported target CPU
281#endif
3fb2ded1 282 env->exception_index = -1;
9d27abd9 283
7d13299d 284 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 285 for(;;) {
286 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 287#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2 288#undef env
6792a57b 289 env = cpu_single_env;
9ddff3d2
BS		 290#define env cpu_single_env
291#endif
3fb2ded1
FB		 292 /* if an exception is pending, we execute it here */
293 if (env->exception_index >= 0) {
294 if (env->exception_index >= EXCP_INTERRUPT) {
295 /* exit request from the cpu execution loop */
296 ret = env->exception_index;
1009d2ed
JK		 297 if (ret == EXCP_DEBUG) {
298 cpu_handle_debug_exception(env);
299 }
3fb2ded1 300 break;
72d239ed
AJ		 301 } else {
302#if defined(CONFIG_USER_ONLY)
3fb2ded1 303 /* if user mode only, we simulate a fake exception
9f083493 304 which will be handled outside the cpu execution
3fb2ded1 305 loop */
83479e77 306#if defined(TARGET_I386)
5fafdf24
TS		 307 do_interrupt_user(env->exception_index,
308 env->exception_is_int,
309 env->error_code,
3fb2ded1 310 env->exception_next_eip);
eba01623
FB		 311 /* successfully delivered */
312 env->old_exception = -1;
83479e77 313#endif
3fb2ded1
FB		 314 ret = env->exception_index;
315 break;
72d239ed 316#else
83479e77 317#if defined(TARGET_I386)
3fb2ded1
FB		 318 /* simulate a real cpu exception. On i386, it can
319 trigger new exceptions, but we do not handle
320 double or triple faults yet. */
5fafdf24
TS		 321 do_interrupt(env->exception_index,
322 env->exception_is_int,
323 env->error_code,
d05e66d2 324 env->exception_next_eip, 0);
678dde13
TS		 325 /* successfully delivered */
326 env->old_exception = -1;
ce09776b
FB		 327#elif defined(TARGET_PPC)
328 do_interrupt(env);
81ea0e13
MW		 329#elif defined(TARGET_LM32)
330 do_interrupt(env);
b779e29e
EI		 331#elif defined(TARGET_MICROBLAZE)
332 do_interrupt(env);
6af0bf9c
FB		 333#elif defined(TARGET_MIPS)
334 do_interrupt(env);
e95c8d51 335#elif defined(TARGET_SPARC)
f2bc7e7f 336 do_interrupt(env);
b5ff1b31
FB		 337#elif defined(TARGET_ARM)
338 do_interrupt(env);
d2fbca94
GX		 339#elif defined(TARGET_UNICORE32)
340 do_interrupt(env);
fdf9b3e8
FB		 341#elif defined(TARGET_SH4)
342 do_interrupt(env);
eddf68a6
JM		 343#elif defined(TARGET_ALPHA)
344 do_interrupt(env);
f1ccf904
TS		 345#elif defined(TARGET_CRIS)
346 do_interrupt(env);
0633879f
PB		 347#elif defined(TARGET_M68K)
348 do_interrupt(0);
3110e292
AG		 349#elif defined(TARGET_S390X)
350 do_interrupt(env);
72d239ed 351#endif
301d2908 352 env->exception_index = -1;
83479e77 353#endif
3fb2ded1 354 }
5fafdf24 355 }
9df217a3 356
b5fc09ae 357 next_tb = 0; /* force lookup of first TB */
3fb2ded1 358 for(;;) {
68a79315 359 interrupt_request = env->interrupt_request;
e1638bd8 360 if (unlikely(interrupt_request)) {
361 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
362 /* Mask out external interrupts for this step. */
3125f763 363 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 364 }
6658ffb8
PB		 365 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
366 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
367 env->exception_index = EXCP_DEBUG;
368 cpu_loop_exit();
369 }
a90b7318 370#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 371 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
d2fbca94 372 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
a90b7318
AZ		 373 if (interrupt_request & CPU_INTERRUPT_HALT) {
374 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
375 env->halted = 1;
376 env->exception_index = EXCP_HLT;
377 cpu_loop_exit();
378 }
379#endif
68a79315 380#if defined(TARGET_I386)
b09ea7d5
GN		 381 if (interrupt_request & CPU_INTERRUPT_INIT) {
382 svm_check_intercept(SVM_EXIT_INIT);
383 do_cpu_init(env);
384 env->exception_index = EXCP_HALTED;
385 cpu_loop_exit();
386 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
387 do_cpu_sipi(env);
388 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 389 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
390 !(env->hflags & HF_SMM_MASK)) {
391 svm_check_intercept(SVM_EXIT_SMI);
392 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
393 do_smm_enter();
394 next_tb = 0;
395 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
396 !(env->hflags2 & HF2_NMI_MASK)) {
397 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
398 env->hflags2 |= HF2_NMI_MASK;
399 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
400 next_tb = 0;
79c4f6b0
HY		 401 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
402 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
403 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
404 next_tb = 0;
db620f46
FB		 405 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
406 (((env->hflags2 & HF2_VINTR_MASK) &&
407 (env->hflags2 & HF2_HIF_MASK)) ||
408 (!(env->hflags2 & HF2_VINTR_MASK) &&
409 (env->eflags & IF_MASK &&
410 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
411 int intno;
412 svm_check_intercept(SVM_EXIT_INTR);
413 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
414 intno = cpu_get_pic_interrupt(env);
93fcfe39 415 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 416#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 417#undef env
418 env = cpu_single_env;
419#define env cpu_single_env
420#endif
db620f46
FB		 421 do_interrupt(intno, 0, 0, 0, 1);
422 /* ensure that no TB jump will be modified as
423 the program flow was changed */
424 next_tb = 0;
0573fbfc 425#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 426 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
427 (env->eflags & IF_MASK) &&
428 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
429 int intno;
430 /* FIXME: this should respect TPR */
431 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 432 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 433 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 434 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 435 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 436 next_tb = 0;
907a5b26 437#endif
db620f46 438 }
68a79315 439 }
ce09776b 440#elif defined(TARGET_PPC)
9fddaa0c
FB		 441#if 0
442 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 443 cpu_reset(env);
9fddaa0c
FB		 444 }
445#endif
47103572 446 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 447 ppc_hw_interrupt(env);
448 if (env->pending_interrupts == 0)
449 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 450 next_tb = 0;
ce09776b 451 }
81ea0e13
MW		 452#elif defined(TARGET_LM32)
453 if ((interrupt_request & CPU_INTERRUPT_HARD)
454 && (env->ie & IE_IE)) {
455 env->exception_index = EXCP_IRQ;
456 do_interrupt(env);
457 next_tb = 0;
458 }
b779e29e
EI		 459#elif defined(TARGET_MICROBLAZE)
460 if ((interrupt_request & CPU_INTERRUPT_HARD)
461 && (env->sregs[SR_MSR] & MSR_IE)
462 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
463 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
464 env->exception_index = EXCP_IRQ;
465 do_interrupt(env);
466 next_tb = 0;
467 }
6af0bf9c
FB		 468#elif defined(TARGET_MIPS)
469 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 470 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 471 /* Raise it */
472 env->exception_index = EXCP_EXT_INTERRUPT;
473 env->error_code = 0;
474 do_interrupt(env);
b5fc09ae 475 next_tb = 0;
6af0bf9c 476 }
e95c8d51 477#elif defined(TARGET_SPARC)
d532b26c
IK		 478 if (interrupt_request & CPU_INTERRUPT_HARD) {
479 if (cpu_interrupts_enabled(env) &&
480 env->interrupt_index > 0) {
481 int pil = env->interrupt_index & 0xf;
482 int type = env->interrupt_index & 0xf0;
483
484 if (((type == TT_EXTINT) &&
485 cpu_pil_allowed(env, pil)) ||
486 type != TT_EXTINT) {
487 env->exception_index = env->interrupt_index;
488 do_interrupt(env);
489 next_tb = 0;
490 }
491 }
a90b7318 492 }
b5ff1b31
FB		 493#elif defined(TARGET_ARM)
494 if (interrupt_request & CPU_INTERRUPT_FIQ
495 && !(env->uncached_cpsr & CPSR_F)) {
496 env->exception_index = EXCP_FIQ;
497 do_interrupt(env);
b5fc09ae 498 next_tb = 0;
b5ff1b31 499 }
9ee6e8bb
PB		 500 /* ARMv7-M interrupt return works by loading a magic value
501 into the PC. On real hardware the load causes the
502 return to occur. The qemu implementation performs the
503 jump normally, then does the exception return when the
504 CPU tries to execute code at the magic address.
505 This will cause the magic PC value to be pushed to
a1c7273b 506 the stack if an interrupt occurred at the wrong time.
9ee6e8bb
PB		 507 We avoid this by disabling interrupts when
508 pc contains a magic address. */
b5ff1b31 509 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 510 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
511 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 512 env->exception_index = EXCP_IRQ;
513 do_interrupt(env);
b5fc09ae 514 next_tb = 0;
b5ff1b31 515 }
d2fbca94
GX		 516#elif defined(TARGET_UNICORE32)
517 if (interrupt_request & CPU_INTERRUPT_HARD
518 && !(env->uncached_asr & ASR_I)) {
519 do_interrupt(env);
520 next_tb = 0;
521 }
fdf9b3e8 522#elif defined(TARGET_SH4)
e96e2044
TS		 523 if (interrupt_request & CPU_INTERRUPT_HARD) {
524 do_interrupt(env);
b5fc09ae 525 next_tb = 0;
e96e2044 526 }
eddf68a6
JM		 527#elif defined(TARGET_ALPHA)
528 if (interrupt_request & CPU_INTERRUPT_HARD) {
529 do_interrupt(env);
b5fc09ae 530 next_tb = 0;
eddf68a6 531 }
f1ccf904 532#elif defined(TARGET_CRIS)
1b1a38b0 533 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 534 && (env->pregs[PR_CCS] & I_FLAG)
535 && !env->locked_irq) {
1b1a38b0
EI		 536 env->exception_index = EXCP_IRQ;
537 do_interrupt(env);
538 next_tb = 0;
539 }
540 if (interrupt_request & CPU_INTERRUPT_NMI
541 && (env->pregs[PR_CCS] & M_FLAG)) {
542 env->exception_index = EXCP_NMI;
f1ccf904 543 do_interrupt(env);
b5fc09ae 544 next_tb = 0;
f1ccf904 545 }
0633879f
PB		 546#elif defined(TARGET_M68K)
547 if (interrupt_request & CPU_INTERRUPT_HARD
548 && ((env->sr & SR_I) >> SR_I_SHIFT)
549 < env->pending_level) {
550 /* Real hardware gets the interrupt vector via an
551 IACK cycle at this point. Current emulated
552 hardware doesn't rely on this, so we
553 provide/save the vector when the interrupt is
554 first signalled. */
555 env->exception_index = env->pending_vector;
556 do_interrupt(1);
b5fc09ae 557 next_tb = 0;
0633879f 558 }
3110e292
AG		 559#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
560 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
561 (env->psw.mask & PSW_MASK_EXT)) {
562 do_interrupt(env);
563 next_tb = 0;
564 }
68a79315 565#endif
ff2712ba 566 /* Don't use the cached interrupt_request value,
9d05095e 567 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 568 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 569 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
570 /* ensure that no TB jump will be modified as
571 the program flow was changed */
b5fc09ae 572 next_tb = 0;
bf3e8bf1 573 }
be214e6c
AJ		 574 }
575 if (unlikely(env->exit_request)) {
576 env->exit_request = 0;
577 env->exception_index = EXCP_INTERRUPT;
578 cpu_loop_exit();
3fb2ded1 579 }
a73b1fd9 580#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 581 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 582 /* restore flags in standard format */
ecb644f4 583#if defined(TARGET_I386)
a7812ae4 584 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 585 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 586 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 587#elif defined(TARGET_M68K)
588 cpu_m68k_flush_flags(env, env->cc_op);
589 env->cc_op = CC_OP_FLAGS;
590 env->sr = (env->sr & 0xffe0)
591 | env->cc_dest | (env->cc_x << 4);
93fcfe39 592 log_cpu_state(env, 0);
e4533c7a 593#else
a73b1fd9 594 log_cpu_state(env, 0);
e4533c7a 595#endif
3fb2ded1 596 }
a73b1fd9 597#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 598 spin_lock(&tb_lock);
8a40a180 599 tb = tb_find_fast();
d5975363
PB		 600 /* Note: we do it here to avoid a gcc bug on Mac OS X when
601 doing it in tb_find_slow */
602 if (tb_invalidated_flag) {
603 /* as some TB could have been invalidated because
604 of memory exceptions while generating the code, we
605 must recompute the hash index here */
606 next_tb = 0;
2e70f6ef 607 tb_invalidated_flag = 0;
d5975363 608 }
f0667e66 609#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 610 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
611 (long)tb->tc_ptr, tb->pc,
612 lookup_symbol(tb->pc));
9d27abd9 613#endif
8a40a180
FB		 614 /* see if we can patch the calling TB. When the TB
615 spans two pages, we cannot safely do a direct
616 jump. */
040f2fb2 617 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 618 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 619 }
d5975363 620 spin_unlock(&tb_lock);
55e8b85e 621
622 /* cpu_interrupt might be called while translating the
623 TB, but before it is linked into a potentially
624 infinite loop and becomes env->current_tb. Avoid
625 starting execution if there is a pending interrupt. */
b0052d15
JK		 626 env->current_tb = tb;
627 barrier();
628 if (likely(!env->exit_request)) {
2e70f6ef 629 tc_ptr = tb->tc_ptr;
3fb2ded1 630 /* execute the generated code */
dfe5fff3 631#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 632#undef env
2e70f6ef 633 env = cpu_single_env;
572a9d4a
BS		 634#define env cpu_single_env
635#endif
2e70f6ef 636 next_tb = tcg_qemu_tb_exec(tc_ptr);
2e70f6ef 637 if ((next_tb & 3) == 2) {
bf20dc07 638 /* Instruction counter expired. */
2e70f6ef
PB		 639 int insns_left;
640 tb = (TranslationBlock *)(long)(next_tb & ~3);
641 /* Restore PC. */
622ed360 642 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 643 insns_left = env->icount_decr.u32;
644 if (env->icount_extra && insns_left >= 0) {
645 /* Refill decrementer and continue execution. */
646 env->icount_extra += insns_left;
647 if (env->icount_extra > 0xffff) {
648 insns_left = 0xffff;
649 } else {
650 insns_left = env->icount_extra;
651 }
652 env->icount_extra -= insns_left;
653 env->icount_decr.u16.low = insns_left;
654 } else {
655 if (insns_left > 0) {
656 /* Execute remaining instructions. */
657 cpu_exec_nocache(insns_left, tb);
658 }
659 env->exception_index = EXCP_INTERRUPT;
660 next_tb = 0;
661 cpu_loop_exit();
662 }
663 }
664 }
b0052d15 665 env->current_tb = NULL;
4cbf74b6
FB		 666 /* reset soft MMU for next block (it can currently
667 only be set by a memory fault) */
50a518e3 668 } /* for(;;) */
7d13299d 669 }
3fb2ded1
FB		 670 } /* for(;;) */
671
7d13299d 672
e4533c7a 673#if defined(TARGET_I386)
9de5e440 674 /* restore flags in standard format */
a7812ae4 675 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 676#elif defined(TARGET_ARM)
b7bcbe95 677 /* XXX: Save/restore host fpu exception state?. */
d2fbca94 678#elif defined(TARGET_UNICORE32)
93ac68bc 679#elif defined(TARGET_SPARC)
67867308 680#elif defined(TARGET_PPC)
81ea0e13 681#elif defined(TARGET_LM32)
e6e5906b
PB		 682#elif defined(TARGET_M68K)
683 cpu_m68k_flush_flags(env, env->cc_op);
684 env->cc_op = CC_OP_FLAGS;
685 env->sr = (env->sr & 0xffe0)
686 | env->cc_dest | (env->cc_x << 4);
b779e29e 687#elif defined(TARGET_MICROBLAZE)
6af0bf9c 688#elif defined(TARGET_MIPS)
fdf9b3e8 689#elif defined(TARGET_SH4)
eddf68a6 690#elif defined(TARGET_ALPHA)
f1ccf904 691#elif defined(TARGET_CRIS)
10ec5117 692#elif defined(TARGET_S390X)
fdf9b3e8 693 /* XXXXX */
e4533c7a
FB		 694#else
695#error unsupported target CPU
696#endif
1057eaa7
PB		 697
698 /* restore global registers */
1d93f0f0 699 barrier();
24ebf5f3 700 env = (void *) saved_env_reg;
1057eaa7 701
6a00d601 702 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 703 cpu_single_env = NULL;
7d13299d
FB		 704 return ret;
705}
6dbad63e 706
1a18c71b 707#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 708
6dbad63e
FB		 709void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
710{
711 CPUX86State *saved_env;
712
713 saved_env = env;
714 env = s;
a412ac57 715 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 716 selector &= 0xffff;
5fafdf24 717 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 718 (selector << 4), 0xffff, 0);
a513fe19 719 } else {
5d97559d 720 helper_load_seg(seg_reg, selector);
a513fe19 721 }
6dbad63e
FB		 722 env = saved_env;
723}
9de5e440 724
6f12a2a6 725void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 726{
727 CPUX86State *saved_env;
728
729 saved_env = env;
730 env = s;
3b46e624 731
6f12a2a6 732 helper_fsave(ptr, data32);
d0a1ffc9
FB		 733
734 env = saved_env;
735}
736
6f12a2a6 737void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 738{
739 CPUX86State *saved_env;
740
741 saved_env = env;
742 env = s;
3b46e624 743
6f12a2a6 744 helper_frstor(ptr, data32);
d0a1ffc9
FB		 745
746 env = saved_env;
747}
748
e4533c7a
FB		 749#endif /* TARGET_I386 */
750
67b915a5
FB		 751#if !defined(CONFIG_SOFTMMU)
752
3fb2ded1 753#if defined(TARGET_I386)
0b5c1ce8
NF		 754#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
755#else
756#define EXCEPTION_ACTION cpu_loop_exit()
757#endif
3fb2ded1 758
b56dad1c 759/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 760 the effective address of the memory exception. 'is_write' is 1 if a
761 write caused the exception and otherwise 0'. 'old_set' is the
762 signal set which should be restored */
2b413144 763static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 764 int is_write, sigset_t *old_set,
bf3e8bf1 765 void *puc)
9de5e440 766{
a513fe19
FB		 767 TranslationBlock *tb;
768 int ret;
68a79315 769
83479e77
FB		 770 if (cpu_single_env)
771 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 772#if defined(DEBUG_SIGNAL)
5fafdf24 773 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 774 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 775#endif
25eb4484 776 /* XXX: locking issue */
53a5960a 777 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 778 return 1;
779 }
fbf9eeb3 780
3fb2ded1 781 /* see if it is an MMU fault */
0b5c1ce8 782 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 783 if (ret < 0)
784 return 0; /* not an MMU fault */
785 if (ret == 0)
786 return 1; /* the MMU fault was handled without causing real CPU fault */
787 /* now we have a real cpu fault */
788 tb = tb_find_pc(pc);
789 if (tb) {
790 /* the PC is inside the translated code. It means that we have
791 a virtual CPU fault */
618ba8e6 792 cpu_restore_state(tb, env, pc);
68016c62 793 }
68016c62 794
68016c62
FB		 795 /* we restore the process signal mask as the sigreturn should
796 do it (XXX: use sigsetjmp) */
797 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 798 EXCEPTION_ACTION;
e6e5906b 799
e6e5906b 800 /* never comes here */
67867308
FB		 801 return 1;
802}
6af0bf9c 803
2b413144
FB		 804#if defined(__i386__)
805
d8ecc0b9
FB		 806#if defined(__APPLE__)
807# include <sys/ucontext.h>
808
809# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
810# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
811# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 812# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 813#elif defined (__NetBSD__)
814# include <ucontext.h>
815
816# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
817# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
818# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
819# define MASK_sig(context) ((context)->uc_sigmask)
820#elif defined (__FreeBSD__) || defined(__DragonFly__)
821# include <ucontext.h>
822
823# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
824# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
825# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
826# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 827#elif defined(__OpenBSD__)
828# define EIP_sig(context) ((context)->sc_eip)
829# define TRAP_sig(context) ((context)->sc_trapno)
830# define ERROR_sig(context) ((context)->sc_err)
831# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 832#else
833# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
834# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
835# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 836# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 837#endif
838
5fafdf24 839int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 840 void *puc)
9de5e440 841{
5a7b542b 842 siginfo_t *info = pinfo;
78cfb07f
JL		 843#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
844 ucontext_t *uc = puc;
845#elif defined(__OpenBSD__)
d39bb24a
BS		 846 struct sigcontext *uc = puc;
847#else
9de5e440 848 struct ucontext *uc = puc;
d39bb24a 849#endif
9de5e440 850 unsigned long pc;
bf3e8bf1 851 int trapno;
97eb5b14 852
d691f669
FB		 853#ifndef REG_EIP
854/* for glibc 2.1 */
fd6ce8f6
FB		 855#define REG_EIP EIP
856#define REG_ERR ERR
857#define REG_TRAPNO TRAPNO
d691f669 858#endif
d8ecc0b9
FB		 859 pc = EIP_sig(uc);
860 trapno = TRAP_sig(uc);
ec6338ba
FB		 861 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
862 trapno == 0xe ?
863 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 864 &MASK_sig(uc), puc);
2b413144
FB		 865}
866
bc51c5c9
FB		 867#elif defined(__x86_64__)
868
b3efe5c8 869#ifdef __NetBSD__
d397abbd
BS		 870#define PC_sig(context) _UC_MACHINE_PC(context)
871#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
872#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
873#define MASK_sig(context) ((context)->uc_sigmask)
874#elif defined(__OpenBSD__)
875#define PC_sig(context) ((context)->sc_rip)
876#define TRAP_sig(context) ((context)->sc_trapno)
877#define ERROR_sig(context) ((context)->sc_err)
878#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 879#elif defined (__FreeBSD__) || defined(__DragonFly__)
880#include <ucontext.h>
881
882#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
883#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
884#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
885#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 886#else
d397abbd
BS		 887#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
888#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
889#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
890#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 891#endif
892
5a7b542b 893int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 894 void *puc)
895{
5a7b542b 896 siginfo_t *info = pinfo;
bc51c5c9 897 unsigned long pc;
78cfb07f 898#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 899 ucontext_t *uc = puc;
d397abbd
BS		 900#elif defined(__OpenBSD__)
901 struct sigcontext *uc = puc;
b3efe5c8
BS		 902#else
903 struct ucontext *uc = puc;
904#endif
bc51c5c9 905
d397abbd 906 pc = PC_sig(uc);
5fafdf24 907 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 908 TRAP_sig(uc) == 0xe ?
909 (ERROR_sig(uc) >> 1) & 1 : 0,
910 &MASK_sig(uc), puc);
bc51c5c9
FB		 911}
912
e58ffeb3 913#elif defined(_ARCH_PPC)
2b413144 914
83fb7adf
FB		 915/***********************************************************************
916 * signal context platform-specific definitions
917 * From Wine
918 */
919#ifdef linux
920/* All Registers access - only for local access */
921# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
922/* Gpr Registers access */
923# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
924# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
925# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
926# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
927# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
928# define LR_sig(context) REG_sig(link, context) /* Link register */
929# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
930/* Float Registers access */
931# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
932# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
933/* Exception Registers access */
934# define DAR_sig(context) REG_sig(dar, context)
935# define DSISR_sig(context) REG_sig(dsisr, context)
936# define TRAP_sig(context) REG_sig(trap, context)
937#endif /* linux */
938
58d9b1e0
JL		 939#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
940#include <ucontext.h>
941# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
942# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
943# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
944# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
945# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
946# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
947/* Exception Registers access */
948# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
949# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
950# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
951#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
952
83fb7adf
FB		 953#ifdef __APPLE__
954# include <sys/ucontext.h>
955typedef struct ucontext SIGCONTEXT;
956/* All Registers access - only for local access */
957# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
958# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
959# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
960# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
961/* Gpr Registers access */
962# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
963# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
964# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
965# define CTR_sig(context) REG_sig(ctr, context)
966# define XER_sig(context) REG_sig(xer, context) /* Link register */
967# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
968# define CR_sig(context) REG_sig(cr, context) /* Condition register */
969/* Float Registers access */
970# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
971# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
972/* Exception Registers access */
973# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
974# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
975# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
976#endif /* __APPLE__ */
977
5fafdf24 978int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 979 void *puc)
2b413144 980{
5a7b542b 981 siginfo_t *info = pinfo;
58d9b1e0
JL		 982#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
983 ucontext_t *uc = puc;
984#else
25eb4484 985 struct ucontext *uc = puc;
58d9b1e0 986#endif
25eb4484 987 unsigned long pc;
25eb4484
FB		 988 int is_write;
989
83fb7adf 990 pc = IAR_sig(uc);
25eb4484
FB		 991 is_write = 0;
992#if 0
993 /* ppc 4xx case */
83fb7adf 994 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 995 is_write = 1;
996#else
83fb7adf 997 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 998 is_write = 1;
999#endif
5fafdf24 1000 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1001 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1002}
1003
2f87c607
FB		 1004#elif defined(__alpha__)
1005
5fafdf24 1006int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1007 void *puc)
1008{
5a7b542b 1009 siginfo_t *info = pinfo;
2f87c607
FB		 1010 struct ucontext *uc = puc;
1011 uint32_t *pc = uc->uc_mcontext.sc_pc;
1012 uint32_t insn = *pc;
1013 int is_write = 0;
1014
8c6939c0 1015 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1016 switch (insn >> 26) {
1017 case 0x0d: // stw
1018 case 0x0e: // stb
1019 case 0x0f: // stq_u
1020 case 0x24: // stf
1021 case 0x25: // stg
1022 case 0x26: // sts
1023 case 0x27: // stt
1024 case 0x2c: // stl
1025 case 0x2d: // stq
1026 case 0x2e: // stl_c
1027 case 0x2f: // stq_c
1028 is_write = 1;
1029 }
1030
5fafdf24 1031 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1032 is_write, &uc->uc_sigmask, puc);
2f87c607 1033}
8c6939c0
FB		 1034#elif defined(__sparc__)
1035
5fafdf24 1036int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1037 void *puc)
8c6939c0 1038{
5a7b542b 1039 siginfo_t *info = pinfo;
8c6939c0
FB		 1040 int is_write;
1041 uint32_t insn;
dfe5fff3 1042#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1043 uint32_t *regs = (uint32_t *)(info + 1);
1044 void *sigmask = (regs + 20);
8c6939c0 1045 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1046 unsigned long pc = regs[1];
1047#else
84778508 1048#ifdef __linux__
c9e1e2b0
BS		 1049 struct sigcontext *sc = puc;
1050 unsigned long pc = sc->sigc_regs.tpc;
1051 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1052#elif defined(__OpenBSD__)
1053 struct sigcontext *uc = puc;
1054 unsigned long pc = uc->sc_pc;
1055 void *sigmask = (void *)(long)uc->sc_mask;
1056#endif
c9e1e2b0
BS		 1057#endif
1058
8c6939c0
FB		 1059 /* XXX: need kernel patch to get write flag faster */
1060 is_write = 0;
1061 insn = *(uint32_t *)pc;
1062 if ((insn >> 30) == 3) {
1063 switch((insn >> 19) & 0x3f) {
1064 case 0x05: // stb
d877fa5a 1065 case 0x15: // stba
8c6939c0 1066 case 0x06: // sth
d877fa5a 1067 case 0x16: // stha
8c6939c0 1068 case 0x04: // st
d877fa5a 1069 case 0x14: // sta
8c6939c0 1070 case 0x07: // std
d877fa5a
BS		 1071 case 0x17: // stda
1072 case 0x0e: // stx
1073 case 0x1e: // stxa
8c6939c0 1074 case 0x24: // stf
d877fa5a 1075 case 0x34: // stfa
8c6939c0 1076 case 0x27: // stdf
d877fa5a
BS		 1077 case 0x37: // stdfa
1078 case 0x26: // stqf
1079 case 0x36: // stqfa
8c6939c0 1080 case 0x25: // stfsr
d877fa5a
BS		 1081 case 0x3c: // casa
1082 case 0x3e: // casxa
8c6939c0
FB		 1083 is_write = 1;
1084 break;
1085 }
1086 }
5fafdf24 1087 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1088 is_write, sigmask, NULL);
8c6939c0
FB		 1089}
1090
1091#elif defined(__arm__)
1092
5fafdf24 1093int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1094 void *puc)
8c6939c0 1095{
5a7b542b 1096 siginfo_t *info = pinfo;
8c6939c0
FB		 1097 struct ucontext *uc = puc;
1098 unsigned long pc;
1099 int is_write;
3b46e624 1100
48bbf11b 1101#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1102 pc = uc->uc_mcontext.gregs[R15];
1103#else
4eee57f5 1104 pc = uc->uc_mcontext.arm_pc;
5c49b363 1105#endif
8c6939c0
FB		 1106 /* XXX: compute is_write */
1107 is_write = 0;
5fafdf24 1108 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1109 is_write,
f3a9676a 1110 &uc->uc_sigmask, puc);
8c6939c0
FB		 1111}
1112
38e584a0
FB		 1113#elif defined(__mc68000)
1114
5fafdf24 1115int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1116 void *puc)
1117{
5a7b542b 1118 siginfo_t *info = pinfo;
38e584a0
FB		 1119 struct ucontext *uc = puc;
1120 unsigned long pc;
1121 int is_write;
3b46e624 1122
38e584a0
FB		 1123 pc = uc->uc_mcontext.gregs[16];
1124 /* XXX: compute is_write */
1125 is_write = 0;
5fafdf24 1126 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1127 is_write,
bf3e8bf1 1128 &uc->uc_sigmask, puc);
38e584a0
FB		 1129}
1130
b8076a74
FB		 1131#elif defined(__ia64)
1132
1133#ifndef __ISR_VALID
1134 /* This ought to be in <bits/siginfo.h>... */
1135# define __ISR_VALID 1
b8076a74
FB		 1136#endif
1137
5a7b542b 1138int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1139{
5a7b542b 1140 siginfo_t *info = pinfo;
b8076a74
FB		 1141 struct ucontext *uc = puc;
1142 unsigned long ip;
1143 int is_write = 0;
1144
1145 ip = uc->uc_mcontext.sc_ip;
1146 switch (host_signum) {
1147 case SIGILL:
1148 case SIGFPE:
1149 case SIGSEGV:
1150 case SIGBUS:
1151 case SIGTRAP:
fd4a43e4 1152 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1153 /* ISR.W (write-access) is bit 33: */
1154 is_write = (info->si_isr >> 33) & 1;
1155 break;
1156
1157 default:
1158 break;
1159 }
1160 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1161 is_write,
60e99246 1162 (sigset_t *)&uc->uc_sigmask, puc);
b8076a74
FB		 1163}
1164
90cb9493
FB		 1165#elif defined(__s390__)
1166
5fafdf24 1167int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1168 void *puc)
1169{
5a7b542b 1170 siginfo_t *info = pinfo;
90cb9493
FB		 1171 struct ucontext *uc = puc;
1172 unsigned long pc;
6a1621b9
RH		 1173 uint16_t *pinsn;
1174 int is_write = 0;
3b46e624 1175
90cb9493 1176 pc = uc->uc_mcontext.psw.addr;
6a1621b9
RH		 1177
1178 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1179 of the normal 2 arguments. The 3rd argument contains the "int_code"
1180 from the hardware which does in fact contain the is_write value.
1181 The rt signal handler, as far as I can tell, does not give this value
1182 at all. Not that we could get to it from here even if it were. */
1183 /* ??? This is not even close to complete, since it ignores all
1184 of the read-modify-write instructions. */
1185 pinsn = (uint16_t *)pc;
1186 switch (pinsn[0] >> 8) {
1187 case 0x50: /* ST */
1188 case 0x42: /* STC */
1189 case 0x40: /* STH */
1190 is_write = 1;
1191 break;
1192 case 0xc4: /* RIL format insns */
1193 switch (pinsn[0] & 0xf) {
1194 case 0xf: /* STRL */
1195 case 0xb: /* STGRL */
1196 case 0x7: /* STHRL */
1197 is_write = 1;
1198 }
1199 break;
1200 case 0xe3: /* RXY format insns */
1201 switch (pinsn[2] & 0xff) {
1202 case 0x50: /* STY */
1203 case 0x24: /* STG */
1204 case 0x72: /* STCY */
1205 case 0x70: /* STHY */
1206 case 0x8e: /* STPQ */
1207 case 0x3f: /* STRVH */
1208 case 0x3e: /* STRV */
1209 case 0x2f: /* STRVG */
1210 is_write = 1;
1211 }
1212 break;
1213 }
5fafdf24 1214 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1215 is_write, &uc->uc_sigmask, puc);
1216}
1217
1218#elif defined(__mips__)
1219
5fafdf24 1220int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1221 void *puc)
1222{
9617efe8 1223 siginfo_t *info = pinfo;
c4b89d18
TS		 1224 struct ucontext *uc = puc;
1225 greg_t pc = uc->uc_mcontext.pc;
1226 int is_write;
3b46e624 1227
c4b89d18
TS		 1228 /* XXX: compute is_write */
1229 is_write = 0;
5fafdf24 1230 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1231 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1232}
1233
f54b3f92
AJ		 1234#elif defined(__hppa__)
1235
1236int cpu_signal_handler(int host_signum, void *pinfo,
1237 void *puc)
1238{
1239 struct siginfo *info = pinfo;
1240 struct ucontext *uc = puc;
f57040be
RH		 1241 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1242 uint32_t insn = *(uint32_t *)pc;
1243 int is_write = 0;
1244
1245 /* XXX: need kernel patch to get write flag faster. */
1246 switch (insn >> 26) {
1247 case 0x1a: /* STW */
1248 case 0x19: /* STH */
1249 case 0x18: /* STB */
1250 case 0x1b: /* STWM */
1251 is_write = 1;
1252 break;
1253
1254 case 0x09: /* CSTWX, FSTWX, FSTWS */
1255 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1256 /* Distinguish from coprocessor load ... */
1257 is_write = (insn >> 9) & 1;
1258 break;
1259
1260 case 0x03:
1261 switch ((insn >> 6) & 15) {
1262 case 0xa: /* STWS */
1263 case 0x9: /* STHS */
1264 case 0x8: /* STBS */
1265 case 0xe: /* STWAS */
1266 case 0xc: /* STBYS */
1267 is_write = 1;
1268 }
1269 break;
1270 }
f54b3f92 1271
f54b3f92 1272 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
f57040be 1273 is_write, &uc->uc_sigmask, puc);
f54b3f92
AJ		 1274}
1275
9de5e440 1276#else
2b413144 1277
3fb2ded1 1278#error host CPU specific signal handler needed
2b413144 1279
9de5e440 1280#endif
67b915a5
FB		 1281
1282#endif /* !defined(CONFIG_SOFTMMU) */
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