[qemu.git] / hw / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sh.h"
#include "qemu-char.h"
#include <assert.h>

//#define DEBUG_SERIAL

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    target_phys_addr_t base;
    int freq;
    int feat;
    int flags;
    int rtrg;

    CharDriverState *chr;

    struct intc_source *eri;
    struct intc_source *rxi;
    struct intc_source *txi;
    struct intc_source *tei;
    struct intc_source *bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state * s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

#ifdef DEBUG_SERIAL
    printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
	   (unsigned long) s->base, offs, val);
#endif
    switch(offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
	return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5)))
            s->flags |= SH_SERIAL_FLAG_TEND;
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
            if ((val & (1 << 7)) && !(s->txi->asserted))
                sh_intc_toggle_source(s->txi, 0, 1);
            else if (!(val & (1 << 7)) && s->txi->asserted)
                sh_intc_toggle_source(s->txi, 0, -1);
        }
        if (!(val & (1 << 6)) && s->rxi->asserted) {
	    sh_intc_toggle_source(s->rxi, 0, -1);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (s->chr) {
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
	}
	s->dr = val;
	s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6)))
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            if (!(val & (1 << 5)))
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            if (!(val & (1 << 4)))
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            if (!(val & (1 << 1)))
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            if (!(val & (1 << 0)))
                s->flags &= ~SH_SERIAL_FLAG_DR;

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi && s->rxi->asserted) {
                    sh_intc_toggle_source(s->rxi, 0, -1);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    }
    else {
#if 0
        switch(offs) {
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x1c:
            ret = s->sptr;
            break;
        }
#endif
    }

    fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
    assert(0);
}

static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
{
    sh_serial_state *s = opaque;
    uint32_t ret = ~0;

#if 0
    switch(offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
	break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND)
                ret |= (1 << 6);
            if (s->flags & SH_SERIAL_FLAG_TDE)
                ret |= (1 << 5);
            if (s->flags & SH_SERIAL_FLAG_BRK)
                ret |= (1 << 4);
            if (s->flags & SH_SERIAL_FLAG_RDF)
                ret |= (1 << 1);
            if (s->flags & SH_SERIAL_FLAG_DR)
                ret |= (1 << 0);

            if (s->scr & (1 << 5))
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH)
                    s->rx_tail = 0;
                if (s->rx_cnt < s->rtrg)
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            break;
#if 0
        case 0x18:
            ret = s->fcr;
            break;
#endif
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    }
    else {
#if 0
        switch(offs) {
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
        case 0x1c:
            ret = s->sptr;
            break;
        }
#endif
    }
#ifdef DEBUG_SERIAL
    printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
	   (unsigned long) s->base, offs, ret);
#endif

    if (ret & ~((1 << 16) - 1)) {
        fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
	assert(0);
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_byte(sh_serial_state *s, int ch)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
            s->rx_fifo[s->rx_head++] = ch;
            if (s->rx_head == SH_RX_FIFO_LENGTH)
                s->rx_head = 0;
            s->rx_cnt++;
            if (s->rx_cnt >= s->rtrg) {
                s->flags |= SH_SERIAL_FLAG_RDF;
                if (s->scr & (1 << 6) && s->rxi) {
                    sh_intc_toggle_source(s->rxi, 0, 1);
                }
            }
        }
    } else {
        s->rx_fifo[0] = ch;
    }
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF)
        s->sr |= (1 << 4);
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;
    sh_serial_receive_byte(s, buf[0]);
}

static void sh_serial_event(void *opaque, int event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK)
        sh_serial_receive_break(s);
}

static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
{
    sh_serial_state *s = opaque;
    return sh_serial_ioport_read(s, addr - s->base);
}

static void sh_serial_write (void *opaque,
                             target_phys_addr_t addr, uint32_t value)
{
    sh_serial_state *s = opaque;
    sh_serial_ioport_write(s, addr - s->base, value);
}

static CPUReadMemoryFunc *sh_serial_readfn[] = {
    &sh_serial_read,
    &sh_serial_read,
    &sh_serial_read,
};

static CPUWriteMemoryFunc *sh_serial_writefn[] = {
    &sh_serial_write,
    &sh_serial_write,
    &sh_serial_write,
};

void sh_serial_init (target_phys_addr_t base, int feat,
		     uint32_t freq, CharDriverState *chr,
		     struct intc_source *eri_source,
		     struct intc_source *rxi_source,
		     struct intc_source *txi_source,
		     struct intc_source *tei_source,
		     struct intc_source *bri_source)
{
    sh_serial_state *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(sh_serial_state));
    if (!s)
        return;

    s->base = base;
    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    }
    else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
					 sh_serial_writefn, s);
    cpu_register_physical_memory(base, 0x28, s_io_memory);

    s->chr = chr;

    if (chr)
        qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
			      sh_serial_event, s);

    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
87ecb68b PB	27	#include "hw.h"
	28	#include "sh.h"
	29	#include "qemu-char.h"
2f062c72 TS	30	#include <assert.h>
	31
	32	//#define DEBUG_SERIAL
	33
	34	#define SH_SERIAL_FLAG_TEND (1 << 0)
	35	#define SH_SERIAL_FLAG_TDE (1 << 1)
	36	#define SH_SERIAL_FLAG_RDF (1 << 2)
	37	#define SH_SERIAL_FLAG_BRK (1 << 3)
	38	#define SH_SERIAL_FLAG_DR (1 << 4)
	39
63242a00 AJ	40	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	41
2f062c72 TS	42	typedef struct {
	43	uint8_t smr;
	44	uint8_t brr;
	45	uint8_t scr;
	46	uint8_t dr; /* ftdr / tdr */
	47	uint8_t sr; /* fsr / ssr */
	48	uint16_t fcr;
	49	uint8_t sptr;
	50
63242a00	51	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	52	uint8_t rx_cnt;
63242a00 AJ	53	uint8_t rx_tail;
63242a00 AJ	54	uint8_t rx_head;
2f062c72 TS	55
	56	target_phys_addr_t base;
	57	int freq;
	58	int feat;
	59	int flags;
63242a00	60	int rtrg;
2f062c72 TS	61
2f062c72 TS	62	CharDriverState *chr;
bf5b7423 AJ	63
	64	struct intc_source *eri;
	65	struct intc_source *rxi;
	66	struct intc_source *txi;
	67	struct intc_source *tei;
	68	struct intc_source *bri;
2f062c72 TS	69	} sh_serial_state;
2f062c72 TS	70
63242a00 AJ	71	static void sh_serial_clear_fifo(sh_serial_state * s)
	72	{
	73	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	74	s->rx_cnt = 0;
	75	s->rx_head = 0;
	76	s->rx_tail = 0;
	77	}
	78
2f062c72 TS	79	static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
	80	{
	81	sh_serial_state *s = opaque;
	82	unsigned char ch;
	83
	84	#ifdef DEBUG_SERIAL
	85	printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
	86	(unsigned long) s->base, offs, val);
	87	#endif
	88	switch(offs) {
	89	case 0x00: /* SMR */
	90	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	91	return;
	92	case 0x04: /* BRR */
	93	s->brr = val;
	94	return;
	95	case 0x08: /* SCR */
63242a00	96	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	97	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
2f062c72 TS	98	if (!(val & (1 << 5)))
2f062c72 TS	99	s->flags \|= SH_SERIAL_FLAG_TEND;
bf5b7423 AJ	100	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
	101	if ((val & (1 << 7)) && !(s->txi->asserted))
	102	sh_intc_toggle_source(s->txi, 0, 1);
	103	else if (!(val & (1 << 7)) && s->txi->asserted)
	104	sh_intc_toggle_source(s->txi, 0, -1);
	105	}
63242a00 AJ	106	if (!(val & (1 << 6)) && s->rxi->asserted) {
	107	sh_intc_toggle_source(s->rxi, 0, -1);
	108	}
2f062c72 TS	109	return;
	110	case 0x0c: /* FTDR / TDR */
	111	if (s->chr) {
	112	ch = val;
	113	qemu_chr_write(s->chr, &ch, 1);
	114	}
	115	s->dr = val;
	116	s->flags &= ~SH_SERIAL_FLAG_TDE;
	117	return;
	118	#if 0
	119	case 0x14: /* FRDR / RDR */
	120	ret = 0;
	121	break;
	122	#endif
	123	}
	124	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	125	switch(offs) {
	126	case 0x10: /* FSR */
	127	if (!(val & (1 << 6)))
	128	s->flags &= ~SH_SERIAL_FLAG_TEND;
	129	if (!(val & (1 << 5)))
	130	s->flags &= ~SH_SERIAL_FLAG_TDE;
	131	if (!(val & (1 << 4)))
	132	s->flags &= ~SH_SERIAL_FLAG_BRK;
	133	if (!(val & (1 << 1)))
	134	s->flags &= ~SH_SERIAL_FLAG_RDF;
	135	if (!(val & (1 << 0)))
	136	s->flags &= ~SH_SERIAL_FLAG_DR;
63242a00 AJ	137
	138	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
	139	if (s->rxi && s->rxi->asserted) {
	140	sh_intc_toggle_source(s->rxi, 0, -1);
	141	}
	142	}
2f062c72 TS	143	return;
	144	case 0x18: /* FCR */
	145	s->fcr = val;
63242a00 AJ	146	switch ((val >> 6) & 3) {
	147	case 0:
	148	s->rtrg = 1;
	149	break;
	150	case 1:
	151	s->rtrg = 4;
	152	break;
	153	case 2:
	154	s->rtrg = 8;
	155	break;
	156	case 3:
	157	s->rtrg = 14;
	158	break;
	159	}
	160	if (val & (1 << 1)) {
	161	sh_serial_clear_fifo(s);
	162	s->sr &= ~(1 << 1);
	163	}
	164
2f062c72 TS	165	return;
2f062c72 TS	166	case 0x20: /* SPTR */
63242a00	167	s->sptr = val & 0xf3;
2f062c72 TS	168	return;
	169	case 0x24: /* LSR */
	170	return;
	171	}
	172	}
	173	else {
	174	#if 0
	175	switch(offs) {
	176	case 0x0c:
	177	ret = s->dr;
	178	break;
	179	case 0x10:
	180	ret = 0;
	181	break;
	182	case 0x1c:
	183	ret = s->sptr;
	184	break;
	185	}
	186	#endif
	187	}
	188
	189	fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
	190	assert(0);
	191	}
	192
	193	static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
	194	{
	195	sh_serial_state *s = opaque;
	196	uint32_t ret = ~0;
	197
	198	#if 0
	199	switch(offs) {
	200	case 0x00:
	201	ret = s->smr;
	202	break;
	203	case 0x04:
	204	ret = s->brr;
	205	break;
	206	case 0x08:
	207	ret = s->scr;
	208	break;
	209	case 0x14:
	210	ret = 0;
	211	break;
	212	}
	213	#endif
	214	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	215	switch(offs) {
bf5b7423 AJ	216	case 0x00: /* SMR */
	217	ret = s->smr;
	218	break;
	219	case 0x08: /* SCR */
	220	ret = s->scr;
	221	break;
2f062c72 TS	222	case 0x10: /* FSR */
	223	ret = 0;
	224	if (s->flags & SH_SERIAL_FLAG_TEND)
	225	ret \|= (1 << 6);
	226	if (s->flags & SH_SERIAL_FLAG_TDE)
	227	ret \|= (1 << 5);
	228	if (s->flags & SH_SERIAL_FLAG_BRK)
	229	ret \|= (1 << 4);
	230	if (s->flags & SH_SERIAL_FLAG_RDF)
	231	ret \|= (1 << 1);
	232	if (s->flags & SH_SERIAL_FLAG_DR)
	233	ret \|= (1 << 0);
	234
63242a00	235	if (s->scr & (1 << 5))
2f062c72 TS	236	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
2f062c72 TS	237
63242a00 AJ	238	break;
	239	case 0x14:
	240	if (s->rx_cnt > 0) {
	241	ret = s->rx_fifo[s->rx_tail++];
	242	s->rx_cnt--;
	243	if (s->rx_tail == SH_RX_FIFO_LENGTH)
	244	s->rx_tail = 0;
	245	if (s->rx_cnt < s->rtrg)
	246	s->flags &= ~SH_SERIAL_FLAG_RDF;
	247	}
2f062c72 TS	248	break;
	249	#if 0
	250	case 0x18:
	251	ret = s->fcr;
	252	break;
	253	#endif
	254	case 0x1c:
	255	ret = s->rx_cnt;
	256	break;
	257	case 0x20:
	258	ret = s->sptr;
	259	break;
	260	case 0x24:
	261	ret = 0;
	262	break;
	263	}
	264	}
	265	else {
	266	#if 0
	267	switch(offs) {
	268	case 0x0c:
	269	ret = s->dr;
	270	break;
	271	case 0x10:
	272	ret = 0;
	273	break;
63242a00 AJ	274	case 0x14:
	275	ret = s->rx_fifo[0];
	276	break;
2f062c72 TS	277	case 0x1c:
	278	ret = s->sptr;
	279	break;
	280	}
	281	#endif
	282	}
	283	#ifdef DEBUG_SERIAL
	284	printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
	285	(unsigned long) s->base, offs, ret);
	286	#endif
	287
	288	if (ret & ~((1 << 16) - 1)) {
	289	fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
	290	assert(0);
	291	}
	292
	293	return ret;
	294	}
	295
	296	static int sh_serial_can_receive(sh_serial_state *s)
	297	{
63242a00	298	return s->scr & (1 << 4);
2f062c72 TS	299	}
	300
	301	static void sh_serial_receive_byte(sh_serial_state *s, int ch)
	302	{
63242a00 AJ	303	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	304	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	305	s->rx_fifo[s->rx_head++] = ch;
	306	if (s->rx_head == SH_RX_FIFO_LENGTH)
	307	s->rx_head = 0;
	308	s->rx_cnt++;
	309	if (s->rx_cnt >= s->rtrg) {
	310	s->flags \|= SH_SERIAL_FLAG_RDF;
	311	if (s->scr & (1 << 6) && s->rxi) {
	312	sh_intc_toggle_source(s->rxi, 0, 1);
	313	}
	314	}
	315	}
	316	} else {
	317	s->rx_fifo[0] = ch;
	318	}
2f062c72 TS	319	}
	320
	321	static void sh_serial_receive_break(sh_serial_state *s)
	322	{
63242a00 AJ	323	if (s->feat & SH_SERIAL_FEAT_SCIF)
63242a00 AJ	324	s->sr \|= (1 << 4);
2f062c72 TS	325	}
	326
	327	static int sh_serial_can_receive1(void *opaque)
	328	{
	329	sh_serial_state *s = opaque;
	330	return sh_serial_can_receive(s);
	331	}
	332
	333	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	334	{
	335	sh_serial_state *s = opaque;
	336	sh_serial_receive_byte(s, buf[0]);
	337	}
	338
	339	static void sh_serial_event(void *opaque, int event)
	340	{
	341	sh_serial_state *s = opaque;
	342	if (event == CHR_EVENT_BREAK)
	343	sh_serial_receive_break(s);
	344	}
	345
9596ebb7	346	static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
2f062c72 TS	347	{
	348	sh_serial_state *s = opaque;
	349	return sh_serial_ioport_read(s, addr - s->base);
	350	}
	351
9596ebb7 PB	352	static void sh_serial_write (void *opaque,
9596ebb7 PB	353	target_phys_addr_t addr, uint32_t value)
2f062c72 TS	354	{
	355	sh_serial_state *s = opaque;
	356	sh_serial_ioport_write(s, addr - s->base, value);
	357	}
	358
	359	static CPUReadMemoryFunc *sh_serial_readfn[] = {
	360	&sh_serial_read,
	361	&sh_serial_read,
	362	&sh_serial_read,
	363	};
	364
	365	static CPUWriteMemoryFunc *sh_serial_writefn[] = {
	366	&sh_serial_write,
	367	&sh_serial_write,
	368	&sh_serial_write,
	369	};
	370
	371	void sh_serial_init (target_phys_addr_t base, int feat,
bf5b7423 AJ	372	uint32_t freq, CharDriverState *chr,
	373	struct intc_source *eri_source,
	374	struct intc_source *rxi_source,
	375	struct intc_source *txi_source,
	376	struct intc_source *tei_source,
	377	struct intc_source *bri_source)
2f062c72 TS	378	{
	379	sh_serial_state *s;
	380	int s_io_memory;
	381
	382	s = qemu_mallocz(sizeof(sh_serial_state));
	383	if (!s)
	384	return;
	385
	386	s->base = base;
	387	s->feat = feat;
	388	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	389	s->rtrg = 1;
2f062c72 TS	390
	391	s->smr = 0;
	392	s->brr = 0xff;
b7d35e65	393	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	394	s->sptr = 0;
	395
	396	if (feat & SH_SERIAL_FEAT_SCIF) {
	397	s->fcr = 0;
	398	}
	399	else {
	400	s->dr = 0xff;
	401	}
	402
63242a00	403	sh_serial_clear_fifo(s);
2f062c72 TS	404
	405	s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
	406	sh_serial_writefn, s);
	407	cpu_register_physical_memory(base, 0x28, s_io_memory);
	408
	409	s->chr = chr;
	410
	411	if (chr)
	412	qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
	413	sh_serial_event, s);
bf5b7423 AJ	414
	415	s->eri = eri_source;
	416	s->rxi = rxi_source;
	417	s->txi = txi_source;
	418	s->tei = tei_source;
	419	s->bri = bri_source;
2f062c72	420	}