[qemu.git] / target / sparc / fop_helper.c

/*
 * FPU op helpers
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"

#define QT0 (env->qt0)
#define QT1 (env->qt1)

static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
{
    target_ulong status = get_float_exception_flags(&env->fp_status);
    target_ulong fsr = env->fsr;

    if (unlikely(status)) {
        /* Keep exception flags clear for next time.  */
        set_float_exception_flags(0, &env->fp_status);

        /* Copy IEEE 754 flags into FSR */
        if (status & float_flag_invalid) {
            fsr |= FSR_NVC;
        }
        if (status & float_flag_overflow) {
            fsr |= FSR_OFC;
        }
        if (status & float_flag_underflow) {
            fsr |= FSR_UFC;
        }
        if (status & float_flag_divbyzero) {
            fsr |= FSR_DZC;
        }
        if (status & float_flag_inexact) {
            fsr |= FSR_NXC;
        }

        if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
            CPUState *cs = CPU(sparc_env_get_cpu(env));

            /* Unmasked exception, generate a trap.  Note that while
               the helper is marked as NO_WG, we can get away with
               writing to cpu state along the exception path, since
               TCG generated code will never see the write.  */
            env->fsr = fsr | FSR_FTT_IEEE_EXCP;
            cs->exception_index = TT_FP_EXCP;
            cpu_loop_exit_restore(cs, ra);
        } else {
            /* Accumulate exceptions */
            fsr |= (fsr & FSR_CEXC_MASK) << 5;
        }
    }

    return fsr;
}

target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
{
    return do_check_ieee_exceptions(env, GETPC());
}

#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)

#define F_BINOP(name)                                           \
    float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
                                   float32 src2)                \
    {                                                           \
        return float32_ ## name (src1, src2, &env->fp_status);  \
    }                                                           \
    float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
                                   float64 src2)                \
    {                                                           \
        return float64_ ## name (src1, src2, &env->fp_status);  \
    }                                                           \
    F_HELPER(name, q)                                           \
    {                                                           \
        QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \
    }

F_BINOP(add);
F_BINOP(sub);
F_BINOP(mul);
F_BINOP(div);
#undef F_BINOP

float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
{
    return float64_mul(float32_to_float64(src1, &env->fp_status),
                       float32_to_float64(src2, &env->fp_status),
                       &env->fp_status);
}

void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
{
    QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
                       float64_to_float128(src2, &env->fp_status),
                       &env->fp_status);
}

float32 helper_fnegs(float32 src)
{
    return float32_chs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fnegd(float64 src)
{
    return float64_chs(src);
}

F_HELPER(neg, q)
{
    QT0 = float128_chs(QT1);
}
#endif

/* Integer to float conversion.  */
float32 helper_fitos(CPUSPARCState *env, int32_t src)
{
    return int32_to_float32(src, &env->fp_status);
}

float64 helper_fitod(CPUSPARCState *env, int32_t src)
{
    return int32_to_float64(src, &env->fp_status);
}

void helper_fitoq(CPUSPARCState *env, int32_t src)
{
    QT0 = int32_to_float128(src, &env->fp_status);
}

#ifdef TARGET_SPARC64
float32 helper_fxtos(CPUSPARCState *env, int64_t src)
{
    return int64_to_float32(src, &env->fp_status);
}

float64 helper_fxtod(CPUSPARCState *env, int64_t src)
{
    return int64_to_float64(src, &env->fp_status);
}

void helper_fxtoq(CPUSPARCState *env, int64_t src)
{
    QT0 = int64_to_float128(src, &env->fp_status);
}
#endif
#undef F_HELPER

/* floating point conversion */
float32 helper_fdtos(CPUSPARCState *env, float64 src)
{
    return float64_to_float32(src, &env->fp_status);
}

float64 helper_fstod(CPUSPARCState *env, float32 src)
{
    return float32_to_float64(src, &env->fp_status);
}

float32 helper_fqtos(CPUSPARCState *env)
{
    return float128_to_float32(QT1, &env->fp_status);
}

void helper_fstoq(CPUSPARCState *env, float32 src)
{
    QT0 = float32_to_float128(src, &env->fp_status);
}

float64 helper_fqtod(CPUSPARCState *env)
{
    return float128_to_float64(QT1, &env->fp_status);
}

void helper_fdtoq(CPUSPARCState *env, float64 src)
{
    QT0 = float64_to_float128(src, &env->fp_status);
}

/* Float to integer conversion.  */
int32_t helper_fstoi(CPUSPARCState *env, float32 src)
{
    return float32_to_int32_round_to_zero(src, &env->fp_status);
}

int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
{
    return float64_to_int32_round_to_zero(src, &env->fp_status);
}

int32_t helper_fqtoi(CPUSPARCState *env)
{
    return float128_to_int32_round_to_zero(QT1, &env->fp_status);
}

#ifdef TARGET_SPARC64
int64_t helper_fstox(CPUSPARCState *env, float32 src)
{
    return float32_to_int64_round_to_zero(src, &env->fp_status);
}

int64_t helper_fdtox(CPUSPARCState *env, float64 src)
{
    return float64_to_int64_round_to_zero(src, &env->fp_status);
}

int64_t helper_fqtox(CPUSPARCState *env)
{
    return float128_to_int64_round_to_zero(QT1, &env->fp_status);
}
#endif

float32 helper_fabss(float32 src)
{
    return float32_abs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fabsd(float64 src)
{
    return float64_abs(src);
}

void helper_fabsq(CPUSPARCState *env)
{
    QT0 = float128_abs(QT1);
}
#endif

float32 helper_fsqrts(CPUSPARCState *env, float32 src)
{
    return float32_sqrt(src, &env->fp_status);
}

float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
{
    return float64_sqrt(src, &env->fp_status);
}

void helper_fsqrtq(CPUSPARCState *env)
{
    QT0 = float128_sqrt(QT1, &env->fp_status);
}

#define GEN_FCMP(name, size, reg1, reg2, FS, E)                         \
    target_ulong glue(helper_, name) (CPUSPARCState *env)               \
    {                                                                   \
        int ret;                                                        \
        target_ulong fsr;                                               \
        if (E) {                                                        \
            ret = glue(size, _compare)(reg1, reg2, &env->fp_status);    \
        } else {                                                        \
            ret = glue(size, _compare_quiet)(reg1, reg2,                \
                                             &env->fp_status);          \
        }                                                               \
        fsr = do_check_ieee_exceptions(env, GETPC());                   \
        switch (ret) {                                                  \
        case float_relation_unordered:                                  \
            fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                         \
            fsr |= FSR_NVA;                                             \
            break;                                                      \
        case float_relation_less:                                       \
            fsr &= ~(FSR_FCC1) << FS;                                   \
            fsr |= FSR_FCC0 << FS;                                      \
            break;                                                      \
        case float_relation_greater:                                    \
            fsr &= ~(FSR_FCC0) << FS;                                   \
            fsr |= FSR_FCC1 << FS;                                      \
            break;                                                      \
        default:                                                        \
            fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                      \
            break;                                                      \
        }                                                               \
        return fsr;                                                     \
    }
#define GEN_FCMP_T(name, size, FS, E)                                   \
    target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\
    {                                                                   \
        int ret;                                                        \
        target_ulong fsr;                                               \
        if (E) {                                                        \
            ret = glue(size, _compare)(src1, src2, &env->fp_status);    \
        } else {                                                        \
            ret = glue(size, _compare_quiet)(src1, src2,                \
                                             &env->fp_status);          \
        }                                                               \
        fsr = do_check_ieee_exceptions(env, GETPC());                   \
        switch (ret) {                                                  \
        case float_relation_unordered:                                  \
            fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                         \
            break;                                                      \
        case float_relation_less:                                       \
            fsr &= ~(FSR_FCC1 << FS);                                   \
            fsr |= FSR_FCC0 << FS;                                      \
            break;                                                      \
        case float_relation_greater:                                    \
            fsr &= ~(FSR_FCC0 << FS);                                   \
            fsr |= FSR_FCC1 << FS;                                      \
            break;                                                      \
        default:                                                        \
            fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                      \
            break;                                                      \
        }                                                               \
        return fsr;                                                     \
    }

GEN_FCMP_T(fcmps, float32, 0, 0);
GEN_FCMP_T(fcmpd, float64, 0, 0);

GEN_FCMP_T(fcmpes, float32, 0, 1);
GEN_FCMP_T(fcmped, float64, 0, 1);

GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);

#ifdef TARGET_SPARC64
GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);

GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);

GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);

GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);

GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);

GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#endif
#undef GEN_FCMP_T
#undef GEN_FCMP

static void set_fsr(CPUSPARCState *env, target_ulong fsr)
{
    int rnd_mode;

    switch (fsr & FSR_RD_MASK) {
    case FSR_RD_NEAREST:
        rnd_mode = float_round_nearest_even;
        break;
    default:
    case FSR_RD_ZERO:
        rnd_mode = float_round_to_zero;
        break;
    case FSR_RD_POS:
        rnd_mode = float_round_up;
        break;
    case FSR_RD_NEG:
        rnd_mode = float_round_down;
        break;
    }
    set_float_rounding_mode(rnd_mode, &env->fp_status);
}

target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
                          uint32_t new_fsr)
{
    old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
    set_fsr(env, old_fsr);
    return old_fsr;
}

#ifdef TARGET_SPARC64
target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
                           uint64_t new_fsr)
{
    old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
    set_fsr(env, old_fsr);
    return old_fsr;
}
#endif
Commit	Line	Data
1bccec25 BS	1	/*
	2	* FPU op helpers
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
db5ebe5f	20	#include "qemu/osdep.h"
1bccec25	21	#include "cpu.h"
02c79d78	22	#include "exec/exec-all.h"
2ef6175a	23	#include "exec/helper-proto.h"
1bccec25	24
1bccec25 BS	25	#define QT0 (env->qt0)
	26	#define QT1 (env->qt1)
	27
02c79d78	28	static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
44516772	29	{
7385aed2 RH	30	target_ulong status = get_float_exception_flags(&env->fp_status);
	31	target_ulong fsr = env->fsr;
	32
	33	if (unlikely(status)) {
	34	/* Keep exception flags clear for next time. */
	35	set_float_exception_flags(0, &env->fp_status);
44516772	36
44516772 RH	37	/* Copy IEEE 754 flags into FSR */
44516772 RH	38	if (status & float_flag_invalid) {
7385aed2	39	fsr \|= FSR_NVC;
44516772 RH	40	}
44516772 RH	41	if (status & float_flag_overflow) {
7385aed2	42	fsr \|= FSR_OFC;
44516772 RH	43	}
44516772 RH	44	if (status & float_flag_underflow) {
7385aed2	45	fsr \|= FSR_UFC;
44516772 RH	46	}
44516772 RH	47	if (status & float_flag_divbyzero) {
7385aed2	48	fsr \|= FSR_DZC;
44516772 RH	49	}
44516772 RH	50	if (status & float_flag_inexact) {
7385aed2	51	fsr \|= FSR_NXC;
44516772 RH	52	}
44516772 RH	53
7385aed2	54	if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
02c79d78 RH	55	CPUState *cs = CPU(sparc_env_get_cpu(env));
02c79d78 RH	56
7385aed2 RH	57	/* Unmasked exception, generate a trap. Note that while
	58	the helper is marked as NO_WG, we can get away with
	59	writing to cpu state along the exception path, since
	60	TCG generated code will never see the write. */
	61	env->fsr = fsr \| FSR_FTT_IEEE_EXCP;
02c79d78 RH	62	cs->exception_index = TT_FP_EXCP;
02c79d78 RH	63	cpu_loop_exit_restore(cs, ra);
44516772 RH	64	} else {
44516772 RH	65	/* Accumulate exceptions */
7385aed2	66	fsr \|= (fsr & FSR_CEXC_MASK) << 5;
44516772 RH	67	}
44516772 RH	68	}
44516772	69
7385aed2	70	return fsr;
44516772 RH	71	}
44516772 RH	72
02c79d78 RH	73	target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
	74	{
	75	return do_check_ieee_exceptions(env, GETPC());
	76	}
	77
c5f9864e	78	#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
1bccec25 BS	79
1bccec25 BS	80	#define F_BINOP(name) \
c5f9864e	81	float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
2e2f4ade	82	float32 src2) \
1bccec25	83	{ \
7385aed2	84	return float32_ ## name (src1, src2, &env->fp_status); \
1bccec25	85	} \
c5f9864e	86	float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
03fb8cfc	87	float64 src2) \
1bccec25	88	{ \
7385aed2	89	return float64_ ## name (src1, src2, &env->fp_status); \
1bccec25 BS	90	} \
	91	F_HELPER(name, q) \
	92	{ \
	93	QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
	94	}
	95
	96	F_BINOP(add);
	97	F_BINOP(sub);
	98	F_BINOP(mul);
	99	F_BINOP(div);
	100	#undef F_BINOP
	101
c5f9864e	102	float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
1bccec25	103	{
7385aed2 RH	104	return float64_mul(float32_to_float64(src1, &env->fp_status),
	105	float32_to_float64(src2, &env->fp_status),
	106	&env->fp_status);
1bccec25 BS	107	}
1bccec25 BS	108
c5f9864e	109	void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
1bccec25	110	{
03fb8cfc RH	111	QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
03fb8cfc RH	112	float64_to_float128(src2, &env->fp_status),
1bccec25 BS	113	&env->fp_status);
	114	}
	115
	116	float32 helper_fnegs(float32 src)
	117	{
	118	return float32_chs(src);
	119	}
	120
	121	#ifdef TARGET_SPARC64
03fb8cfc	122	float64 helper_fnegd(float64 src)
1bccec25	123	{
03fb8cfc	124	return float64_chs(src);
1bccec25 BS	125	}
	126
	127	F_HELPER(neg, q)
	128	{
	129	QT0 = float128_chs(QT1);
	130	}
	131	#endif
	132
	133	/* Integer to float conversion. */
c5f9864e	134	float32 helper_fitos(CPUSPARCState *env, int32_t src)
1bccec25	135	{
7385aed2	136	return int32_to_float32(src, &env->fp_status);
1bccec25 BS	137	}
1bccec25 BS	138
c5f9864e	139	float64 helper_fitod(CPUSPARCState *env, int32_t src)
1bccec25	140	{
03fb8cfc	141	return int32_to_float64(src, &env->fp_status);
1bccec25 BS	142	}
1bccec25 BS	143
c5f9864e	144	void helper_fitoq(CPUSPARCState *env, int32_t src)
1bccec25 BS	145	{
	146	QT0 = int32_to_float128(src, &env->fp_status);
	147	}
	148
	149	#ifdef TARGET_SPARC64
c5f9864e	150	float32 helper_fxtos(CPUSPARCState *env, int64_t src)
1bccec25	151	{
7385aed2	152	return int64_to_float32(src, &env->fp_status);
1bccec25 BS	153	}
1bccec25 BS	154
c5f9864e	155	float64 helper_fxtod(CPUSPARCState *env, int64_t src)
1bccec25	156	{
7385aed2	157	return int64_to_float64(src, &env->fp_status);
1bccec25 BS	158	}
1bccec25 BS	159
c5f9864e	160	void helper_fxtoq(CPUSPARCState *env, int64_t src)
1bccec25	161	{
03fb8cfc	162	QT0 = int64_to_float128(src, &env->fp_status);
1bccec25 BS	163	}
	164	#endif
	165	#undef F_HELPER
	166
	167	/* floating point conversion */
c5f9864e	168	float32 helper_fdtos(CPUSPARCState *env, float64 src)
1bccec25	169	{
7385aed2	170	return float64_to_float32(src, &env->fp_status);
1bccec25 BS	171	}
1bccec25 BS	172
c5f9864e	173	float64 helper_fstod(CPUSPARCState *env, float32 src)
1bccec25	174	{
7385aed2	175	return float32_to_float64(src, &env->fp_status);
1bccec25 BS	176	}
1bccec25 BS	177
c5f9864e	178	float32 helper_fqtos(CPUSPARCState *env)
1bccec25	179	{
7385aed2	180	return float128_to_float32(QT1, &env->fp_status);
1bccec25 BS	181	}
1bccec25 BS	182
c5f9864e	183	void helper_fstoq(CPUSPARCState *env, float32 src)
1bccec25 BS	184	{
	185	QT0 = float32_to_float128(src, &env->fp_status);
	186	}
	187
c5f9864e	188	float64 helper_fqtod(CPUSPARCState *env)
1bccec25	189	{
7385aed2	190	return float128_to_float64(QT1, &env->fp_status);
1bccec25 BS	191	}
1bccec25 BS	192
c5f9864e	193	void helper_fdtoq(CPUSPARCState *env, float64 src)
1bccec25	194	{
03fb8cfc	195	QT0 = float64_to_float128(src, &env->fp_status);
1bccec25 BS	196	}
	197
	198	/* Float to integer conversion. */
c5f9864e	199	int32_t helper_fstoi(CPUSPARCState *env, float32 src)
1bccec25	200	{
7385aed2	201	return float32_to_int32_round_to_zero(src, &env->fp_status);
1bccec25 BS	202	}
1bccec25 BS	203
c5f9864e	204	int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
1bccec25	205	{
7385aed2	206	return float64_to_int32_round_to_zero(src, &env->fp_status);
1bccec25 BS	207	}
1bccec25 BS	208
c5f9864e	209	int32_t helper_fqtoi(CPUSPARCState *env)
1bccec25	210	{
7385aed2	211	return float128_to_int32_round_to_zero(QT1, &env->fp_status);
1bccec25 BS	212	}
	213
	214	#ifdef TARGET_SPARC64
c5f9864e	215	int64_t helper_fstox(CPUSPARCState *env, float32 src)
1bccec25	216	{
7385aed2	217	return float32_to_int64_round_to_zero(src, &env->fp_status);
1bccec25 BS	218	}
1bccec25 BS	219
c5f9864e	220	int64_t helper_fdtox(CPUSPARCState *env, float64 src)
1bccec25	221	{
7385aed2	222	return float64_to_int64_round_to_zero(src, &env->fp_status);
1bccec25 BS	223	}
1bccec25 BS	224
c5f9864e	225	int64_t helper_fqtox(CPUSPARCState *env)
1bccec25	226	{
7385aed2	227	return float128_to_int64_round_to_zero(QT1, &env->fp_status);
1bccec25 BS	228	}
	229	#endif
	230
	231	float32 helper_fabss(float32 src)
	232	{
	233	return float32_abs(src);
	234	}
	235
	236	#ifdef TARGET_SPARC64
f027c3b1	237	float64 helper_fabsd(float64 src)
1bccec25	238	{
03fb8cfc	239	return float64_abs(src);
1bccec25 BS	240	}
1bccec25 BS	241
c5f9864e	242	void helper_fabsq(CPUSPARCState *env)
1bccec25 BS	243	{
	244	QT0 = float128_abs(QT1);
	245	}
	246	#endif
	247
c5f9864e	248	float32 helper_fsqrts(CPUSPARCState *env, float32 src)
1bccec25	249	{
7385aed2	250	return float32_sqrt(src, &env->fp_status);
1bccec25 BS	251	}
1bccec25 BS	252
c5f9864e	253	float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
1bccec25	254	{
7385aed2	255	return float64_sqrt(src, &env->fp_status);
1bccec25 BS	256	}
1bccec25 BS	257
c5f9864e	258	void helper_fsqrtq(CPUSPARCState *env)
1bccec25 BS	259	{
	260	QT0 = float128_sqrt(QT1, &env->fp_status);
	261	}
	262
	263	#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
7385aed2	264	target_ulong glue(helper_, name) (CPUSPARCState *env) \
1bccec25	265	{ \
5acfc832	266	int ret; \
7385aed2	267	target_ulong fsr; \
5acfc832 AJ	268	if (E) { \
	269	ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \
	270	} else { \
	271	ret = glue(size, _compare_quiet)(reg1, reg2, \
	272	&env->fp_status); \
1bccec25	273	} \
02c79d78	274	fsr = do_check_ieee_exceptions(env, GETPC()); \
5acfc832	275	switch (ret) { \
1bccec25	276	case float_relation_unordered: \
7385aed2 RH	277	fsr \|= (FSR_FCC1 \| FSR_FCC0) << FS; \
7385aed2 RH	278	fsr \|= FSR_NVA; \
1bccec25 BS	279	break; \
1bccec25 BS	280	case float_relation_less: \
7385aed2 RH	281	fsr &= ~(FSR_FCC1) << FS; \
7385aed2 RH	282	fsr \|= FSR_FCC0 << FS; \
1bccec25 BS	283	break; \
1bccec25 BS	284	case float_relation_greater: \
7385aed2 RH	285	fsr &= ~(FSR_FCC0) << FS; \
7385aed2 RH	286	fsr \|= FSR_FCC1 << FS; \
1bccec25 BS	287	break; \
1bccec25 BS	288	default: \
7385aed2	289	fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
1bccec25 BS	290	break; \
1bccec25 BS	291	} \
7385aed2	292	return fsr; \
1bccec25	293	}
03fb8cfc	294	#define GEN_FCMP_T(name, size, FS, E) \
7385aed2	295	target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\
1bccec25	296	{ \
5acfc832	297	int ret; \
7385aed2	298	target_ulong fsr; \
5acfc832 AJ	299	if (E) { \
	300	ret = glue(size, _compare)(src1, src2, &env->fp_status); \
	301	} else { \
	302	ret = glue(size, _compare_quiet)(src1, src2, \
	303	&env->fp_status); \
1bccec25	304	} \
02c79d78	305	fsr = do_check_ieee_exceptions(env, GETPC()); \
5acfc832	306	switch (ret) { \
1bccec25	307	case float_relation_unordered: \
7385aed2	308	fsr \|= (FSR_FCC1 \| FSR_FCC0) << FS; \
1bccec25 BS	309	break; \
1bccec25 BS	310	case float_relation_less: \
7385aed2 RH	311	fsr &= ~(FSR_FCC1 << FS); \
7385aed2 RH	312	fsr \|= FSR_FCC0 << FS; \
1bccec25 BS	313	break; \
1bccec25 BS	314	case float_relation_greater: \
7385aed2 RH	315	fsr &= ~(FSR_FCC0 << FS); \
7385aed2 RH	316	fsr \|= FSR_FCC1 << FS; \
1bccec25 BS	317	break; \
1bccec25 BS	318	default: \
7385aed2	319	fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
1bccec25 BS	320	break; \
1bccec25 BS	321	} \
7385aed2	322	return fsr; \
1bccec25 BS	323	}
1bccec25 BS	324
03fb8cfc RH	325	GEN_FCMP_T(fcmps, float32, 0, 0);
03fb8cfc RH	326	GEN_FCMP_T(fcmpd, float64, 0, 0);
1bccec25	327
03fb8cfc RH	328	GEN_FCMP_T(fcmpes, float32, 0, 1);
03fb8cfc RH	329	GEN_FCMP_T(fcmped, float64, 0, 1);
1bccec25 BS	330
	331	GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
	332	GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
	333
	334	#ifdef TARGET_SPARC64
03fb8cfc RH	335	GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
03fb8cfc RH	336	GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
1bccec25 BS	337	GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1bccec25 BS	338
03fb8cfc RH	339	GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
03fb8cfc RH	340	GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
1bccec25 BS	341	GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1bccec25 BS	342
03fb8cfc RH	343	GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
03fb8cfc RH	344	GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
1bccec25 BS	345	GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1bccec25 BS	346
03fb8cfc RH	347	GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
03fb8cfc RH	348	GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
1bccec25 BS	349	GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1bccec25 BS	350
03fb8cfc RH	351	GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
03fb8cfc RH	352	GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
1bccec25 BS	353	GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1bccec25 BS	354
03fb8cfc RH	355	GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
03fb8cfc RH	356	GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
1bccec25 BS	357	GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1bccec25 BS	358	#endif
03fb8cfc RH	359	#undef GEN_FCMP_T
03fb8cfc RH	360	#undef GEN_FCMP
1bccec25	361
7385aed2	362	static void set_fsr(CPUSPARCState *env, target_ulong fsr)
1bccec25 BS	363	{
	364	int rnd_mode;
	365
7385aed2	366	switch (fsr & FSR_RD_MASK) {
1bccec25 BS	367	case FSR_RD_NEAREST:
	368	rnd_mode = float_round_nearest_even;
	369	break;
	370	default:
	371	case FSR_RD_ZERO:
	372	rnd_mode = float_round_to_zero;
	373	break;
	374	case FSR_RD_POS:
	375	rnd_mode = float_round_up;
	376	break;
	377	case FSR_RD_NEG:
	378	rnd_mode = float_round_down;
	379	break;
	380	}
	381	set_float_rounding_mode(rnd_mode, &env->fp_status);
	382	}
	383
7385aed2 RH	384	target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
7385aed2 RH	385	uint32_t new_fsr)
1bccec25	386	{
7385aed2 RH	387	old_fsr = (new_fsr & FSR_LDFSR_MASK) \| (old_fsr & FSR_LDFSR_OLDMASK);
	388	set_fsr(env, old_fsr);
	389	return old_fsr;
1bccec25 BS	390	}
	391
	392	#ifdef TARGET_SPARC64
7385aed2 RH	393	target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
7385aed2 RH	394	uint64_t new_fsr)
1bccec25	395	{
7385aed2 RH	396	old_fsr = (new_fsr & FSR_LDXFSR_MASK) \| (old_fsr & FSR_LDXFSR_OLDMASK);
	397	set_fsr(env, old_fsr);
	398	return old_fsr;
1bccec25 BS	399	}
1bccec25 BS	400	#endif