[qemu.git] / hw / dma / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"

#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

typedef struct {
    uint32_t src;
    uint32_t dest;
    uint32_t lli;
    uint32_t ctrl;
    uint32_t conf;
} pl080_channel;

#define TYPE_PL080 "pl080"
#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)

typedef struct PL080State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint8_t tc_int;
    uint8_t tc_mask;
    uint8_t err_int;
    uint8_t err_mask;
    uint32_t conf;
    uint32_t sync;
    uint32_t req_single;
    uint32_t req_burst;
    pl080_channel chan[PL080_MAX_CHANNELS];
    int nchannels;
    /* Flag to avoid recursive DMA invocations.  */
    int running;
    qemu_irq irq;
} PL080State;

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_mask, PL080State),
        VMSTATE_UINT8(err_int, PL080State),
        VMSTATE_UINT8(err_mask, PL080State),
        VMSTATE_UINT32(conf, PL080State),
        VMSTATE_UINT32(sync, PL080State),
        VMSTATE_UINT32(req_single, PL080State),
        VMSTATE_UINT32(req_burst, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, PL080State),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(PL080State *s)
{
    if ((s->tc_int & s->tc_mask)
            || (s->err_int & s->err_mask))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void pl080_run(PL080State *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = ldl_le_phys(ch->lli);
                    ch->dest = ldl_le_phys(ch->lli + 4);
                    ch->ctrl = ldl_le_phys(ch->lli + 12);
                    ch->lli = ldl_le_phys(ch->lli + 8);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint64_t pl080_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
            qemu_log_mask(LOG_UNIMP,
                          "pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static const MemoryRegionOps pl080_ops = {
    .read = pl080_read,
    .write = pl080_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl080_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL080State *s = PL080(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->nchannels = 8;
}

static void pl081_init(Object *obj)
{
    PL080State *s = PL080(obj);

    s->nchannels = 2;
}

static void pl080_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->no_user = 1;
    dc->vmsd = &vmstate_pl080;
}

static const TypeInfo pl080_info = {
    .name          = TYPE_PL080,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL080State),
    .instance_init = pl080_init,
    .class_init    = pl080_class_init,
};

static const TypeInfo pl081_info = {
    .name          = "pl081",
    .parent        = TYPE_PL080,
    .instance_init = pl081_init,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_types(void)
{
    type_register_static(&pl080_info);
    type_register_static(&pl081_info);
}

type_init(pl080_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
cdbdb648	11
e69954b9	12	#define PL080_MAX_CHANNELS 8
cdbdb648 PB	13	#define PL080_CONF_E 0x1
	14	#define PL080_CONF_M1 0x2
	15	#define PL080_CONF_M2 0x4
	16
	17	#define PL080_CCONF_H 0x40000
	18	#define PL080_CCONF_A 0x20000
	19	#define PL080_CCONF_L 0x10000
	20	#define PL080_CCONF_ITC 0x08000
	21	#define PL080_CCONF_IE 0x04000
	22	#define PL080_CCONF_E 0x00001
	23
	24	#define PL080_CCTRL_I 0x80000000
	25	#define PL080_CCTRL_DI 0x08000000
	26	#define PL080_CCTRL_SI 0x04000000
	27	#define PL080_CCTRL_D 0x02000000
	28	#define PL080_CCTRL_S 0x01000000
	29
	30	typedef struct {
	31	uint32_t src;
	32	uint32_t dest;
	33	uint32_t lli;
	34	uint32_t ctrl;
	35	uint32_t conf;
	36	} pl080_channel;
	37
4f800554 AF	38	#define TYPE_PL080 "pl080"
	39	#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
	40
d7ba0a62	41	typedef struct PL080State {
4f800554 AF	42	SysBusDevice parent_obj;
4f800554 AF	43
63b02e04	44	MemoryRegion iomem;
cdbdb648 PB	45	uint8_t tc_int;
	46	uint8_t tc_mask;
	47	uint8_t err_int;
	48	uint8_t err_mask;
	49	uint32_t conf;
	50	uint32_t sync;
	51	uint32_t req_single;
	52	uint32_t req_burst;
e69954b9 PB	53	pl080_channel chan[PL080_MAX_CHANNELS];
e69954b9 PB	54	int nchannels;
cdbdb648 PB	55	/* Flag to avoid recursive DMA invocations. */
cdbdb648 PB	56	int running;
d537cf6c	57	qemu_irq irq;
d7ba0a62	58	} PL080State;
cdbdb648	59
ff175853 PM	60	static const VMStateDescription vmstate_pl080_channel = {
	61	.name = "pl080_channel",
	62	.version_id = 1,
	63	.minimum_version_id = 1,
	64	.fields = (VMStateField[]) {
	65	VMSTATE_UINT32(src, pl080_channel),
	66	VMSTATE_UINT32(dest, pl080_channel),
	67	VMSTATE_UINT32(lli, pl080_channel),
	68	VMSTATE_UINT32(ctrl, pl080_channel),
	69	VMSTATE_UINT32(conf, pl080_channel),
	70	VMSTATE_END_OF_LIST()
	71	}
	72	};
	73
	74	static const VMStateDescription vmstate_pl080 = {
	75	.name = "pl080",
	76	.version_id = 1,
	77	.minimum_version_id = 1,
	78	.fields = (VMStateField[]) {
d7ba0a62 AF	79	VMSTATE_UINT8(tc_int, PL080State),
	80	VMSTATE_UINT8(tc_mask, PL080State),
	81	VMSTATE_UINT8(err_int, PL080State),
	82	VMSTATE_UINT8(err_mask, PL080State),
	83	VMSTATE_UINT32(conf, PL080State),
	84	VMSTATE_UINT32(sync, PL080State),
	85	VMSTATE_UINT32(req_single, PL080State),
	86	VMSTATE_UINT32(req_burst, PL080State),
	87	VMSTATE_UINT8(tc_int, PL080State),
	88	VMSTATE_UINT8(tc_int, PL080State),
	89	VMSTATE_UINT8(tc_int, PL080State),
	90	VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
ff175853	91	1, vmstate_pl080_channel, pl080_channel),
d7ba0a62	92	VMSTATE_INT32(running, PL080State),
ff175853 PM	93	VMSTATE_END_OF_LIST()
	94	}
	95	};
	96
cdbdb648 PB	97	static const unsigned char pl080_id[] =
	98	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	99
e69954b9 PB	100	static const unsigned char pl081_id[] =
	101	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	102
d7ba0a62	103	static void pl080_update(PL080State *s)
cdbdb648 PB	104	{
	105	if ((s->tc_int & s->tc_mask)
	106	\|\| (s->err_int & s->err_mask))
d537cf6c	107	qemu_irq_raise(s->irq);
cdbdb648	108	else
d537cf6c	109	qemu_irq_lower(s->irq);
cdbdb648 PB	110	}
cdbdb648 PB	111
d7ba0a62	112	static void pl080_run(PL080State *s)
cdbdb648 PB	113	{
	114	int c;
	115	int flow;
	116	pl080_channel *ch;
	117	int swidth;
	118	int dwidth;
	119	int xsize;
	120	int n;
	121	int src_id;
	122	int dest_id;
	123	int size;
b55266b5	124	uint8_t buff[4];
cdbdb648 PB	125	uint32_t req;
	126
	127	s->tc_mask = 0;
e69954b9	128	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	129	if (s->chan[c].conf & PL080_CCONF_ITC)
	130	s->tc_mask \|= 1 << c;
	131	if (s->chan[c].conf & PL080_CCONF_IE)
	132	s->err_mask \|= 1 << c;
	133	}
	134
	135	if ((s->conf & PL080_CONF_E) == 0)
	136	return;
	137
2ac71179	138	hw_error("DMA active\n");
cdbdb648 PB	139	/* If we are already in the middle of a DMA operation then indicate that
	140	there may be new DMA requests and return immediately. */
	141	if (s->running) {
	142	s->running++;
	143	return;
	144	}
	145	s->running = 1;
	146	while (s->running) {
e69954b9	147	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	148	ch = &s->chan[c];
	149	again:
	150	/* Test if thiws channel has any pending DMA requests. */
	151	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	152	!= PL080_CCONF_E)
	153	continue;
	154	flow = (ch->conf >> 11) & 7;
	155	if (flow >= 4) {
2ac71179	156	hw_error(
cdbdb648 PB	157	"pl080_run: Peripheral flow control not implemented\n");
	158	}
	159	src_id = (ch->conf >> 1) & 0x1f;
	160	dest_id = (ch->conf >> 6) & 0x1f;
	161	size = ch->ctrl & 0xfff;
	162	req = s->req_single \| s->req_burst;
	163	switch (flow) {
	164	case 0:
	165	break;
	166	case 1:
	167	if ((req & (1u << dest_id)) == 0)
	168	size = 0;
	169	break;
	170	case 2:
	171	if ((req & (1u << src_id)) == 0)
	172	size = 0;
	173	break;
	174	case 3:
	175	if ((req & (1u << src_id)) == 0
	176	\|\| (req & (1u << dest_id)) == 0)
	177	size = 0;
	178	break;
	179	}
	180	if (!size)
	181	continue;
	182
	183	/* Transfer one element. */
	184	/* ??? Should transfer multiple elements for a burst request. */
	185	/* ??? Unclear what the proper behavior is when source and
	186	destination widths are different. */
	187	swidth = 1 << ((ch->ctrl >> 18) & 7);
	188	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	189	for (n = 0; n < dwidth; n+= swidth) {
	190	cpu_physical_memory_read(ch->src, buff + n, swidth);
	191	if (ch->ctrl & PL080_CCTRL_SI)
	192	ch->src += swidth;
	193	}
	194	xsize = (dwidth < swidth) ? swidth : dwidth;
	195	/* ??? This may pad the value incorrectly for dwidth < 32. */
	196	for (n = 0; n < xsize; n += dwidth) {
	197	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	198	if (ch->ctrl & PL080_CCTRL_DI)
	199	ch->dest += swidth;
	200	}
	201
	202	size--;
	203	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	204	if (size == 0) {
	205	/* Transfer complete. */
	206	if (ch->lli) {
75b0646f AG	207	ch->src = ldl_le_phys(ch->lli);
	208	ch->dest = ldl_le_phys(ch->lli + 4);
	209	ch->ctrl = ldl_le_phys(ch->lli + 12);
	210	ch->lli = ldl_le_phys(ch->lli + 8);
cdbdb648 PB	211	} else {
	212	ch->conf &= ~PL080_CCONF_E;
	213	}
	214	if (ch->ctrl & PL080_CCTRL_I) {
	215	s->tc_int \|= 1 << c;
	216	}
	217	}
	218	goto again;
	219	}
	220	if (--s->running)
	221	s->running = 1;
	222	}
	223	}
	224
a8170e5e	225	static uint64_t pl080_read(void *opaque, hwaddr offset,
63b02e04	226	unsigned size)
cdbdb648	227	{
d7ba0a62	228	PL080State s = (PL080State )opaque;
cdbdb648 PB	229	uint32_t i;
	230	uint32_t mask;
	231
cdbdb648	232	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	233	if (s->nchannels == 8) {
	234	return pl080_id[(offset - 0xfe0) >> 2];
	235	} else {
	236	return pl081_id[(offset - 0xfe0) >> 2];
	237	}
cdbdb648 PB	238	}
	239	if (offset >= 0x100 && offset < 0x200) {
	240	i = (offset & 0xe0) >> 5;
e69954b9 PB	241	if (i >= s->nchannels)
e69954b9 PB	242	goto bad_offset;
cdbdb648 PB	243	switch (offset >> 2) {
	244	case 0: /* SrcAddr */
	245	return s->chan[i].src;
	246	case 1: /* DestAddr */
	247	return s->chan[i].dest;
	248	case 2: /* LLI */
	249	return s->chan[i].lli;
	250	case 3: /* Control */
	251	return s->chan[i].ctrl;
	252	case 4: /* Configuration */
	253	return s->chan[i].conf;
	254	default:
	255	goto bad_offset;
	256	}
	257	}
	258	switch (offset >> 2) {
	259	case 0: /* IntStatus */
	260	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	261	case 1: /* IntTCStatus */
	262	return (s->tc_int & s->tc_mask);
	263	case 3: /* IntErrorStatus */
	264	return (s->err_int & s->err_mask);
	265	case 5: /* RawIntTCStatus */
	266	return s->tc_int;
	267	case 6: /* RawIntErrorStatus */
	268	return s->err_int;
	269	case 7: /* EnbldChns */
	270	mask = 0;
e69954b9	271	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	272	if (s->chan[i].conf & PL080_CCONF_E)
	273	mask \|= 1 << i;
	274	}
	275	return mask;
	276	case 8: /* SoftBReq */
	277	case 9: /* SoftSReq */
	278	case 10: /* SoftLBReq */
	279	case 11: /* SoftLSReq */
	280	/* ??? Implement these. */
	281	return 0;
	282	case 12: /* Configuration */
	283	return s->conf;
	284	case 13: /* Sync */
	285	return s->sync;
	286	default:
	287	bad_offset:
df374162 PM	288	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	289	"pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	290	return 0;
	291	}
	292	}
	293
a8170e5e	294	static void pl080_write(void *opaque, hwaddr offset,
63b02e04	295	uint64_t value, unsigned size)
cdbdb648	296	{
d7ba0a62	297	PL080State s = (PL080State )opaque;
cdbdb648 PB	298	int i;
cdbdb648 PB	299
cdbdb648 PB	300	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	301	i = (offset & 0xe0) >> 5;
e69954b9 PB	302	if (i >= s->nchannels)
e69954b9 PB	303	goto bad_offset;
cdbdb648 PB	304	switch (offset >> 2) {
	305	case 0: /* SrcAddr */
	306	s->chan[i].src = value;
	307	break;
	308	case 1: /* DestAddr */
	309	s->chan[i].dest = value;
	310	break;
	311	case 2: /* LLI */
	312	s->chan[i].lli = value;
	313	break;
	314	case 3: /* Control */
	315	s->chan[i].ctrl = value;
	316	break;
	317	case 4: /* Configuration */
	318	s->chan[i].conf = value;
	319	pl080_run(s);
	320	break;
	321	}
	322	}
	323	switch (offset >> 2) {
	324	case 2: /* IntTCClear */
	325	s->tc_int &= ~value;
	326	break;
	327	case 4: /* IntErrorClear */
	328	s->err_int &= ~value;
	329	break;
	330	case 8: /* SoftBReq */
	331	case 9: /* SoftSReq */
	332	case 10: /* SoftLBReq */
	333	case 11: /* SoftLSReq */
	334	/* ??? Implement these. */
df374162	335	qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	336	break;
	337	case 12: /* Configuration */
	338	s->conf = value;
	339	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M1)) {
df374162 PM	340	qemu_log_mask(LOG_UNIMP,
df374162 PM	341	"pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	342	}
	343	pl080_run(s);
	344	break;
	345	case 13: /* Sync */
	346	s->sync = value;
	347	break;
	348	default:
e69954b9	349	bad_offset:
df374162 PM	350	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	351	"pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	352	}
	353	pl080_update(s);
	354	}
	355
63b02e04 AK	356	static const MemoryRegionOps pl080_ops = {
	357	.read = pl080_read,
	358	.write = pl080_write,
	359	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	360	};
cdbdb648 PB	361
4f800554	362	static void pl080_init(Object *obj)
cdbdb648	363	{
4f800554 AF	364	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4f800554 AF	365	PL080State *s = PL080(obj);
cdbdb648	366
3eadad55	367	memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
4f800554 AF	368	sysbus_init_mmio(sbd, &s->iomem);
	369	sysbus_init_irq(sbd, &s->irq);
	370	s->nchannels = 8;
cdbdb648	371	}
b4496b13	372
4f800554	373	static void pl081_init(Object *obj)
b4496b13	374	{
4f800554	375	PL080State *s = PL080(obj);
b4496b13	376
4f800554	377	s->nchannels = 2;
b4496b13 PB	378	}
b4496b13 PB	379
4f800554	380	static void pl080_class_init(ObjectClass oc, void data)
999e12bb	381	{
4f800554	382	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	383
39bffca2 AL	384	dc->no_user = 1;
39bffca2 AL	385	dc->vmsd = &vmstate_pl080;
999e12bb AL	386	}
999e12bb AL	387
8c43a6f0	388	static const TypeInfo pl080_info = {
4f800554	389	.name = TYPE_PL080,
39bffca2	390	.parent = TYPE_SYS_BUS_DEVICE,
d7ba0a62	391	.instance_size = sizeof(PL080State),
4f800554	392	.instance_init = pl080_init,
39bffca2	393	.class_init = pl080_class_init,
ff175853 PM	394	};
ff175853 PM	395
8c43a6f0	396	static const TypeInfo pl081_info = {
39bffca2	397	.name = "pl081",
4f800554 AF	398	.parent = TYPE_PL080,
4f800554 AF	399	.instance_init = pl081_init,
ff175853 PM	400	};
ff175853 PM	401
b4496b13 PB	402	/* The PL080 and PL081 are the same except for the number of channels
b4496b13 PB	403	they implement (8 and 2 respectively). */
83f7d43a	404	static void pl080_register_types(void)
b4496b13	405	{
39bffca2 AL	406	type_register_static(&pl080_info);
39bffca2 AL	407	type_register_static(&pl081_info);
b4496b13 PB	408	}
b4496b13 PB	409
83f7d43a	410	type_init(pl080_register_types)