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target-tricore: Add instructions of SLR, SSRO and SRO opcode format
[qemu.git] / target-tricore / op_helper.c
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48e06fe0
BK		 1/*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17#include <stdlib.h>
18#include "cpu.h"
19#include "qemu/host-utils.h"
20#include "exec/helper-proto.h"
21#include "exec/cpu_ldst.h"
22
2692802a
BK		 23#define SSOV(env, ret, arg, len) do { \
24 int64_t max_pos = INT##len ##_MAX; \
25 int64_t max_neg = INT##len ##_MIN; \
26 if (arg > max_pos) { \
27 env->PSW_USB_V = (1 << 31); \
28 env->PSW_USB_SV = (1 << 31); \
29 ret = (target_ulong)max_pos; \
30 } else { \
31 if (arg < max_neg) { \
32 env->PSW_USB_V = (1 << 31); \
33 env->PSW_USB_SV = (1 << 31); \
34 ret = (target_ulong)max_neg; \
35 } else { \
36 env->PSW_USB_V = 0; \
37 ret = (target_ulong)arg; \
38 } \
39 } \
40 env->PSW_USB_AV = arg ^ arg * 2u; \
41 env->PSW_USB_SAV |= env->PSW_USB_AV; \
42} while (0)
43
44target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
45 target_ulong r2)
46{
47 target_ulong ret;
48 int64_t t1 = sextract64(r1, 0, 32);
49 int64_t t2 = sextract64(r2, 0, 32);
50 int64_t result = t1 + t2;
51 SSOV(env, ret, result, 32);
52 return ret;
53}
54
55target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
56 target_ulong r2)
57{
58 target_ulong ret;
59 int64_t t1 = sextract64(r1, 0, 32);
60 int64_t t2 = sextract64(r2, 0, 32);
61 int64_t result = t1 - t2;
62 SSOV(env, ret, result, 32);
63 return ret;
64}
65
9a31922b
BK		 66/* context save area (CSA) related helpers */
67
68static int cdc_increment(target_ulong *psw)
69{
70 if ((*psw & MASK_PSW_CDC) == 0x7f) {
71 return 0;
72 }
73
74 (*psw)++;
75 /* check for overflow */
76 int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
77 int mask = (1u << (7 - lo)) - 1;
78 int count = *psw & mask;
79 if (count == 0) {
80 (*psw)--;
81 return 1;
82 }
83 return 0;
84}
85
86static int cdc_decrement(target_ulong *psw)
87{
88 if ((*psw & MASK_PSW_CDC) == 0x7f) {
89 return 0;
90 }
91 /* check for underflow */
92 int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
93 int mask = (1u << (7 - lo)) - 1;
94 int count = *psw & mask;
95 if (count == 0) {
96 return 1;
97 }
98 (*psw)--;
99 return 0;
100}
101
102static void save_context_upper(CPUTriCoreState *env, int ea,
103 target_ulong *new_FCX)
104{
105 *new_FCX = cpu_ldl_data(env, ea);
106 cpu_stl_data(env, ea, env->PCXI);
107 cpu_stl_data(env, ea+4, env->PSW);
108 cpu_stl_data(env, ea+8, env->gpr_a[10]);
109 cpu_stl_data(env, ea+12, env->gpr_a[11]);
110 cpu_stl_data(env, ea+16, env->gpr_d[8]);
111 cpu_stl_data(env, ea+20, env->gpr_d[9]);
112 cpu_stl_data(env, ea+24, env->gpr_d[10]);
113 cpu_stl_data(env, ea+28, env->gpr_d[11]);
114 cpu_stl_data(env, ea+32, env->gpr_a[12]);
115 cpu_stl_data(env, ea+36, env->gpr_a[13]);
116 cpu_stl_data(env, ea+40, env->gpr_a[14]);
117 cpu_stl_data(env, ea+44, env->gpr_a[15]);
118 cpu_stl_data(env, ea+48, env->gpr_d[12]);
119 cpu_stl_data(env, ea+52, env->gpr_d[13]);
120 cpu_stl_data(env, ea+56, env->gpr_d[14]);
121 cpu_stl_data(env, ea+60, env->gpr_d[15]);
122
123}
124
5de93515
BK		 125static void save_context_lower(CPUTriCoreState *env, int ea,
126 target_ulong *new_FCX)
127{
128 *new_FCX = cpu_ldl_data(env, ea);
129 cpu_stl_data(env, ea, env->PCXI);
130 cpu_stl_data(env, ea+4, env->PSW);
131 cpu_stl_data(env, ea+8, env->gpr_a[2]);
132 cpu_stl_data(env, ea+12, env->gpr_a[3]);
133 cpu_stl_data(env, ea+16, env->gpr_d[0]);
134 cpu_stl_data(env, ea+20, env->gpr_d[1]);
135 cpu_stl_data(env, ea+24, env->gpr_d[2]);
136 cpu_stl_data(env, ea+28, env->gpr_d[3]);
137 cpu_stl_data(env, ea+32, env->gpr_a[4]);
138 cpu_stl_data(env, ea+36, env->gpr_a[5]);
139 cpu_stl_data(env, ea+40, env->gpr_a[6]);
140 cpu_stl_data(env, ea+44, env->gpr_a[7]);
141 cpu_stl_data(env, ea+48, env->gpr_d[4]);
142 cpu_stl_data(env, ea+52, env->gpr_d[5]);
143 cpu_stl_data(env, ea+56, env->gpr_d[6]);
144 cpu_stl_data(env, ea+60, env->gpr_d[7]);
145}
146
9a31922b
BK		 147static void restore_context_upper(CPUTriCoreState *env, int ea,
148 target_ulong *new_PCXI, target_ulong *new_PSW)
149{
150 *new_PCXI = cpu_ldl_data(env, ea);
151 *new_PSW = cpu_ldl_data(env, ea+4);
152 env->gpr_a[10] = cpu_ldl_data(env, ea+8);
153 env->gpr_a[11] = cpu_ldl_data(env, ea+12);
154 env->gpr_d[8] = cpu_ldl_data(env, ea+16);
155 env->gpr_d[9] = cpu_ldl_data(env, ea+20);
156 env->gpr_d[10] = cpu_ldl_data(env, ea+24);
157 env->gpr_d[11] = cpu_ldl_data(env, ea+28);
158 env->gpr_a[12] = cpu_ldl_data(env, ea+32);
159 env->gpr_a[13] = cpu_ldl_data(env, ea+36);
160 env->gpr_a[14] = cpu_ldl_data(env, ea+40);
161 env->gpr_a[15] = cpu_ldl_data(env, ea+44);
162 env->gpr_d[12] = cpu_ldl_data(env, ea+48);
163 env->gpr_d[13] = cpu_ldl_data(env, ea+52);
164 env->gpr_d[14] = cpu_ldl_data(env, ea+56);
165 env->gpr_d[15] = cpu_ldl_data(env, ea+60);
166 cpu_stl_data(env, ea, env->FCX);
167}
168
169void helper_call(CPUTriCoreState *env, uint32_t next_pc)
170{
171 target_ulong tmp_FCX;
172 target_ulong ea;
173 target_ulong new_FCX;
174 target_ulong psw;
175
176 psw = psw_read(env);
177 /* if (FCX == 0) trap(FCU); */
178 if (env->FCX == 0) {
179 /* FCU trap */
180 }
181 /* if (PSW.CDE) then if (cdc_increment()) then trap(CDO); */
182 if (psw & MASK_PSW_CDE) {
183 if (cdc_increment(&psw)) {
184 /* CDO trap */
185 }
186 }
187 /* PSW.CDE = 1;*/
188 psw |= MASK_PSW_CDE;
189 /* tmp_FCX = FCX; */
190 tmp_FCX = env->FCX;
191 /* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
192 ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
193 ((env->FCX & MASK_FCX_FCXO) << 6);
194 /* new_FCX = M(EA, word);
195 M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
196 A[12], A[13], A[14], A[15], D[12], D[13], D[14],
197 D[15]}; */
198 save_context_upper(env, ea, &new_FCX);
199
200 /* PCXI.PCPN = ICR.CCPN; */
201 env->PCXI = (env->PCXI & 0xffffff) +
202 ((env->ICR & MASK_ICR_CCPN) << 24);
203 /* PCXI.PIE = ICR.IE; */
204 env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
205 ((env->ICR & MASK_ICR_IE) << 15));
206 /* PCXI.UL = 1; */
207 env->PCXI |= MASK_PCXI_UL;
208
209 /* PCXI[19: 0] = FCX[19: 0]; */
210 env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
211 /* FCX[19: 0] = new_FCX[19: 0]; */
212 env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
213 /* A[11] = next_pc[31: 0]; */
214 env->gpr_a[11] = next_pc;
215
216 /* if (tmp_FCX == LCX) trap(FCD);*/
217 if (tmp_FCX == env->LCX) {
218 /* FCD trap */
219 }
220 psw_write(env, psw);
221}
222
223void helper_ret(CPUTriCoreState *env)
224{
225 target_ulong ea;
226 target_ulong new_PCXI;
227 target_ulong new_PSW, psw;
228
229 psw = psw_read(env);
230 /* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
231 if (env->PSW & MASK_PSW_CDE) {
232 if (cdc_decrement(&(env->PSW))) {
233 /* CDU trap */
234 }
235 }
236 /* if (PCXI[19: 0] == 0) then trap(CSU); */
237 if ((env->PCXI & 0xfffff) == 0) {
238 /* CSU trap */
239 }
240 /* if (PCXI.UL == 0) then trap(CTYP); */
241 if ((env->PCXI & MASK_PCXI_UL) == 0) {
242 /* CTYP trap */
243 }
244 /* PC = {A11 [31: 1], 1’b0}; */
245 env->PC = env->gpr_a[11] & 0xfffffffe;
246
247 /* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
248 ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
249 ((env->PCXI & MASK_PCXI_PCXO) << 6);
250 /* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
251 A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word);
252 M(EA, word) = FCX; */
253 restore_context_upper(env, ea, &new_PCXI, &new_PSW);
254 /* FCX[19: 0] = PCXI[19: 0]; */
255 env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
256 /* PCXI = new_PCXI; */
257 env->PCXI = new_PCXI;
258
259 if (tricore_feature(env, TRICORE_FEATURE_13)) {
260 /* PSW = new_PSW */
261 psw_write(env, new_PSW);
262 } else {
263 /* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
264 psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
265 }
266}
267
5de93515
BK		 268void helper_bisr(CPUTriCoreState *env, uint32_t const9)
269{
270 target_ulong tmp_FCX;
271 target_ulong ea;
272 target_ulong new_FCX;
273
274 if (env->FCX == 0) {
275 /* FCU trap */
276 }
277
278 tmp_FCX = env->FCX;
279 ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);
280
281 save_context_lower(env, ea, &new_FCX);
282
283 /* PCXI.PCPN = ICR.CCPN */
284 env->PCXI = (env->PCXI & 0xffffff) +
285 ((env->ICR & MASK_ICR_CCPN) << 24);
286 /* PCXI.PIE = ICR.IE */
287 env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
288 ((env->ICR & MASK_ICR_IE) << 15));
289 /* PCXI.UL = 0 */
290 env->PCXI &= ~(MASK_PCXI_UL);
291 /* PCXI[19: 0] = FCX[19: 0] */
292 env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
293 /* FXC[19: 0] = new_FCX[19: 0] */
294 env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
295 /* ICR.IE = 1 */
296 env->ICR |= MASK_ICR_IE;
297
298 env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
299
300 if (tmp_FCX == env->LCX) {
301 /* FCD trap */
302 }
303}
304
2d30267e
BK		 305static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
306 uint32_t exception,
307 int error_code,
308 uintptr_t pc)
309{
310 CPUState *cs = CPU(tricore_env_get_cpu(env));
311 cs->exception_index = exception;
312 env->error_code = error_code;
313
314 if (pc) {
315 /* now we have a real cpu fault */
316 cpu_restore_state(cs, pc);
317 }
318
319 cpu_loop_exit(cs);
320}
321
322static inline void QEMU_NORETURN do_raise_exception(CPUTriCoreState *env,
323 uint32_t exception,
324 uintptr_t pc)
325{
326 do_raise_exception_err(env, exception, 0, pc);
327}
328
48e06fe0
BK		 329void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
330 uintptr_t retaddr)
331{
2d30267e
BK		 332 int ret;
333 ret = cpu_tricore_handle_mmu_fault(cs, addr, is_write, mmu_idx);
334 if (ret) {
335 TriCoreCPU *cpu = TRICORE_CPU(cs);
336 CPUTriCoreState *env = &cpu->env;
337 do_raise_exception_err(env, cs->exception_index,
338 env->error_code, retaddr);
339 }
48e06fe0 340}
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