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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef SUN4M_H |
2 | #define SUN4M_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
87ecb68b PB |
6 | /* Devices used by sparc32 system. */ |
7 | ||
8 | /* iommu.c */ | |
ff403da6 | 9 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq); |
87ecb68b PB |
10 | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
11 | uint8_t *buf, int len, int is_write); | |
12 | static inline void sparc_iommu_memory_read(void *opaque, | |
13 | target_phys_addr_t addr, | |
14 | uint8_t *buf, int len) | |
15 | { | |
16 | sparc_iommu_memory_rw(opaque, addr, buf, len, 0); | |
17 | } | |
18 | ||
19 | static inline void sparc_iommu_memory_write(void *opaque, | |
20 | target_phys_addr_t addr, | |
21 | uint8_t *buf, int len) | |
22 | { | |
23 | sparc_iommu_memory_rw(opaque, addr, buf, len, 1); | |
24 | } | |
25 | ||
26 | /* tcx.c */ | |
dc828ca1 | 27 | void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height, |
87ecb68b PB |
28 | int depth); |
29 | ||
30 | /* slavio_intctl.c */ | |
31 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, | |
32 | const uint32_t *intbit_to_level, | |
33 | qemu_irq **irq, qemu_irq **cpu_irq, | |
34 | qemu_irq **parent_irq, unsigned int cputimer); | |
376253ec AL |
35 | void slavio_pic_info(Monitor *mon, void *opaque); |
36 | void slavio_irq_info(Monitor *mon, void *opaque); | |
87ecb68b | 37 | |
7d85892b BS |
38 | /* sbi.c */ |
39 | void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, | |
40 | qemu_irq **parent_irq); | |
41 | ||
ee76f82e BS |
42 | /* sun4c_intctl.c */ |
43 | void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, | |
44 | qemu_irq *parent_irq); | |
376253ec AL |
45 | void sun4c_pic_info(Monitor *mon, void *opaque); |
46 | void sun4c_irq_info(Monitor *mon, void *opaque); | |
ee76f82e | 47 | |
87ecb68b PB |
48 | /* slavio_timer.c */ |
49 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, | |
19f8e5dd | 50 | qemu_irq *cpu_irqs, unsigned int num_cpus); |
87ecb68b | 51 | |
87ecb68b PB |
52 | /* slavio_misc.c */ |
53 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, | |
0019ad53 BS |
54 | target_phys_addr_t aux1_base, |
55 | target_phys_addr_t aux2_base, qemu_irq irq, | |
6d0c293d | 56 | qemu_irq cpu_halt, qemu_irq **fdc_tc); |
87ecb68b PB |
57 | void slavio_set_power_fail(void *opaque, int power_failing); |
58 | ||
87ecb68b PB |
59 | /* cs4231.c */ |
60 | void cs_init(target_phys_addr_t base, int irq, void *intctl); | |
61 | ||
62 | /* sparc32_dma.c */ | |
216fdffa | 63 | #include "sparc32_dma.h" |
87ecb68b | 64 | |
7eb0c8e8 | 65 | /* eccmemctl.c */ |
e42c20b4 | 66 | void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version); |
7eb0c8e8 | 67 | |
87ecb68b | 68 | #endif |