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Don't define HIGH_LATENCY for ARM, this was a workaround for an ALSA problem.
[qemu.git] / target-sparc / op.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC micro operations
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
5
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
10
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
15
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include "exec.h"
22
cf495bcf 23 /*XXX*/
7a3f1944
FB		 24#define REGNAME g0
25#define REG (env->gregs[0])
26#include "op_template.h"
27#define REGNAME g1
28#define REG (env->gregs[1])
29#include "op_template.h"
30#define REGNAME g2
31#define REG (env->gregs[2])
32#include "op_template.h"
33#define REGNAME g3
34#define REG (env->gregs[3])
35#include "op_template.h"
36#define REGNAME g4
37#define REG (env->gregs[4])
38#include "op_template.h"
39#define REGNAME g5
40#define REG (env->gregs[5])
41#include "op_template.h"
42#define REGNAME g6
43#define REG (env->gregs[6])
44#include "op_template.h"
45#define REGNAME g7
46#define REG (env->gregs[7])
47#include "op_template.h"
48#define REGNAME i0
3475187d 49#define REG (REGWPTR[16])
7a3f1944
FB		 50#include "op_template.h"
51#define REGNAME i1
3475187d 52#define REG (REGWPTR[17])
7a3f1944
FB		 53#include "op_template.h"
54#define REGNAME i2
3475187d 55#define REG (REGWPTR[18])
7a3f1944
FB		 56#include "op_template.h"
57#define REGNAME i3
3475187d 58#define REG (REGWPTR[19])
7a3f1944
FB		 59#include "op_template.h"
60#define REGNAME i4
3475187d 61#define REG (REGWPTR[20])
7a3f1944
FB		 62#include "op_template.h"
63#define REGNAME i5
3475187d 64#define REG (REGWPTR[21])
7a3f1944
FB		 65#include "op_template.h"
66#define REGNAME i6
3475187d 67#define REG (REGWPTR[22])
7a3f1944
FB		 68#include "op_template.h"
69#define REGNAME i7
3475187d 70#define REG (REGWPTR[23])
7a3f1944
FB		 71#include "op_template.h"
72#define REGNAME l0
3475187d 73#define REG (REGWPTR[8])
7a3f1944
FB		 74#include "op_template.h"
75#define REGNAME l1
3475187d 76#define REG (REGWPTR[9])
7a3f1944
FB		 77#include "op_template.h"
78#define REGNAME l2
3475187d 79#define REG (REGWPTR[10])
7a3f1944
FB		 80#include "op_template.h"
81#define REGNAME l3
3475187d 82#define REG (REGWPTR[11])
7a3f1944
FB		 83#include "op_template.h"
84#define REGNAME l4
3475187d 85#define REG (REGWPTR[12])
7a3f1944
FB		 86#include "op_template.h"
87#define REGNAME l5
3475187d 88#define REG (REGWPTR[13])
7a3f1944
FB		 89#include "op_template.h"
90#define REGNAME l6
3475187d 91#define REG (REGWPTR[14])
7a3f1944
FB		 92#include "op_template.h"
93#define REGNAME l7
3475187d 94#define REG (REGWPTR[15])
7a3f1944
FB		 95#include "op_template.h"
96#define REGNAME o0
3475187d 97#define REG (REGWPTR[0])
7a3f1944
FB		 98#include "op_template.h"
99#define REGNAME o1
3475187d 100#define REG (REGWPTR[1])
7a3f1944
FB		 101#include "op_template.h"
102#define REGNAME o2
3475187d 103#define REG (REGWPTR[2])
7a3f1944
FB		 104#include "op_template.h"
105#define REGNAME o3
3475187d 106#define REG (REGWPTR[3])
7a3f1944
FB		 107#include "op_template.h"
108#define REGNAME o4
3475187d 109#define REG (REGWPTR[4])
7a3f1944
FB		 110#include "op_template.h"
111#define REGNAME o5
3475187d 112#define REG (REGWPTR[5])
7a3f1944
FB		 113#include "op_template.h"
114#define REGNAME o6
3475187d 115#define REG (REGWPTR[6])
7a3f1944
FB		 116#include "op_template.h"
117#define REGNAME o7
3475187d 118#define REG (REGWPTR[7])
7a3f1944 119#include "op_template.h"
e8af50a3
FB		 120
121#define REGNAME f0
122#define REG (env->fpr[0])
123#include "fop_template.h"
124#define REGNAME f1
125#define REG (env->fpr[1])
126#include "fop_template.h"
127#define REGNAME f2
128#define REG (env->fpr[2])
129#include "fop_template.h"
130#define REGNAME f3
131#define REG (env->fpr[3])
132#include "fop_template.h"
133#define REGNAME f4
134#define REG (env->fpr[4])
135#include "fop_template.h"
136#define REGNAME f5
137#define REG (env->fpr[5])
138#include "fop_template.h"
139#define REGNAME f6
140#define REG (env->fpr[6])
141#include "fop_template.h"
142#define REGNAME f7
143#define REG (env->fpr[7])
144#include "fop_template.h"
145#define REGNAME f8
146#define REG (env->fpr[8])
147#include "fop_template.h"
148#define REGNAME f9
149#define REG (env->fpr[9])
150#include "fop_template.h"
151#define REGNAME f10
152#define REG (env->fpr[10])
153#include "fop_template.h"
154#define REGNAME f11
155#define REG (env->fpr[11])
156#include "fop_template.h"
157#define REGNAME f12
158#define REG (env->fpr[12])
159#include "fop_template.h"
160#define REGNAME f13
161#define REG (env->fpr[13])
162#include "fop_template.h"
163#define REGNAME f14
164#define REG (env->fpr[14])
165#include "fop_template.h"
166#define REGNAME f15
167#define REG (env->fpr[15])
168#include "fop_template.h"
169#define REGNAME f16
170#define REG (env->fpr[16])
171#include "fop_template.h"
172#define REGNAME f17
173#define REG (env->fpr[17])
174#include "fop_template.h"
175#define REGNAME f18
176#define REG (env->fpr[18])
177#include "fop_template.h"
178#define REGNAME f19
179#define REG (env->fpr[19])
180#include "fop_template.h"
181#define REGNAME f20
182#define REG (env->fpr[20])
183#include "fop_template.h"
184#define REGNAME f21
185#define REG (env->fpr[21])
186#include "fop_template.h"
187#define REGNAME f22
188#define REG (env->fpr[22])
189#include "fop_template.h"
190#define REGNAME f23
191#define REG (env->fpr[23])
192#include "fop_template.h"
193#define REGNAME f24
194#define REG (env->fpr[24])
195#include "fop_template.h"
196#define REGNAME f25
197#define REG (env->fpr[25])
198#include "fop_template.h"
199#define REGNAME f26
200#define REG (env->fpr[26])
201#include "fop_template.h"
202#define REGNAME f27
203#define REG (env->fpr[27])
204#include "fop_template.h"
205#define REGNAME f28
206#define REG (env->fpr[28])
207#include "fop_template.h"
208#define REGNAME f29
209#define REG (env->fpr[29])
210#include "fop_template.h"
211#define REGNAME f30
212#define REG (env->fpr[30])
213#include "fop_template.h"
214#define REGNAME f31
215#define REG (env->fpr[31])
216#include "fop_template.h"
217
3475187d
FB		 218#ifdef TARGET_SPARC64
219#define REGNAME f32
220#define REG (env->fpr[32])
221#include "fop_template.h"
222#define REGNAME f34
223#define REG (env->fpr[34])
224#include "fop_template.h"
225#define REGNAME f36
226#define REG (env->fpr[36])
227#include "fop_template.h"
228#define REGNAME f38
229#define REG (env->fpr[38])
230#include "fop_template.h"
231#define REGNAME f40
232#define REG (env->fpr[40])
233#include "fop_template.h"
234#define REGNAME f42
235#define REG (env->fpr[42])
236#include "fop_template.h"
237#define REGNAME f44
238#define REG (env->fpr[44])
239#include "fop_template.h"
240#define REGNAME f46
241#define REG (env->fpr[46])
242#include "fop_template.h"
243#define REGNAME f48
244#define REG (env->fpr[47])
245#include "fop_template.h"
246#define REGNAME f50
247#define REG (env->fpr[50])
248#include "fop_template.h"
249#define REGNAME f52
250#define REG (env->fpr[52])
251#include "fop_template.h"
252#define REGNAME f54
253#define REG (env->fpr[54])
254#include "fop_template.h"
255#define REGNAME f56
256#define REG (env->fpr[56])
257#include "fop_template.h"
258#define REGNAME f58
259#define REG (env->fpr[58])
260#include "fop_template.h"
261#define REGNAME f60
262#define REG (env->fpr[60])
263#include "fop_template.h"
264#define REGNAME f62
265#define REG (env->fpr[62])
266#include "fop_template.h"
267#endif
268
269#ifdef TARGET_SPARC64
3475187d
FB		 270#ifdef WORDS_BIGENDIAN
271typedef union UREG64 {
272 struct { uint16_t v3, v2, v1, v0; } w;
273 struct { uint32_t v1, v0; } l;
274 uint64_t q;
275} UREG64;
276#else
277typedef union UREG64 {
278 struct { uint16_t v0, v1, v2, v3; } w;
279 struct { uint32_t v0, v1; } l;
280 uint64_t q;
281} UREG64;
282#endif
283
284#define PARAMQ1 \
285({\
286 UREG64 __p;\
287 __p.l.v1 = PARAM1;\
288 __p.l.v0 = PARAM2;\
289 __p.q;\
290})
291
292void OPPROTO op_movq_T0_im64(void)
293{
294 T0 = PARAMQ1;
295}
296
297void OPPROTO op_movq_T1_im64(void)
298{
299 T1 = PARAMQ1;
300}
301
302#define XFLAG_SET(x) ((env->xcc&x)?1:0)
303
304#else
7a3f1944 305#define EIP (env->pc)
3475187d 306#endif
7a3f1944 307
af7bf89b 308#define FLAG_SET(x) ((env->psr&x)?1:0)
cf495bcf 309
7a3f1944
FB		 310void OPPROTO op_movl_T0_0(void)
311{
cf495bcf 312 T0 = 0;
7a3f1944
FB		 313}
314
7a3f1944
FB		 315void OPPROTO op_movl_T0_im(void)
316{
3475187d 317 T0 = (uint32_t)PARAM1;
7a3f1944
FB		 318}
319
320void OPPROTO op_movl_T1_im(void)
321{
3475187d 322 T1 = (uint32_t)PARAM1;
7a3f1944
FB		 323}
324
325void OPPROTO op_movl_T2_im(void)
326{
3475187d
FB		 327 T2 = (uint32_t)PARAM1;
328}
329
330void OPPROTO op_movl_T0_sim(void)
331{
332 T0 = (int32_t)PARAM1;
333}
334
335void OPPROTO op_movl_T1_sim(void)
336{
337 T1 = (int32_t)PARAM1;
338}
339
340void OPPROTO op_movl_T2_sim(void)
341{
342 T2 = (int32_t)PARAM1;
343}
344
345void OPPROTO op_movl_T0_env(void)
346{
347 T0 = *(uint32_t *)((char *)env + PARAM1);
348}
349
350void OPPROTO op_movl_env_T0(void)
351{
352 *(uint32_t *)((char *)env + PARAM1) = T0;
353}
354
355void OPPROTO op_movtl_T0_env(void)
356{
357 T0 = *(target_ulong *)((char *)env + PARAM1);
358}
359
360void OPPROTO op_movtl_env_T0(void)
361{
362 *(target_ulong *)((char *)env + PARAM1) = T0;
7a3f1944
FB		 363}
364
af7bf89b 365void OPPROTO op_add_T1_T0(void)
7a3f1944 366{
af7bf89b 367 T0 += T1;
7a3f1944
FB		 368}
369
af7bf89b 370void OPPROTO op_add_T1_T0_cc(void)
7a3f1944 371{
af7bf89b 372 target_ulong src1;
7a3f1944 373
af7bf89b
FB		 374 src1 = T0;
375 T0 += T1;
376 env->psr = 0;
3475187d
FB		 377#ifdef TARGET_SPARC64
378 if (!(T0 & 0xffffffff))
379 env->psr |= PSR_ZERO;
380 if ((int32_t) T0 < 0)
381 env->psr |= PSR_NEG;
bb3911a6 382 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
3475187d
FB		 383 env->psr |= PSR_CARRY;
384 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
385 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
386 env->psr |= PSR_OVF;
387
388 env->xcc = 0;
389 if (!T0)
390 env->xcc |= PSR_ZERO;
391 if ((int64_t) T0 < 0)
392 env->xcc |= PSR_NEG;
393 if (T0 < src1)
394 env->xcc |= PSR_CARRY;
395 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
396 env->xcc |= PSR_OVF;
397#else
af7bf89b
FB		 398 if (!T0)
399 env->psr |= PSR_ZERO;
400 if ((int32_t) T0 < 0)
401 env->psr |= PSR_NEG;
402 if (T0 < src1)
403 env->psr |= PSR_CARRY;
404 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
405 env->psr |= PSR_OVF;
3475187d 406#endif
af7bf89b 407 FORCE_RET();
7a3f1944
FB		 408}
409
af7bf89b 410void OPPROTO op_addx_T1_T0(void)
7a3f1944 411{
af7bf89b 412 T0 += T1 + FLAG_SET(PSR_CARRY);
7a3f1944
FB		 413}
414
af7bf89b 415void OPPROTO op_addx_T1_T0_cc(void)
7a3f1944 416{
af7bf89b 417 target_ulong src1;
cf495bcf 418 src1 = T0;
b854608e
FB		 419 if (FLAG_SET(PSR_CARRY))
420 {
421 T0 += T1 + 1;
422 env->psr = 0;
423#ifdef TARGET_SPARC64
424 if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
425 env->psr |= PSR_CARRY;
426 env->xcc = 0;
427 if (T0 <= src1)
428 env->xcc |= PSR_CARRY;
429#else
430 if (T0 <= src1)
431 env->psr |= PSR_CARRY;
432#endif
433 }
434 else
435 {
436 T0 += T1;
437 env->psr = 0;
438#ifdef TARGET_SPARC64
439 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
440 env->psr |= PSR_CARRY;
441 env->xcc = 0;
442 if (T0 < src1)
443 env->xcc |= PSR_CARRY;
444#else
445 if (T0 < src1)
446 env->psr |= PSR_CARRY;
447#endif
448 }
3475187d
FB		 449#ifdef TARGET_SPARC64
450 if (!(T0 & 0xffffffff))
451 env->psr |= PSR_ZERO;
452 if ((int32_t) T0 < 0)
453 env->psr |= PSR_NEG;
3475187d
FB		 454 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
455 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
456 env->psr |= PSR_OVF;
457
3475187d
FB		 458 if (!T0)
459 env->xcc |= PSR_ZERO;
460 if ((int64_t) T0 < 0)
461 env->xcc |= PSR_NEG;
3475187d
FB		 462 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
463 env->xcc |= PSR_OVF;
464#else
cf495bcf
FB		 465 if (!T0)
466 env->psr |= PSR_ZERO;
af7bf89b 467 if ((int32_t) T0 < 0)
cf495bcf 468 env->psr |= PSR_NEG;
cf495bcf
FB		 469 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
470 env->psr |= PSR_OVF;
3475187d 471#endif
cf495bcf 472 FORCE_RET();
7a3f1944
FB		 473}
474
e32f879d
BS		 475void OPPROTO op_tadd_T1_T0_cc(void)
476{
477 target_ulong src1;
478
479 src1 = T0;
480 T0 += T1;
481 env->psr = 0;
482#ifdef TARGET_SPARC64
483 if (!(T0 & 0xffffffff))
484 env->psr |= PSR_ZERO;
485 if ((int32_t) T0 < 0)
486 env->psr |= PSR_NEG;
487 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
488 env->psr |= PSR_CARRY;
489 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
490 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
491 env->psr |= PSR_OVF;
492 if ((src1 & 0x03) || (T1 & 0x03))
493 env->psr |= PSR_OVF;
494
495 env->xcc = 0;
496 if (!T0)
497 env->xcc |= PSR_ZERO;
498 if ((int64_t) T0 < 0)
499 env->xcc |= PSR_NEG;
500 if (T0 < src1)
501 env->xcc |= PSR_CARRY;
502 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
503 env->xcc |= PSR_OVF;
504#else
505 if (!T0)
506 env->psr |= PSR_ZERO;
507 if ((int32_t) T0 < 0)
508 env->psr |= PSR_NEG;
509 if (T0 < src1)
510 env->psr |= PSR_CARRY;
511 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
512 env->psr |= PSR_OVF;
513 if ((src1 & 0x03) || (T1 & 0x03))
514 env->psr |= PSR_OVF;
515#endif
516 FORCE_RET();
517}
518
519void OPPROTO op_tadd_T1_T0_ccTV(void)
520{
521 target_ulong src1;
522
523 if ((T0 & 0x03) || (T1 & 0x03))
524 raise_exception(TT_TOVF);
525
526 src1 = T0;
527 T0 += T1;
528
529#ifdef TARGET_SPARC64
530 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
531 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
532 raise_exception(TT_TOVF);
533#else
534 if ((src1 & 0x03) || (T1 & 0x03))
535 raise_exception(TT_TOVF);
536#endif
537
538 env->psr = 0;
539#ifdef TARGET_SPARC64
540 if (!(T0 & 0xffffffff))
541 env->psr |= PSR_ZERO;
542 if ((int32_t) T0 < 0)
543 env->psr |= PSR_NEG;
544 if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
545 env->psr |= PSR_CARRY;
546
547 env->xcc = 0;
548 if (!T0)
549 env->xcc |= PSR_ZERO;
550 if ((int64_t) T0 < 0)
551 env->xcc |= PSR_NEG;
552 if (T0 < src1)
553 env->xcc |= PSR_CARRY;
554#else
555 if (!T0)
556 env->psr |= PSR_ZERO;
557 if ((int32_t) T0 < 0)
558 env->psr |= PSR_NEG;
559 if (T0 < src1)
560 env->psr |= PSR_CARRY;
561#endif
562 FORCE_RET();
563}
564
cf495bcf 565void OPPROTO op_sub_T1_T0(void)
7a3f1944 566{
cf495bcf 567 T0 -= T1;
7a3f1944
FB		 568}
569
cf495bcf 570void OPPROTO op_sub_T1_T0_cc(void)
7a3f1944 571{
af7bf89b 572 target_ulong src1;
cf495bcf
FB		 573
574 src1 = T0;
575 T0 -= T1;
576 env->psr = 0;
3475187d
FB		 577#ifdef TARGET_SPARC64
578 if (!(T0 & 0xffffffff))
579 env->psr |= PSR_ZERO;
580 if ((int32_t) T0 < 0)
581 env->psr |= PSR_NEG;
83469015 582 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
3475187d
FB		 583 env->psr |= PSR_CARRY;
584 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
585 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
586 env->psr |= PSR_OVF;
587
588 env->xcc = 0;
589 if (!T0)
590 env->xcc |= PSR_ZERO;
591 if ((int64_t) T0 < 0)
592 env->xcc |= PSR_NEG;
bb3911a6 593 if (src1 < T1)
3475187d
FB		 594 env->xcc |= PSR_CARRY;
595 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
596 env->xcc |= PSR_OVF;
597#else
cf495bcf
FB		 598 if (!T0)
599 env->psr |= PSR_ZERO;
af7bf89b 600 if ((int32_t) T0 < 0)
cf495bcf
FB		 601 env->psr |= PSR_NEG;
602 if (src1 < T1)
603 env->psr |= PSR_CARRY;
604 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
605 env->psr |= PSR_OVF;
3475187d 606#endif
af7bf89b
FB		 607 FORCE_RET();
608}
609
610void OPPROTO op_subx_T1_T0(void)
611{
612 T0 -= T1 + FLAG_SET(PSR_CARRY);
613}
614
615void OPPROTO op_subx_T1_T0_cc(void)
616{
617 target_ulong src1;
af7bf89b 618 src1 = T0;
b854608e
FB		 619 if (FLAG_SET(PSR_CARRY))
620 {
621 T0 -= T1 + 1;
622 env->psr = 0;
623#ifdef TARGET_SPARC64
624 if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
625 env->psr |= PSR_CARRY;
626 env->xcc = 0;
627 if (src1 <= T1)
628 env->xcc |= PSR_CARRY;
629#else
630 if (src1 <= T1)
631 env->psr |= PSR_CARRY;
632#endif
633 }
634 else
635 {
636 T0 -= T1;
637 env->psr = 0;
638#ifdef TARGET_SPARC64
639 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
640 env->psr |= PSR_CARRY;
641 env->xcc = 0;
642 if (src1 < T1)
643 env->xcc |= PSR_CARRY;
644#else
645 if (src1 < T1)
646 env->psr |= PSR_CARRY;
647#endif
648 }
3475187d
FB		 649#ifdef TARGET_SPARC64
650 if (!(T0 & 0xffffffff))
651 env->psr |= PSR_ZERO;
652 if ((int32_t) T0 < 0)
653 env->psr |= PSR_NEG;
3475187d
FB		 654 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
655 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
656 env->psr |= PSR_OVF;
657
3475187d
FB		 658 if (!T0)
659 env->xcc |= PSR_ZERO;
660 if ((int64_t) T0 < 0)
661 env->xcc |= PSR_NEG;
3475187d
FB		 662 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
663 env->xcc |= PSR_OVF;
664#else
af7bf89b
FB		 665 if (!T0)
666 env->psr |= PSR_ZERO;
667 if ((int32_t) T0 < 0)
668 env->psr |= PSR_NEG;
af7bf89b
FB		 669 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
670 env->psr |= PSR_OVF;
3475187d 671#endif
cf495bcf 672 FORCE_RET();
7a3f1944
FB		 673}
674
e32f879d
BS		 675void OPPROTO op_tsub_T1_T0_cc(void)
676{
677 target_ulong src1;
678
679 src1 = T0;
680 T0 -= T1;
681 env->psr = 0;
682#ifdef TARGET_SPARC64
683 if (!(T0 & 0xffffffff))
684 env->psr |= PSR_ZERO;
685 if ((int32_t) T0 < 0)
686 env->psr |= PSR_NEG;
687 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
688 env->psr |= PSR_CARRY;
689 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
690 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
691 env->psr |= PSR_OVF;
692 if ((src1 & 0x03) || (T1 & 0x03))
693 env->psr |= PSR_OVF;
694
695 env->xcc = 0;
696 if (!T0)
697 env->xcc |= PSR_ZERO;
698 if ((int64_t) T0 < 0)
699 env->xcc |= PSR_NEG;
700 if (src1 < T1)
701 env->xcc |= PSR_CARRY;
702 if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
703 env->xcc |= PSR_OVF;
704#else
705 if (!T0)
706 env->psr |= PSR_ZERO;
707 if ((int32_t) T0 < 0)
708 env->psr |= PSR_NEG;
709 if (src1 < T1)
710 env->psr |= PSR_CARRY;
711 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
712 env->psr |= PSR_OVF;
713 if ((src1 & 0x03) || (T1 & 0x03))
714 env->psr |= PSR_OVF;
715#endif
716 FORCE_RET();
717}
718
719void OPPROTO op_tsub_T1_T0_ccTV(void)
720{
721 target_ulong src1;
722
723 if ((T0 & 0x03) || (T1 & 0x03))
724 raise_exception(TT_TOVF);
725
726 src1 = T0;
727 T0 -= T1;
728
729#ifdef TARGET_SPARC64
730 if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
731 ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
732 raise_exception(TT_TOVF);
733#else
734 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
735 raise_exception(TT_TOVF);
736#endif
737
738 env->psr = 0;
739#ifdef TARGET_SPARC64
740 if (!(T0 & 0xffffffff))
741 env->psr |= PSR_ZERO;
742 if ((int32_t) T0 < 0)
743 env->psr |= PSR_NEG;
744 if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
745 env->psr |= PSR_CARRY;
746
747 env->xcc = 0;
748 if (!T0)
749 env->xcc |= PSR_ZERO;
750 if ((int64_t) T0 < 0)
751 env->xcc |= PSR_NEG;
752 if (src1 < T1)
753 env->xcc |= PSR_CARRY;
754#else
755 if (!T0)
756 env->psr |= PSR_ZERO;
757 if ((int32_t) T0 < 0)
758 env->psr |= PSR_NEG;
759 if (src1 < T1)
760 env->psr |= PSR_CARRY;
761#endif
762 FORCE_RET();
763}
764
cf495bcf 765void OPPROTO op_and_T1_T0(void)
7a3f1944 766{
cf495bcf 767 T0 &= T1;
7a3f1944
FB		 768}
769
cf495bcf 770void OPPROTO op_or_T1_T0(void)
7a3f1944 771{
cf495bcf 772 T0 |= T1;
7a3f1944
FB		 773}
774
cf495bcf 775void OPPROTO op_xor_T1_T0(void)
7a3f1944 776{
cf495bcf 777 T0 ^= T1;
7a3f1944
FB		 778}
779
cf495bcf 780void OPPROTO op_andn_T1_T0(void)
7a3f1944 781{
cf495bcf 782 T0 &= ~T1;
7a3f1944
FB		 783}
784
cf495bcf 785void OPPROTO op_orn_T1_T0(void)
7a3f1944 786{
cf495bcf 787 T0 |= ~T1;
7a3f1944
FB		 788}
789
cf495bcf 790void OPPROTO op_xnor_T1_T0(void)
7a3f1944 791{
cf495bcf 792 T0 ^= ~T1;
7a3f1944
FB		 793}
794
cf495bcf 795void OPPROTO op_umul_T1_T0(void)
7a3f1944 796{
cf495bcf 797 uint64_t res;
af7bf89b 798 res = (uint64_t) T0 * (uint64_t) T1;
83469015
FB		 799#ifdef TARGET_SPARC64
800 T0 = res;
801#else
cf495bcf 802 T0 = res & 0xffffffff;
83469015 803#endif
cf495bcf 804 env->y = res >> 32;
7a3f1944
FB		 805}
806
cf495bcf 807void OPPROTO op_smul_T1_T0(void)
7a3f1944 808{
cf495bcf
FB		 809 uint64_t res;
810 res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1);
83469015
FB		 811#ifdef TARGET_SPARC64
812 T0 = res;
813#else
cf495bcf 814 T0 = res & 0xffffffff;
83469015 815#endif
cf495bcf 816 env->y = res >> 32;
7a3f1944
FB		 817}
818
cf495bcf 819void OPPROTO op_mulscc_T1_T0(void)
7a3f1944 820{
af7bf89b
FB		 821 unsigned int b1, N, V, b2;
822 target_ulong src1;
823
4e8b5da2 824 N = FLAG_SET(PSR_NEG);
cf495bcf 825 V = FLAG_SET(PSR_OVF);
4e8b5da2 826 b1 = N ^ V;
cf495bcf
FB		 827 b2 = T0 & 1;
828 T0 = (b1 << 31) | (T0 >> 1);
829 if (!(env->y & 1))
830 T1 = 0;
831 /* do addition and update flags */
832 src1 = T0;
833 T0 += T1;
834 env->psr = 0;
835 if (!T0)
836 env->psr |= PSR_ZERO;
af7bf89b 837 if ((int32_t) T0 < 0)
cf495bcf
FB		 838 env->psr |= PSR_NEG;
839 if (T0 < src1)
840 env->psr |= PSR_CARRY;
841 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
842 env->psr |= PSR_OVF;
843 env->y = (b2 << 31) | (env->y >> 1);
844 FORCE_RET();
845}
846
847void OPPROTO op_udiv_T1_T0(void)
848{
849 uint64_t x0;
850 uint32_t x1;
851
852 x0 = T0 | ((uint64_t) (env->y) << 32);
853 x1 = T1;
9bb234b3
TS		 854
855 if (x1 == 0) {
856 raise_exception(TT_DIV_ZERO);
857 }
858
cf495bcf
FB		 859 x0 = x0 / x1;
860 if (x0 > 0xffffffff) {
861 T0 = 0xffffffff;
862 T1 = 1;
863 } else {
864 T0 = x0;
865 T1 = 0;
866 }
867 FORCE_RET();
7a3f1944
FB		 868}
869
cf495bcf 870void OPPROTO op_sdiv_T1_T0(void)
7a3f1944 871{
cf495bcf
FB		 872 int64_t x0;
873 int32_t x1;
874
af7bf89b 875 x0 = T0 | ((int64_t) (env->y) << 32);
cf495bcf 876 x1 = T1;
9bb234b3
TS		 877
878 if (x1 == 0) {
879 raise_exception(TT_DIV_ZERO);
880 }
881
cf495bcf
FB		 882 x0 = x0 / x1;
883 if ((int32_t) x0 != x0) {
af7bf89b 884 T0 = x0 < 0? 0x80000000: 0x7fffffff;
cf495bcf
FB		 885 T1 = 1;
886 } else {
887 T0 = x0;
888 T1 = 0;
889 }
890 FORCE_RET();
7a3f1944
FB		 891}
892
cf495bcf 893void OPPROTO op_div_cc(void)
7a3f1944 894{
cf495bcf 895 env->psr = 0;
3475187d
FB		 896#ifdef TARGET_SPARC64
897 if (!T0)
898 env->psr |= PSR_ZERO;
899 if ((int32_t) T0 < 0)
900 env->psr |= PSR_NEG;
901 if (T1)
902 env->psr |= PSR_OVF;
903
904 env->xcc = 0;
905 if (!T0)
906 env->xcc |= PSR_ZERO;
907 if ((int64_t) T0 < 0)
908 env->xcc |= PSR_NEG;
909#else
cf495bcf
FB		 910 if (!T0)
911 env->psr |= PSR_ZERO;
af7bf89b 912 if ((int32_t) T0 < 0)
cf495bcf
FB		 913 env->psr |= PSR_NEG;
914 if (T1)
915 env->psr |= PSR_OVF;
3475187d 916#endif
cf495bcf 917 FORCE_RET();
7a3f1944
FB		 918}
919
3475187d
FB		 920#ifdef TARGET_SPARC64
921void OPPROTO op_mulx_T1_T0(void)
922{
923 T0 *= T1;
924 FORCE_RET();
925}
926
927void OPPROTO op_udivx_T1_T0(void)
928{
929 T0 /= T1;
930 FORCE_RET();
931}
932
933void OPPROTO op_sdivx_T1_T0(void)
934{
935 if (T0 == INT64_MIN && T1 == -1)
936 T0 = INT64_MIN;
937 else
938 T0 /= (target_long) T1;
939 FORCE_RET();
940}
941#endif
942
cf495bcf 943void OPPROTO op_logic_T0_cc(void)
7a3f1944 944{
cf495bcf 945 env->psr = 0;
3475187d
FB		 946#ifdef TARGET_SPARC64
947 if (!(T0 & 0xffffffff))
948 env->psr |= PSR_ZERO;
949 if ((int32_t) T0 < 0)
950 env->psr |= PSR_NEG;
951
952 env->xcc = 0;
953 if (!T0)
954 env->xcc |= PSR_ZERO;
955 if ((int64_t) T0 < 0)
956 env->xcc |= PSR_NEG;
957#else
cf495bcf
FB		 958 if (!T0)
959 env->psr |= PSR_ZERO;
af7bf89b 960 if ((int32_t) T0 < 0)
cf495bcf 961 env->psr |= PSR_NEG;
3475187d 962#endif
cf495bcf 963 FORCE_RET();
7a3f1944
FB		 964}
965
cf495bcf 966void OPPROTO op_sll(void)
7a3f1944 967{
8a08f9a8 968 T0 <<= (T1 & 0x1f);
7a3f1944
FB		 969}
970
3475187d 971#ifdef TARGET_SPARC64
8a08f9a8
BS		 972void OPPROTO op_sllx(void)
973{
974 T0 <<= (T1 & 0x3f);
975}
976
3475187d
FB		 977void OPPROTO op_srl(void)
978{
8a08f9a8 979 T0 = (T0 & 0xffffffff) >> (T1 & 0x1f);
3475187d
FB		 980}
981
982void OPPROTO op_srlx(void)
983{
8a08f9a8 984 T0 >>= (T1 & 0x3f);
3475187d
FB		 985}
986
987void OPPROTO op_sra(void)
988{
8a08f9a8 989 T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f);
3475187d
FB		 990}
991
992void OPPROTO op_srax(void)
993{
8a08f9a8 994 T0 = ((int64_t) T0) >> (T1 & 0x3f);
3475187d
FB		 995}
996#else
cf495bcf 997void OPPROTO op_srl(void)
7a3f1944 998{
8a08f9a8 999 T0 >>= (T1 & 0x1f);
7a3f1944
FB		 1000}
1001
cf495bcf 1002void OPPROTO op_sra(void)
7a3f1944 1003{
8a08f9a8 1004 T0 = ((int32_t) T0) >> (T1 & 0x1f);
7a3f1944 1005}
3475187d 1006#endif
7a3f1944 1007
e8af50a3
FB		 1008/* Load and store */
1009#define MEMSUFFIX _raw
1010#include "op_mem.h"
1011#if !defined(CONFIG_USER_ONLY)
1012#define MEMSUFFIX _user
1013#include "op_mem.h"
1014
1015#define MEMSUFFIX _kernel
1016#include "op_mem.h"
1017#endif
e8af50a3
FB		 1018
1019void OPPROTO op_ldfsr(void)
1020{
3475187d 1021 PUT_FSR32(env, *((uint32_t *) &FT0));
8d5f07fa 1022 helper_ldfsr();
e8af50a3
FB		 1023}
1024
1025void OPPROTO op_stfsr(void)
1026{
3475187d 1027 *((uint32_t *) &FT0) = GET_FSR32(env);
e8af50a3
FB		 1028}
1029
3475187d
FB		 1030#ifndef TARGET_SPARC64
1031void OPPROTO op_rdpsr(void)
7a3f1944 1032{
3475187d 1033 do_rdpsr();
7a3f1944
FB		 1034}
1035
3475187d 1036void OPPROTO op_wrpsr(void)
7a3f1944 1037{
3475187d
FB		 1038 do_wrpsr();
1039 FORCE_RET();
7a3f1944
FB		 1040}
1041
c688a6eb
FB		 1042void OPPROTO op_wrwim(void)
1043{
1044#if NWINDOWS == 32
1045 env->wim = T0;
1046#else
1047 env->wim = T0 & ((1 << NWINDOWS) - 1);
1048#endif
1049}
1050
3475187d 1051void OPPROTO op_rett(void)
cf495bcf 1052{
3475187d
FB		 1053 helper_rett();
1054 FORCE_RET();
e8af50a3
FB		 1055}
1056
3475187d
FB		 1057/* XXX: use another pointer for %iN registers to avoid slow wrapping
1058 handling ? */
1059void OPPROTO op_save(void)
e8af50a3 1060{
3475187d
FB		 1061 uint32_t cwp;
1062 cwp = (env->cwp - 1) & (NWINDOWS - 1);
1063 if (env->wim & (1 << cwp)) {
1064 raise_exception(TT_WIN_OVF);
1065 }
1066 set_cwp(cwp);
e8af50a3
FB		 1067 FORCE_RET();
1068}
1069
3475187d 1070void OPPROTO op_restore(void)
e8af50a3 1071{
3475187d
FB		 1072 uint32_t cwp;
1073 cwp = (env->cwp + 1) & (NWINDOWS - 1);
1074 if (env->wim & (1 << cwp)) {
1075 raise_exception(TT_WIN_UNF);
1076 }
1077 set_cwp(cwp);
1078 FORCE_RET();
1079}
1080#else
1081void OPPROTO op_rdccr(void)
1082{
1083 T0 = GET_CCR(env);
e8af50a3
FB		 1084}
1085
3475187d 1086void OPPROTO op_wrccr(void)
e8af50a3 1087{
3475187d 1088 PUT_CCR(env, T0);
e8af50a3
FB		 1089}
1090
3475187d 1091void OPPROTO op_rdtick(void)
e8af50a3 1092{
3475187d 1093 T0 = 0; // XXX read cycle counter and bit 31
e8af50a3 1094}
cf495bcf 1095
3475187d 1096void OPPROTO op_wrtick(void)
7a3f1944 1097{
e9ebed4d 1098 T0 = 0; // XXX write cycle counter and bit 31
7a3f1944
FB		 1099}
1100
3475187d 1101void OPPROTO op_rdtpc(void)
cf495bcf 1102{
3475187d
FB		 1103 T0 = env->tpc[env->tl];
1104}
1105
1106void OPPROTO op_wrtpc(void)
1107{
1108 env->tpc[env->tl] = T0;
1109}
1110
1111void OPPROTO op_rdtnpc(void)
1112{
1113 T0 = env->tnpc[env->tl];
1114}
1115
1116void OPPROTO op_wrtnpc(void)
1117{
1118 env->tnpc[env->tl] = T0;
1119}
1120
1121void OPPROTO op_rdtstate(void)
1122{
1123 T0 = env->tstate[env->tl];
1124}
1125
1126void OPPROTO op_wrtstate(void)
1127{
1128 env->tstate[env->tl] = T0;
1129}
1130
1131void OPPROTO op_rdtt(void)
1132{
1133 T0 = env->tt[env->tl];
1134}
1135
1136void OPPROTO op_wrtt(void)
1137{
1138 env->tt[env->tl] = T0;
1139}
1140
1141void OPPROTO op_rdpstate(void)
1142{
1143 T0 = env->pstate;
1144}
1145
1146void OPPROTO op_wrpstate(void)
1147{
83469015 1148 do_wrpstate();
3475187d
FB		 1149}
1150
1151// CWP handling is reversed in V9, but we still use the V8 register
1152// order.
1153void OPPROTO op_rdcwp(void)
1154{
1155 T0 = NWINDOWS - 1 - env->cwp;
1156}
1157
1158void OPPROTO op_wrcwp(void)
1159{
1160 env->cwp = NWINDOWS - 1 - T0;
cf495bcf 1161}
7a3f1944 1162
cf495bcf
FB		 1163/* XXX: use another pointer for %iN registers to avoid slow wrapping
1164 handling ? */
1165void OPPROTO op_save(void)
7a3f1944 1166{
af7bf89b 1167 uint32_t cwp;
cf495bcf 1168 cwp = (env->cwp - 1) & (NWINDOWS - 1);
3475187d
FB		 1169 if (env->cansave == 0) {
1170 raise_exception(TT_SPILL | (env->otherwin != 0 ?
1171 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1172 ((env->wstate & 0x7) << 2)));
1173 } else {
1174 if (env->cleanwin - env->canrestore == 0) {
1175 // XXX Clean windows without trap
1176 raise_exception(TT_CLRWIN);
1177 } else {
1178 env->cansave--;
1179 env->canrestore++;
1180 set_cwp(cwp);
1181 }
cf495bcf 1182 }
cf495bcf 1183 FORCE_RET();
7a3f1944
FB		 1184}
1185
cf495bcf 1186void OPPROTO op_restore(void)
7a3f1944 1187{
af7bf89b 1188 uint32_t cwp;
cf495bcf 1189 cwp = (env->cwp + 1) & (NWINDOWS - 1);
3475187d
FB		 1190 if (env->canrestore == 0) {
1191 raise_exception(TT_FILL | (env->otherwin != 0 ?
1192 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1193 ((env->wstate & 0x7) << 2)));
1194 } else {
1195 env->cansave++;
1196 env->canrestore--;
1197 set_cwp(cwp);
cf495bcf 1198 }
cf495bcf 1199 FORCE_RET();
7a3f1944 1200}
3475187d 1201#endif
7a3f1944 1202
cf495bcf 1203void OPPROTO op_exception(void)
7a3f1944 1204{
cf495bcf
FB		 1205 env->exception_index = PARAM1;
1206 cpu_loop_exit();
7a3f1944
FB		 1207}
1208
cf495bcf 1209void OPPROTO op_trap_T0(void)
7a3f1944 1210{
cf495bcf
FB		 1211 env->exception_index = TT_TRAP + (T0 & 0x7f);
1212 cpu_loop_exit();
7a3f1944
FB		 1213}
1214
cf495bcf 1215void OPPROTO op_trapcc_T0(void)
7a3f1944 1216{
cf495bcf
FB		 1217 if (T2) {
1218 env->exception_index = TT_TRAP + (T0 & 0x7f);
1219 cpu_loop_exit();
1220 }
1221 FORCE_RET();
7a3f1944
FB		 1222}
1223
e80cfcfc 1224void OPPROTO op_fpexception_im(void)
e8af50a3 1225{
e80cfcfc
FB		 1226 env->exception_index = TT_FP_EXCP;
1227 env->fsr &= ~FSR_FTT_MASK;
1228 env->fsr |= PARAM1;
e8af50a3 1229 cpu_loop_exit();
e80cfcfc
FB		 1230 FORCE_RET();
1231}
1232
1233void OPPROTO op_debug(void)
1234{
1235 helper_debug();
e8af50a3
FB		 1236}
1237
cf495bcf 1238void OPPROTO op_exit_tb(void)
7a3f1944 1239{
cf495bcf 1240 EXIT_TB();
7a3f1944
FB		 1241}
1242
3475187d
FB		 1243void OPPROTO op_eval_ba(void)
1244{
1245 T2 = 1;
1246}
1247
cf495bcf 1248void OPPROTO op_eval_be(void)
7a3f1944 1249{
af7bf89b 1250 T2 = FLAG_SET(PSR_ZERO);
7a3f1944
FB		 1251}
1252
cf495bcf 1253void OPPROTO op_eval_ble(void)
7a3f1944 1254{
af7bf89b 1255 target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
612b477d 1256
cf495bcf 1257 T2 = Z | (N ^ V);
7a3f1944
FB		 1258}
1259
cf495bcf 1260void OPPROTO op_eval_bl(void)
7a3f1944 1261{
af7bf89b 1262 target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
612b477d 1263
cf495bcf 1264 T2 = N ^ V;
7a3f1944
FB		 1265}
1266
cf495bcf 1267void OPPROTO op_eval_bleu(void)
7a3f1944 1268{
af7bf89b 1269 target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
612b477d 1270
cf495bcf 1271 T2 = C | Z;
7a3f1944
FB		 1272}
1273
cf495bcf 1274void OPPROTO op_eval_bcs(void)
7a3f1944 1275{
af7bf89b 1276 T2 = FLAG_SET(PSR_CARRY);
7a3f1944
FB		 1277}
1278
cf495bcf 1279void OPPROTO op_eval_bvs(void)
7a3f1944 1280{
af7bf89b 1281 T2 = FLAG_SET(PSR_OVF);
7a3f1944
FB		 1282}
1283
3475187d
FB		 1284void OPPROTO op_eval_bn(void)
1285{
1286 T2 = 0;
1287}
1288
cf495bcf 1289void OPPROTO op_eval_bneg(void)
7a3f1944 1290{
af7bf89b 1291 T2 = FLAG_SET(PSR_NEG);
7a3f1944
FB		 1292}
1293
cf495bcf 1294void OPPROTO op_eval_bne(void)
7a3f1944 1295{
af7bf89b 1296 T2 = !FLAG_SET(PSR_ZERO);
7a3f1944
FB		 1297}
1298
cf495bcf 1299void OPPROTO op_eval_bg(void)
7a3f1944 1300{
af7bf89b 1301 target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
612b477d 1302
cf495bcf 1303 T2 = !(Z | (N ^ V));
7a3f1944
FB		 1304}
1305
cf495bcf 1306void OPPROTO op_eval_bge(void)
7a3f1944 1307{
af7bf89b 1308 target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
612b477d 1309
cf495bcf 1310 T2 = !(N ^ V);
7a3f1944
FB		 1311}
1312
cf495bcf 1313void OPPROTO op_eval_bgu(void)
7a3f1944 1314{
af7bf89b 1315 target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
612b477d 1316
cf495bcf 1317 T2 = !(C | Z);
7a3f1944
FB		 1318}
1319
cf495bcf 1320void OPPROTO op_eval_bcc(void)
7a3f1944 1321{
af7bf89b 1322 T2 = !FLAG_SET(PSR_CARRY);
7a3f1944
FB		 1323}
1324
cf495bcf
FB		 1325void OPPROTO op_eval_bpos(void)
1326{
af7bf89b 1327 T2 = !FLAG_SET(PSR_NEG);
cf495bcf
FB		 1328}
1329
1330void OPPROTO op_eval_bvc(void)
1331{
af7bf89b 1332 T2 = !FLAG_SET(PSR_OVF);
cf495bcf
FB		 1333}
1334
3475187d
FB		 1335#ifdef TARGET_SPARC64
1336void OPPROTO op_eval_xbe(void)
1337{
1338 T2 = XFLAG_SET(PSR_ZERO);
1339}
e8af50a3 1340
3475187d 1341void OPPROTO op_eval_xble(void)
e8af50a3 1342{
3475187d
FB		 1343 target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1344
1345 T2 = Z | (N ^ V);
e8af50a3
FB		 1346}
1347
3475187d 1348void OPPROTO op_eval_xbl(void)
e8af50a3 1349{
3475187d
FB		 1350 target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1351
1352 T2 = N ^ V;
e8af50a3
FB		 1353}
1354
3475187d 1355void OPPROTO op_eval_xbleu(void)
e8af50a3 1356{
3475187d
FB		 1357 target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
1358
1359 T2 = C | Z;
e8af50a3
FB		 1360}
1361
3475187d 1362void OPPROTO op_eval_xbcs(void)
e8af50a3 1363{
3475187d 1364 T2 = XFLAG_SET(PSR_CARRY);
e8af50a3
FB		 1365}
1366
3475187d 1367void OPPROTO op_eval_xbvs(void)
e8af50a3 1368{
3475187d 1369 T2 = XFLAG_SET(PSR_OVF);
e8af50a3
FB		 1370}
1371
3475187d 1372void OPPROTO op_eval_xbneg(void)
e8af50a3 1373{
3475187d 1374 T2 = XFLAG_SET(PSR_NEG);
e8af50a3
FB		 1375}
1376
3475187d 1377void OPPROTO op_eval_xbne(void)
e8af50a3 1378{
3475187d 1379 T2 = !XFLAG_SET(PSR_ZERO);
e8af50a3
FB		 1380}
1381
3475187d 1382void OPPROTO op_eval_xbg(void)
e8af50a3 1383{
3475187d
FB		 1384 target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1385
1386 T2 = !(Z | (N ^ V));
e8af50a3
FB		 1387}
1388
3475187d 1389void OPPROTO op_eval_xbge(void)
e8af50a3 1390{
3475187d
FB		 1391 target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1392
1393 T2 = !(N ^ V);
1394}
1395
1396void OPPROTO op_eval_xbgu(void)
1397{
1398 target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
1399
1400 T2 = !(C | Z);
1401}
1402
1403void OPPROTO op_eval_xbcc(void)
1404{
1405 T2 = !XFLAG_SET(PSR_CARRY);
1406}
1407
1408void OPPROTO op_eval_xbpos(void)
1409{
1410 T2 = !XFLAG_SET(PSR_NEG);
1411}
1412
1413void OPPROTO op_eval_xbvc(void)
1414{
1415 T2 = !XFLAG_SET(PSR_OVF);
1416}
1417#endif
1418
1419#define FCC
1420#define FFLAG_SET(x) (env->fsr & x? 1: 0)
1421#include "fbranch_template.h"
1422
1423#ifdef TARGET_SPARC64
1424#define FCC _fcc1
1425#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0)
1426#include "fbranch_template.h"
1427#define FCC _fcc2
1428#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0)
1429#include "fbranch_template.h"
1430#define FCC _fcc3
1431#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0)
1432#include "fbranch_template.h"
1433#endif
1434
1435#ifdef TARGET_SPARC64
1436void OPPROTO op_eval_brz(void)
1437{
83469015 1438 T2 = (T0 == 0);
e8af50a3
FB		 1439}
1440
3475187d 1441void OPPROTO op_eval_brnz(void)
e8af50a3 1442{
83469015 1443 T2 = (T0 != 0);
e8af50a3
FB		 1444}
1445
3475187d 1446void OPPROTO op_eval_brlz(void)
e8af50a3 1447{
3475187d 1448 T2 = ((int64_t)T0 < 0);
e8af50a3
FB		 1449}
1450
3475187d 1451void OPPROTO op_eval_brlez(void)
e8af50a3 1452{
3475187d 1453 T2 = ((int64_t)T0 <= 0);
e8af50a3
FB		 1454}
1455
3475187d 1456void OPPROTO op_eval_brgz(void)
e8af50a3 1457{
3475187d 1458 T2 = ((int64_t)T0 > 0);
e8af50a3
FB		 1459}
1460
3475187d 1461void OPPROTO op_eval_brgez(void)
e8af50a3 1462{
3475187d 1463 T2 = ((int64_t)T0 >= 0);
e8af50a3
FB		 1464}
1465
3475187d
FB		 1466void OPPROTO op_jmp_im64(void)
1467{
1468 env->pc = PARAMQ1;
1469}
1470
1471void OPPROTO op_movq_npc_im64(void)
1472{
1473 env->npc = PARAMQ1;
1474}
1475#endif
1476
cf495bcf
FB		 1477void OPPROTO op_jmp_im(void)
1478{
3475187d 1479 env->pc = (uint32_t)PARAM1;
cf495bcf
FB		 1480}
1481
1482void OPPROTO op_movl_npc_im(void)
1483{
3475187d 1484 env->npc = (uint32_t)PARAM1;
cf495bcf 1485}
7a3f1944 1486
cf495bcf 1487void OPPROTO op_movl_npc_T0(void)
7a3f1944 1488{
d2889a3e
BS		 1489 if (T0 & 0x3)
1490 raise_exception(TT_UNALIGNED);
1491 else
1492 env->npc = T0;
7a3f1944
FB		 1493}
1494
0bee699e
FB		 1495void OPPROTO op_mov_pc_npc(void)
1496{
1497 env->pc = env->npc;
1498}
1499
cf495bcf 1500void OPPROTO op_next_insn(void)
7a3f1944 1501{
cf495bcf
FB		 1502 env->pc = env->npc;
1503 env->npc = env->npc + 4;
7a3f1944
FB		 1504}
1505
83469015 1506void OPPROTO op_goto_tb0(void)
72cbca10 1507{
83469015 1508 GOTO_TB(op_goto_tb0, PARAM1, 0);
72cbca10
FB		 1509}
1510
83469015 1511void OPPROTO op_goto_tb1(void)
7a3f1944 1512{
83469015 1513 GOTO_TB(op_goto_tb1, PARAM1, 1);
72cbca10
FB		 1514}
1515
83469015 1516void OPPROTO op_jmp_label(void)
72cbca10 1517{
83469015
FB		 1518 GOTO_LABEL_PARAM(1);
1519}
1520
1521void OPPROTO op_jnz_T2_label(void)
1522{
1523 if (T2)
1524 GOTO_LABEL_PARAM(1);
cf495bcf 1525 FORCE_RET();
7a3f1944
FB		 1526}
1527
83469015 1528void OPPROTO op_jz_T2_label(void)
7a3f1944 1529{
83469015
FB		 1530 if (!T2)
1531 GOTO_LABEL_PARAM(1);
cf495bcf 1532 FORCE_RET();
7a3f1944 1533}
72cbca10 1534
658138bc
FB		 1535void OPPROTO op_flush_T0(void)
1536{
1537 helper_flush(T0);
1538}
e8af50a3 1539
417454b0
BS		 1540void OPPROTO op_clear_ieee_excp_and_FTT(void)
1541{
1542 env->fsr &= ~(FSR_FTT_MASK | FSR_CEXC_MASK);;
1543}
1544
65ce8c2f
FB		 1545#define F_OP(name, p) void OPPROTO op_f##name##p(void)
1546
1547#define F_BINOP(name) \
1548 F_OP(name, s) \
1549 { \
417454b0 1550 set_float_exception_flags(0, &env->fp_status); \
65ce8c2f 1551 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
417454b0 1552 check_ieee_exceptions(); \
65ce8c2f
FB		 1553 } \
1554 F_OP(name, d) \
1555 { \
417454b0 1556 set_float_exception_flags(0, &env->fp_status); \
65ce8c2f 1557 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
417454b0 1558 check_ieee_exceptions(); \
65ce8c2f 1559 }
e8af50a3 1560
65ce8c2f
FB		 1561F_BINOP(add);
1562F_BINOP(sub);
1563F_BINOP(mul);
1564F_BINOP(div);
1565#undef F_BINOP
e8af50a3
FB		 1566
1567void OPPROTO op_fsmuld(void)
1568{
417454b0 1569 set_float_exception_flags(0, &env->fp_status);
65ce8c2f
FB		 1570 DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
1571 float32_to_float64(FT1, &env->fp_status),
1572 &env->fp_status);
417454b0 1573 check_ieee_exceptions();
e8af50a3
FB		 1574}
1575
65ce8c2f
FB		 1576#define F_HELPER(name) \
1577 F_OP(name, s) \
1578 { \
1579 do_f##name##s(); \
1580 } \
1581 F_OP(name, d) \
1582 { \
1583 do_f##name##d(); \
1584 }
e8af50a3 1585
65ce8c2f 1586F_HELPER(sqrt);
e8af50a3 1587
65ce8c2f 1588F_OP(neg, s)
e8af50a3 1589{
65ce8c2f 1590 FT0 = float32_chs(FT1);
e8af50a3
FB		 1591}
1592
65ce8c2f 1593F_OP(abs, s)
e8af50a3 1594{
65ce8c2f 1595 do_fabss();
e8af50a3
FB		 1596}
1597
65ce8c2f 1598F_HELPER(cmp);
417454b0 1599F_HELPER(cmpe);
e8af50a3 1600
65ce8c2f
FB		 1601#ifdef TARGET_SPARC64
1602F_OP(neg, d)
e8af50a3 1603{
65ce8c2f 1604 DT0 = float64_chs(DT1);
e8af50a3
FB		 1605}
1606
65ce8c2f 1607F_OP(abs, d)
e8af50a3 1608{
65ce8c2f 1609 do_fabsd();
e8af50a3
FB		 1610}
1611
3475187d
FB		 1612void OPPROTO op_fcmps_fcc1(void)
1613{
1614 do_fcmps_fcc1();
1615}
1616
1617void OPPROTO op_fcmpd_fcc1(void)
1618{
1619 do_fcmpd_fcc1();
1620}
1621
1622void OPPROTO op_fcmps_fcc2(void)
1623{
1624 do_fcmps_fcc2();
1625}
1626
1627void OPPROTO op_fcmpd_fcc2(void)
1628{
1629 do_fcmpd_fcc2();
1630}
1631
1632void OPPROTO op_fcmps_fcc3(void)
1633{
1634 do_fcmps_fcc3();
1635}
1636
1637void OPPROTO op_fcmpd_fcc3(void)
1638{
1639 do_fcmpd_fcc3();
1640}
417454b0
BS		 1641
1642void OPPROTO op_fcmpes_fcc1(void)
1643{
1644 do_fcmpes_fcc1();
1645}
1646
1647void OPPROTO op_fcmped_fcc1(void)
1648{
1649 do_fcmped_fcc1();
1650}
1651
1652void OPPROTO op_fcmpes_fcc2(void)
1653{
1654 do_fcmpes_fcc2();
1655}
1656
1657void OPPROTO op_fcmped_fcc2(void)
1658{
1659 do_fcmped_fcc2();
1660}
1661
1662void OPPROTO op_fcmpes_fcc3(void)
1663{
1664 do_fcmpes_fcc3();
1665}
1666
1667void OPPROTO op_fcmped_fcc3(void)
1668{
1669 do_fcmped_fcc3();
1670}
1671
3475187d
FB		 1672#endif
1673
65ce8c2f 1674/* Integer to float conversion. */
a0c4cb4a 1675#ifdef USE_INT_TO_FLOAT_HELPERS
65ce8c2f 1676F_HELPER(ito);
a0c4cb4a 1677#else
65ce8c2f 1678F_OP(ito, s)
a0c4cb4a 1679{
417454b0 1680 set_float_exception_flags(0, &env->fp_status);
65ce8c2f 1681 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
417454b0 1682 check_ieee_exceptions();
e8af50a3
FB		 1683}
1684
65ce8c2f 1685F_OP(ito, d)
e8af50a3 1686{
417454b0 1687 set_float_exception_flags(0, &env->fp_status);
65ce8c2f 1688 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
417454b0 1689 check_ieee_exceptions();
e8af50a3 1690}
3475187d
FB		 1691
1692#ifdef TARGET_SPARC64
65ce8c2f 1693F_OP(xto, s)
3475187d 1694{
417454b0 1695 set_float_exception_flags(0, &env->fp_status);
65ce8c2f 1696 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
417454b0 1697 check_ieee_exceptions();
3475187d
FB		 1698}
1699
65ce8c2f 1700F_OP(xto, d)
3475187d 1701{
417454b0 1702 set_float_exception_flags(0, &env->fp_status);
65ce8c2f 1703 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
417454b0 1704 check_ieee_exceptions();
3475187d
FB		 1705}
1706#endif
a0c4cb4a 1707#endif
65ce8c2f 1708#undef F_HELPER
a0c4cb4a 1709
65ce8c2f 1710/* floating point conversion */
a0c4cb4a
FB		 1711void OPPROTO op_fdtos(void)
1712{
417454b0 1713 set_float_exception_flags(0, &env->fp_status);
65ce8c2f 1714 FT0 = float64_to_float32(DT1, &env->fp_status);
417454b0 1715 check_ieee_exceptions();
a0c4cb4a 1716}
e8af50a3
FB		 1717
1718void OPPROTO op_fstod(void)
1719{
417454b0 1720 set_float_exception_flags(0, &env->fp_status);
65ce8c2f 1721 DT0 = float32_to_float64(FT1, &env->fp_status);
417454b0 1722 check_ieee_exceptions();
e8af50a3
FB		 1723}
1724
65ce8c2f 1725/* Float to integer conversion. */
e8af50a3
FB		 1726void OPPROTO op_fstoi(void)
1727{
417454b0 1728 set_float_exception_flags(0, &env->fp_status);
bd59780c 1729 *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
417454b0 1730 check_ieee_exceptions();
e8af50a3
FB		 1731}
1732
1733void OPPROTO op_fdtoi(void)
1734{
417454b0 1735 set_float_exception_flags(0, &env->fp_status);
bd59780c 1736 *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
417454b0 1737 check_ieee_exceptions();
e8af50a3
FB		 1738}
1739
3475187d
FB		 1740#ifdef TARGET_SPARC64
1741void OPPROTO op_fstox(void)
1742{
417454b0 1743 set_float_exception_flags(0, &env->fp_status);
bd59780c 1744 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
417454b0 1745 check_ieee_exceptions();
3475187d
FB		 1746}
1747
1748void OPPROTO op_fdtox(void)
1749{
417454b0 1750 set_float_exception_flags(0, &env->fp_status);
bd59780c 1751 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
417454b0 1752 check_ieee_exceptions();
3475187d
FB		 1753}
1754
1755void OPPROTO op_fmovs_cc(void)
1756{
1757 if (T2)
1758 FT0 = FT1;
1759}
1760
1761void OPPROTO op_fmovd_cc(void)
1762{
1763 if (T2)
1764 DT0 = DT1;
1765}
1766
1767void OPPROTO op_mov_cc(void)
1768{
1769 if (T2)
1770 T0 = T1;
1771}
1772
1773void OPPROTO op_flushw(void)
1774{
1775 if (env->cansave != NWINDOWS - 2) {
1776 raise_exception(TT_SPILL | (env->otherwin != 0 ?
1777 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1778 ((env->wstate & 0x7) << 2)));
1779 }
1780}
1781
1782void OPPROTO op_saved(void)
1783{
1784 env->cansave++;
1785 if (env->otherwin == 0)
1786 env->canrestore--;
725cb90b
FB		 1787 else
1788 env->otherwin--;
1789 FORCE_RET();
3475187d
FB		 1790}
1791
1792void OPPROTO op_restored(void)
1793{
1794 env->canrestore++;
1795 if (env->cleanwin < NWINDOWS - 1)
1796 env->cleanwin++;
1797 if (env->otherwin == 0)
1798 env->cansave--;
1799 else
1800 env->otherwin--;
725cb90b 1801 FORCE_RET();
3475187d
FB		 1802}
1803
1804void OPPROTO op_popc(void)
1805{
1806 do_popc();
1807}
1808
1809void OPPROTO op_done(void)
1810{
83469015 1811 do_done();
3475187d
FB		 1812}
1813
1814void OPPROTO op_retry(void)
1815{
83469015 1816 do_retry();
3475187d
FB		 1817}
1818
1819void OPPROTO op_sir(void)
1820{
e9ebed4d 1821 T0 = 0; // XXX
3475187d
FB		 1822}
1823
1824void OPPROTO op_ld_asi_reg()
1825{
1826 T0 += PARAM1;
1827 helper_ld_asi(env->asi, PARAM2, PARAM3);
1828}
1829
1830void OPPROTO op_st_asi_reg()
1831{
1832 T0 += PARAM1;
1833 helper_st_asi(env->asi, PARAM2, PARAM3);
1834}
1835#endif
1836
e8af50a3
FB		 1837void OPPROTO op_ld_asi()
1838{
1839 helper_ld_asi(PARAM1, PARAM2, PARAM3);
1840}
1841
1842void OPPROTO op_st_asi()
1843{
1844 helper_st_asi(PARAM1, PARAM2, PARAM3);
1845}
1846
725cb90b 1847#ifdef TARGET_SPARC64
e9ebed4d
BS		 1848// This function uses non-native bit order
1849#define GET_FIELD(X, FROM, TO) \
1850 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
1851
1852// This function uses the order in the manuals, i.e. bit 0 is 2^0
1853#define GET_FIELD_SP(X, FROM, TO) \
1854 GET_FIELD(X, 63 - (TO), 63 - (FROM))
1855
1856void OPPROTO op_array8()
1857{
1858 T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
1859 (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
1860 (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
1861 (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
1862 (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
1863 (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12);
1864}
1865
1866void OPPROTO op_array16()
1867{
1868 T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
1869 (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
1870 (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
1871 (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
1872 (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
1873 (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1;
1874}
1875
1876void OPPROTO op_array32()
1877{
1878 T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
1879 (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
1880 (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
1881 (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
1882 (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
1883 (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2;
1884}
1885
725cb90b
FB		 1886void OPPROTO op_alignaddr()
1887{
1888 uint64_t tmp;
1889
1890 tmp = T0 + T1;
1891 env->gsr &= ~7ULL;
1892 env->gsr |= tmp & 7ULL;
1893 T0 = tmp & ~7ULL;
1894}
1895
1896void OPPROTO op_faligndata()
1897{
1898 uint64_t tmp;
1899
1900 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
1901 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
e9ebed4d 1902 *((uint64_t *)&DT0) = tmp;
725cb90b 1903}
3299908c
BS		 1904
1905void OPPROTO op_movl_FT0_0(void)
1906{
e9ebed4d 1907 *((uint32_t *)&FT0) = 0;
3299908c
BS		 1908}
1909
1910void OPPROTO op_movl_DT0_0(void)
1911{
e9ebed4d 1912 *((uint64_t *)&DT0) = 0;
3299908c
BS		 1913}
1914
1915void OPPROTO op_movl_FT0_1(void)
1916{
e9ebed4d 1917 *((uint32_t *)&FT0) = 0xffffffff;
3299908c
BS		 1918}
1919
1920void OPPROTO op_movl_DT0_1(void)
1921{
e9ebed4d
BS		 1922 *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
1923}
1924
1925void OPPROTO op_fnot(void)
1926{
1927 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
1928}
1929
1930void OPPROTO op_fnots(void)
1931{
1932 *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
1933}
1934
1935void OPPROTO op_fnor(void)
1936{
1937 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
1938}
1939
1940void OPPROTO op_fnors(void)
1941{
1942 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
1943}
1944
1945void OPPROTO op_for(void)
1946{
1947 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
1948}
1949
1950void OPPROTO op_fors(void)
1951{
1952 *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
1953}
1954
1955void OPPROTO op_fxor(void)
1956{
1957 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
1958}
1959
1960void OPPROTO op_fxors(void)
1961{
1962 *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
1963}
1964
1965void OPPROTO op_fand(void)
1966{
1967 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
1968}
1969
1970void OPPROTO op_fands(void)
1971{
1972 *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
1973}
1974
1975void OPPROTO op_fornot(void)
1976{
1977 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
1978}
1979
1980void OPPROTO op_fornots(void)
1981{
1982 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
1983}
1984
1985void OPPROTO op_fandnot(void)
1986{
1987 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
1988}
1989
1990void OPPROTO op_fandnots(void)
1991{
1992 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
1993}
1994
1995void OPPROTO op_fnand(void)
1996{
1997 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
1998}
1999
2000void OPPROTO op_fnands(void)
2001{
2002 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
2003}
2004
2005void OPPROTO op_fxnor(void)
2006{
2007 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
2008}
2009
2010void OPPROTO op_fxnors(void)
2011{
2012 *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
2013}
2014
2015#ifdef WORDS_BIGENDIAN
2016#define VIS_B64(n) b[7 - (n)]
2017#define VIS_W64(n) w[3 - (n)]
2018#define VIS_SW64(n) sw[3 - (n)]
2019#define VIS_L64(n) l[1 - (n)]
2020#define VIS_B32(n) b[3 - (n)]
2021#define VIS_W32(n) w[1 - (n)]
2022#else
2023#define VIS_B64(n) b[n]
2024#define VIS_W64(n) w[n]
2025#define VIS_SW64(n) sw[n]
2026#define VIS_L64(n) l[n]
2027#define VIS_B32(n) b[n]
2028#define VIS_W32(n) w[n]
2029#endif
2030
2031typedef union {
2032 uint8_t b[8];
2033 uint16_t w[4];
2034 int16_t sw[4];
2035 uint32_t l[2];
2036 float64 d;
2037} vis64;
2038
2039typedef union {
2040 uint8_t b[4];
2041 uint16_t w[2];
2042 uint32_t l;
2043 float32 f;
2044} vis32;
2045
2046void OPPROTO op_fpmerge(void)
2047{
2048 vis64 s, d;
2049
2050 s.d = DT0;
2051 d.d = DT1;
2052
2053 // Reverse calculation order to handle overlap
2054 d.VIS_B64(7) = s.VIS_B64(3);
2055 d.VIS_B64(6) = d.VIS_B64(3);
2056 d.VIS_B64(5) = s.VIS_B64(2);
2057 d.VIS_B64(4) = d.VIS_B64(2);
2058 d.VIS_B64(3) = s.VIS_B64(1);
2059 d.VIS_B64(2) = d.VIS_B64(1);
2060 d.VIS_B64(1) = s.VIS_B64(0);
2061 //d.VIS_B64(0) = d.VIS_B64(0);
2062
2063 DT0 = d.d;
2064}
2065
2066void OPPROTO op_fmul8x16(void)
2067{
2068 vis64 s, d;
2069 uint32_t tmp;
2070
2071 s.d = DT0;
2072 d.d = DT1;
2073
2074#define PMUL(r) \
2075 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
2076 if ((tmp & 0xff) > 0x7f) \
2077 tmp += 0x100; \
2078 d.VIS_W64(r) = tmp >> 8;
2079
2080 PMUL(0);
2081 PMUL(1);
2082 PMUL(2);
2083 PMUL(3);
2084#undef PMUL
2085
2086 DT0 = d.d;
2087}
2088
2089void OPPROTO op_fmul8x16al(void)
2090{
2091 vis64 s, d;
2092 uint32_t tmp;
2093
2094 s.d = DT0;
2095 d.d = DT1;
2096
2097#define PMUL(r) \
2098 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
2099 if ((tmp & 0xff) > 0x7f) \
2100 tmp += 0x100; \
2101 d.VIS_W64(r) = tmp >> 8;
2102
2103 PMUL(0);
2104 PMUL(1);
2105 PMUL(2);
2106 PMUL(3);
2107#undef PMUL
2108
2109 DT0 = d.d;
3299908c 2110}
e9ebed4d
BS		 2111
2112void OPPROTO op_fmul8x16au(void)
2113{
2114 vis64 s, d;
2115 uint32_t tmp;
2116
2117 s.d = DT0;
2118 d.d = DT1;
2119
2120#define PMUL(r) \
2121 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
2122 if ((tmp & 0xff) > 0x7f) \
2123 tmp += 0x100; \
2124 d.VIS_W64(r) = tmp >> 8;
2125
2126 PMUL(0);
2127 PMUL(1);
2128 PMUL(2);
2129 PMUL(3);
2130#undef PMUL
2131
2132 DT0 = d.d;
2133}
2134
2135void OPPROTO op_fmul8sux16(void)
2136{
2137 vis64 s, d;
2138 uint32_t tmp;
2139
2140 s.d = DT0;
2141 d.d = DT1;
2142
2143#define PMUL(r) \
2144 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
2145 if ((tmp & 0xff) > 0x7f) \
2146 tmp += 0x100; \
2147 d.VIS_W64(r) = tmp >> 8;
2148
2149 PMUL(0);
2150 PMUL(1);
2151 PMUL(2);
2152 PMUL(3);
2153#undef PMUL
2154
2155 DT0 = d.d;
2156}
2157
2158void OPPROTO op_fmul8ulx16(void)
2159{
2160 vis64 s, d;
2161 uint32_t tmp;
2162
2163 s.d = DT0;
2164 d.d = DT1;
2165
2166#define PMUL(r) \
2167 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
2168 if ((tmp & 0xff) > 0x7f) \
2169 tmp += 0x100; \
2170 d.VIS_W64(r) = tmp >> 8;
2171
2172 PMUL(0);
2173 PMUL(1);
2174 PMUL(2);
2175 PMUL(3);
2176#undef PMUL
2177
2178 DT0 = d.d;
2179}
2180
2181void OPPROTO op_fmuld8sux16(void)
2182{
2183 vis64 s, d;
2184 uint32_t tmp;
2185
2186 s.d = DT0;
2187 d.d = DT1;
2188
2189#define PMUL(r) \
2190 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
2191 if ((tmp & 0xff) > 0x7f) \
2192 tmp += 0x100; \
2193 d.VIS_L64(r) = tmp;
2194
2195 // Reverse calculation order to handle overlap
2196 PMUL(1);
2197 PMUL(0);
2198#undef PMUL
2199
2200 DT0 = d.d;
2201}
2202
2203void OPPROTO op_fmuld8ulx16(void)
2204{
2205 vis64 s, d;
2206 uint32_t tmp;
2207
2208 s.d = DT0;
2209 d.d = DT1;
2210
2211#define PMUL(r) \
2212 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
2213 if ((tmp & 0xff) > 0x7f) \
2214 tmp += 0x100; \
2215 d.VIS_L64(r) = tmp;
2216
2217 // Reverse calculation order to handle overlap
2218 PMUL(1);
2219 PMUL(0);
2220#undef PMUL
2221
2222 DT0 = d.d;
2223}
2224
2225void OPPROTO op_fexpand(void)
2226{
2227 vis32 s;
2228 vis64 d;
2229
2230 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
2231 d.d = DT1;
2232 d.VIS_L64(0) = s.VIS_W32(0) << 4;
2233 d.VIS_L64(1) = s.VIS_W32(1) << 4;
2234 d.VIS_L64(2) = s.VIS_W32(2) << 4;
2235 d.VIS_L64(3) = s.VIS_W32(3) << 4;
2236
2237 DT0 = d.d;
2238}
2239
2240#define VIS_OP(name, F) \
2241 void OPPROTO name##16(void) \
2242 { \
2243 vis64 s, d; \
2244 \
2245 s.d = DT0; \
2246 d.d = DT1; \
2247 \
2248 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
2249 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
2250 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
2251 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
2252 \
2253 DT0 = d.d; \
2254 } \
2255 \
2256 void OPPROTO name##16s(void) \
2257 { \
2258 vis32 s, d; \
2259 \
2260 s.f = FT0; \
2261 d.f = FT1; \
2262 \
2263 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
2264 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
2265 \
2266 FT0 = d.f; \
2267 } \
2268 \
2269 void OPPROTO name##32(void) \
2270 { \
2271 vis64 s, d; \
2272 \
2273 s.d = DT0; \
2274 d.d = DT1; \
2275 \
2276 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
2277 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
2278 \
2279 DT0 = d.d; \
2280 } \
2281 \
2282 void OPPROTO name##32s(void) \
2283 { \
2284 vis32 s, d; \
2285 \
2286 s.f = FT0; \
2287 d.f = FT1; \
2288 \
2289 d.l = F(d.l, s.l); \
2290 \
2291 FT0 = d.f; \
2292 }
2293
2294#define FADD(a, b) ((a) + (b))
2295#define FSUB(a, b) ((a) - (b))
2296VIS_OP(op_fpadd, FADD)
2297VIS_OP(op_fpsub, FSUB)
2298
2299#define VIS_CMPOP(name, F) \
2300 void OPPROTO name##16(void) \
2301 { \
2302 vis64 s, d; \
2303 \
2304 s.d = DT0; \
2305 d.d = DT1; \
2306 \
2307 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
2308 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
2309 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
2310 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
2311 \
2312 DT0 = d.d; \
2313 } \
2314 \
2315 void OPPROTO name##32(void) \
2316 { \
2317 vis64 s, d; \
2318 \
2319 s.d = DT0; \
2320 d.d = DT1; \
2321 \
2322 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
2323 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
2324 \
2325 DT0 = d.d; \
2326 }
2327
2328#define FCMPGT(a, b) ((a) > (b))
2329#define FCMPEQ(a, b) ((a) == (b))
2330#define FCMPLE(a, b) ((a) <= (b))
2331#define FCMPNE(a, b) ((a) != (b))
2332
2333VIS_CMPOP(op_fcmpgt, FCMPGT)
2334VIS_CMPOP(op_fcmpeq, FCMPEQ)
2335VIS_CMPOP(op_fcmple, FCMPLE)
2336VIS_CMPOP(op_fcmpne, FCMPNE)
2337
725cb90b 2338#endif
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