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Emulate a serial bluetooth HCI with H4+ extensions and attach to n8x0's UART.
[qemu.git] / hw / vga.c
CommitLineData
e89f66ec 1/*
4fa0f5d2 2 * QEMU VGA Emulator.
5fafdf24 3 *
e89f66ec 4 * Copyright (c) 2003 Fabrice Bellard
5fafdf24 5 *
e89f66ec
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB		 24#include "hw.h"
25#include "console.h"
26#include "pc.h"
27#include "pci.h"
798b0c25 28#include "vga_int.h"
94470844 29#include "pixel_ops.h"
cb5a7aa8 30#include "qemu-timer.h"
e89f66ec 31
e89f66ec 32//#define DEBUG_VGA
17b0018b 33//#define DEBUG_VGA_MEM
a41bc9af
FB		 34//#define DEBUG_VGA_REG
35
4fa0f5d2
FB		 36//#define DEBUG_BOCHS_VBE
37
e89f66ec 38/* force some bits to zero */
798b0c25 39const uint8_t sr_mask[8] = {
e89f66ec
FB		 40 (uint8_t)~0xfc,
41 (uint8_t)~0xc2,
42 (uint8_t)~0xf0,
43 (uint8_t)~0xc0,
44 (uint8_t)~0xf1,
45 (uint8_t)~0xff,
46 (uint8_t)~0xff,
47 (uint8_t)~0x00,
48};
49
798b0c25 50const uint8_t gr_mask[16] = {
e89f66ec
FB		 51 (uint8_t)~0xf0, /* 0x00 */
52 (uint8_t)~0xf0, /* 0x01 */
53 (uint8_t)~0xf0, /* 0x02 */
54 (uint8_t)~0xe0, /* 0x03 */
55 (uint8_t)~0xfc, /* 0x04 */
56 (uint8_t)~0x84, /* 0x05 */
57 (uint8_t)~0xf0, /* 0x06 */
58 (uint8_t)~0xf0, /* 0x07 */
59 (uint8_t)~0x00, /* 0x08 */
60 (uint8_t)~0xff, /* 0x09 */
61 (uint8_t)~0xff, /* 0x0a */
62 (uint8_t)~0xff, /* 0x0b */
63 (uint8_t)~0xff, /* 0x0c */
64 (uint8_t)~0xff, /* 0x0d */
65 (uint8_t)~0xff, /* 0x0e */
66 (uint8_t)~0xff, /* 0x0f */
67};
68
69#define cbswap_32(__x) \
70((uint32_t)( \
71 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
72 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
73 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
74 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
75
b8ed223b 76#ifdef WORDS_BIGENDIAN
e89f66ec
FB		 77#define PAT(x) cbswap_32(x)
78#else
79#define PAT(x) (x)
80#endif
81
b8ed223b
FB		 82#ifdef WORDS_BIGENDIAN
83#define BIG 1
84#else
85#define BIG 0
86#endif
87
88#ifdef WORDS_BIGENDIAN
89#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
90#else
91#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
92#endif
93
e89f66ec
FB		 94static const uint32_t mask16[16] = {
95 PAT(0x00000000),
96 PAT(0x000000ff),
97 PAT(0x0000ff00),
98 PAT(0x0000ffff),
99 PAT(0x00ff0000),
100 PAT(0x00ff00ff),
101 PAT(0x00ffff00),
102 PAT(0x00ffffff),
103 PAT(0xff000000),
104 PAT(0xff0000ff),
105 PAT(0xff00ff00),
106 PAT(0xff00ffff),
107 PAT(0xffff0000),
108 PAT(0xffff00ff),
109 PAT(0xffffff00),
110 PAT(0xffffffff),
111};
112
113#undef PAT
114
b8ed223b 115#ifdef WORDS_BIGENDIAN
e89f66ec
FB		 116#define PAT(x) (x)
117#else
118#define PAT(x) cbswap_32(x)
119#endif
120
121static const uint32_t dmask16[16] = {
122 PAT(0x00000000),
123 PAT(0x000000ff),
124 PAT(0x0000ff00),
125 PAT(0x0000ffff),
126 PAT(0x00ff0000),
127 PAT(0x00ff00ff),
128 PAT(0x00ffff00),
129 PAT(0x00ffffff),
130 PAT(0xff000000),
131 PAT(0xff0000ff),
132 PAT(0xff00ff00),
133 PAT(0xff00ffff),
134 PAT(0xffff0000),
135 PAT(0xffff00ff),
136 PAT(0xffffff00),
137 PAT(0xffffffff),
138};
139
140static const uint32_t dmask4[4] = {
141 PAT(0x00000000),
142 PAT(0x0000ffff),
143 PAT(0xffff0000),
144 PAT(0xffffffff),
145};
146
147static uint32_t expand4[256];
148static uint16_t expand2[256];
17b0018b 149static uint8_t expand4to8[16];
e89f66ec 150
95219897
PB		 151static void vga_screen_dump(void *opaque, const char *filename);
152
cb5a7aa8 153static void vga_dumb_update_retrace_info(VGAState *s)
154{
155 (void) s;
156}
157
158static void vga_precise_update_retrace_info(VGAState *s)
159{
160 int htotal_chars;
161 int hretr_start_char;
162 int hretr_skew_chars;
163 int hretr_end_char;
164
165 int vtotal_lines;
166 int vretr_start_line;
167 int vretr_end_line;
168
169 int div2, sldiv2, dots;
170 int clocking_mode;
171 int clock_sel;
172 const int hz[] = {25175000, 28322000, 25175000, 25175000};
173 int64_t chars_per_sec;
174 struct vga_precise_retrace *r = &s->retrace_info.precise;
175
176 htotal_chars = s->cr[0x00] + 5;
177 hretr_start_char = s->cr[0x04];
178 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
179 hretr_end_char = s->cr[0x05] & 0x1f;
180
181 vtotal_lines = (s->cr[0x06]
182 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
183 ;
184 vretr_start_line = s->cr[0x10]
185 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
186 ;
187 vretr_end_line = s->cr[0x11] & 0xf;
188
189
190 div2 = (s->cr[0x17] >> 2) & 1;
191 sldiv2 = (s->cr[0x17] >> 3) & 1;
192
193 clocking_mode = (s->sr[0x01] >> 3) & 1;
194 clock_sel = (s->msr >> 2) & 3;
f87fc09b 195 dots = (s->msr & 1) ? 8 : 9;
cb5a7aa8 196
197 chars_per_sec = hz[clock_sel] / dots;
198
199 htotal_chars <<= clocking_mode;
200
201 r->total_chars = vtotal_lines * htotal_chars;
202 r->total_chars = (vretr_start_line + vretr_end_line + 1) * htotal_chars;
203 if (r->freq) {
204 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
205 } else {
206 r->ticks_per_char = ticks_per_sec / chars_per_sec;
207 }
208
209 r->vstart = vretr_start_line;
210 r->vend = r->vstart + vretr_end_line + 1;
211
212 r->hstart = hretr_start_char + hretr_skew_chars;
213 r->hend = r->hstart + hretr_end_char + 1;
214 r->htotal = htotal_chars;
215
f87fc09b 216#if 0
cb5a7aa8 217 printf("hz=%f\n",
cb5a7aa8 218 printf (
f87fc09b 219 "hz=%f\n"
cb5a7aa8 220 "htotal = %d\n"
221 "hretr_start = %d\n"
222 "hretr_skew = %d\n"
223 "hretr_end = %d\n"
224 "vtotal = %d\n"
225 "vretr_start = %d\n"
226 "vretr_end = %d\n"
227 "div2 = %d sldiv2 = %d\n"
228 "clocking_mode = %d\n"
229 "clock_sel = %d %d\n"
230 "dots = %d\n"
231 "ticks/char = %lld\n"
232 "\n",
f87fc09b 233 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
cb5a7aa8 234 htotal_chars,
235 hretr_start_char,
236 hretr_skew_chars,
237 hretr_end_char,
238 vtotal_lines,
239 vretr_start_line,
240 vretr_end_line,
241 div2, sldiv2,
242 clocking_mode,
243 clock_sel,
244 hz[clock_sel],
245 dots,
246 r->ticks_per_char
247 );
248#endif
249}
250
251static uint8_t vga_precise_retrace(VGAState *s)
252{
253 struct vga_precise_retrace *r = &s->retrace_info.precise;
254 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
255
256 if (r->total_chars) {
257 int cur_line, cur_line_char, cur_char;
258 int64_t cur_tick;
259
260 cur_tick = qemu_get_clock(vm_clock);
261
262 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
263 cur_line = cur_char / r->htotal;
264
265 if (cur_line >= r->vstart && cur_line <= r->vend) {
266 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
f87fc09b 267 } else {
268 cur_line_char = cur_char % r->htotal;
269 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
270 val |= ST01_DISP_ENABLE;
271 }
cb5a7aa8 272 }
273
274 return val;
275 } else {
276 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
277 }
278}
279
280static uint8_t vga_dumb_retrace(VGAState *s)
281{
282 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
283}
284
0f35920c 285static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
e89f66ec 286{
0f35920c 287 VGAState *s = opaque;
e89f66ec
FB		 288 int val, index;
289
290 /* check port range access depending on color/monochrome mode */
291 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
292 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
293 val = 0xff;
294 } else {
295 switch(addr) {
296 case 0x3c0:
297 if (s->ar_flip_flop == 0) {
298 val = s->ar_index;
299 } else {
300 val = 0;
301 }
302 break;
303 case 0x3c1:
304 index = s->ar_index & 0x1f;
5fafdf24 305 if (index < 21)
e89f66ec
FB		 306 val = s->ar[index];
307 else
308 val = 0;
309 break;
310 case 0x3c2:
311 val = s->st00;
312 break;
313 case 0x3c4:
314 val = s->sr_index;
315 break;
316 case 0x3c5:
317 val = s->sr[s->sr_index];
a41bc9af
FB		 318#ifdef DEBUG_VGA_REG
319 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
320#endif
e89f66ec
FB		 321 break;
322 case 0x3c7:
323 val = s->dac_state;
324 break;
e6eccb38
FB		 325 case 0x3c8:
326 val = s->dac_write_index;
327 break;
e89f66ec
FB		 328 case 0x3c9:
329 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
330 if (++s->dac_sub_index == 3) {
331 s->dac_sub_index = 0;
332 s->dac_read_index++;
333 }
334 break;
335 case 0x3ca:
336 val = s->fcr;
337 break;
338 case 0x3cc:
339 val = s->msr;
340 break;
341 case 0x3ce:
342 val = s->gr_index;
343 break;
344 case 0x3cf:
345 val = s->gr[s->gr_index];
a41bc9af
FB		 346#ifdef DEBUG_VGA_REG
347 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
348#endif
e89f66ec
FB		 349 break;
350 case 0x3b4:
351 case 0x3d4:
352 val = s->cr_index;
353 break;
354 case 0x3b5:
355 case 0x3d5:
356 val = s->cr[s->cr_index];
a41bc9af
FB		 357#ifdef DEBUG_VGA_REG
358 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
a41bc9af 359#endif
e89f66ec
FB		 360 break;
361 case 0x3ba:
362 case 0x3da:
363 /* just toggle to fool polling */
cb5a7aa8 364 val = s->st01 = s->retrace(s);
e89f66ec
FB		 365 s->ar_flip_flop = 0;
366 break;
367 default:
368 val = 0x00;
369 break;
370 }
371 }
4fa0f5d2 372#if defined(DEBUG_VGA)
e89f66ec
FB		 373 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
374#endif
375 return val;
376}
377
0f35920c 378static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e89f66ec 379{
0f35920c 380 VGAState *s = opaque;
5467a722 381 int index;
e89f66ec
FB		 382
383 /* check port range access depending on color/monochrome mode */
384 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
385 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
386 return;
387
388#ifdef DEBUG_VGA
389 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
390#endif
391
392 switch(addr) {
393 case 0x3c0:
394 if (s->ar_flip_flop == 0) {
395 val &= 0x3f;
396 s->ar_index = val;
397 } else {
398 index = s->ar_index & 0x1f;
399 switch(index) {
400 case 0x00 ... 0x0f:
401 s->ar[index] = val & 0x3f;
402 break;
403 case 0x10:
404 s->ar[index] = val & ~0x10;
405 break;
406 case 0x11:
407 s->ar[index] = val;
408 break;
409 case 0x12:
410 s->ar[index] = val & ~0xc0;
411 break;
412 case 0x13:
413 s->ar[index] = val & ~0xf0;
414 break;
415 case 0x14:
416 s->ar[index] = val & ~0xf0;
417 break;
418 default:
419 break;
420 }
421 }
422 s->ar_flip_flop ^= 1;
423 break;
424 case 0x3c2:
425 s->msr = val & ~0x10;
cb5a7aa8 426 s->update_retrace_info(s);
e89f66ec
FB		 427 break;
428 case 0x3c4:
429 s->sr_index = val & 7;
430 break;
431 case 0x3c5:
a41bc9af
FB		 432#ifdef DEBUG_VGA_REG
433 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
434#endif
e89f66ec 435 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
cb5a7aa8 436 if (s->sr_index == 1) s->update_retrace_info(s);
e89f66ec
FB		 437 break;
438 case 0x3c7:
439 s->dac_read_index = val;
440 s->dac_sub_index = 0;
441 s->dac_state = 3;
442 break;
443 case 0x3c8:
444 s->dac_write_index = val;
445 s->dac_sub_index = 0;
446 s->dac_state = 0;
447 break;
448 case 0x3c9:
449 s->dac_cache[s->dac_sub_index] = val;
450 if (++s->dac_sub_index == 3) {
451 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
452 s->dac_sub_index = 0;
453 s->dac_write_index++;
454 }
455 break;
456 case 0x3ce:
457 s->gr_index = val & 0x0f;
458 break;
459 case 0x3cf:
a41bc9af
FB		 460#ifdef DEBUG_VGA_REG
461 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
462#endif
e89f66ec
FB		 463 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
464 break;
465 case 0x3b4:
466 case 0x3d4:
467 s->cr_index = val;
468 break;
469 case 0x3b5:
470 case 0x3d5:
a41bc9af
FB		 471#ifdef DEBUG_VGA_REG
472 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
473#endif
e89f66ec 474 /* handle CR0-7 protection */
f6c958c8 475 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
e89f66ec
FB		 476 /* can always write bit 4 of CR7 */
477 if (s->cr_index == 7)
478 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
479 return;
480 }
481 switch(s->cr_index) {
482 case 0x01: /* horizontal display end */
483 case 0x07:
484 case 0x09:
485 case 0x0c:
486 case 0x0d:
e91c8a77 487 case 0x12: /* vertical display end */
e89f66ec
FB		 488 s->cr[s->cr_index] = val;
489 break;
e89f66ec
FB		 490 default:
491 s->cr[s->cr_index] = val;
492 break;
493 }
cb5a7aa8 494
495 switch(s->cr_index) {
496 case 0x00:
497 case 0x04:
498 case 0x05:
499 case 0x06:
500 case 0x07:
501 case 0x11:
502 case 0x17:
503 s->update_retrace_info(s);
504 break;
505 }
e89f66ec
FB		 506 break;
507 case 0x3ba:
508 case 0x3da:
509 s->fcr = val & 0x10;
510 break;
511 }
512}
513
4fa0f5d2 514#ifdef CONFIG_BOCHS_VBE
09a79b49 515static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
4fa0f5d2 516{
0f35920c 517 VGAState *s = opaque;
4fa0f5d2 518 uint32_t val;
09a79b49
FB		 519 val = s->vbe_index;
520 return val;
521}
4fa0f5d2 522
09a79b49
FB		 523static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
524{
525 VGAState *s = opaque;
526 uint32_t val;
527
8454df8b
FB		 528 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
529 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
530 switch(s->vbe_index) {
531 /* XXX: do not hardcode ? */
532 case VBE_DISPI_INDEX_XRES:
533 val = VBE_DISPI_MAX_XRES;
534 break;
535 case VBE_DISPI_INDEX_YRES:
536 val = VBE_DISPI_MAX_YRES;
537 break;
538 case VBE_DISPI_INDEX_BPP:
539 val = VBE_DISPI_MAX_BPP;
540 break;
541 default:
5fafdf24 542 val = s->vbe_regs[s->vbe_index];
8454df8b
FB		 543 break;
544 }
545 } else {
5fafdf24 546 val = s->vbe_regs[s->vbe_index];
8454df8b
FB		 547 }
548 } else {
09a79b49 549 val = 0;
8454df8b 550 }
4fa0f5d2 551#ifdef DEBUG_BOCHS_VBE
09a79b49 552 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
4fa0f5d2 553#endif
4fa0f5d2
FB		 554 return val;
555}
556
09a79b49
FB		 557static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
558{
559 VGAState *s = opaque;
560 s->vbe_index = val;
561}
562
563static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
4fa0f5d2 564{
0f35920c 565 VGAState *s = opaque;
4fa0f5d2 566
09a79b49 567 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
4fa0f5d2
FB		 568#ifdef DEBUG_BOCHS_VBE
569 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
570#endif
571 switch(s->vbe_index) {
572 case VBE_DISPI_INDEX_ID:
cae61cef
FB		 573 if (val == VBE_DISPI_ID0 ||
574 val == VBE_DISPI_ID1 ||
37dd208d
FB		 575 val == VBE_DISPI_ID2 ||
576 val == VBE_DISPI_ID3 ||
577 val == VBE_DISPI_ID4) {
cae61cef
FB		 578 s->vbe_regs[s->vbe_index] = val;
579 }
4fa0f5d2
FB		 580 break;
581 case VBE_DISPI_INDEX_XRES:
cae61cef
FB		 582 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
583 s->vbe_regs[s->vbe_index] = val;
584 }
4fa0f5d2
FB		 585 break;
586 case VBE_DISPI_INDEX_YRES:
cae61cef
FB		 587 if (val <= VBE_DISPI_MAX_YRES) {
588 s->vbe_regs[s->vbe_index] = val;
589 }
4fa0f5d2
FB		 590 break;
591 case VBE_DISPI_INDEX_BPP:
592 if (val == 0)
593 val = 8;
5fafdf24 594 if (val == 4 || val == 8 || val == 15 ||
cae61cef
FB		 595 val == 16 || val == 24 || val == 32) {
596 s->vbe_regs[s->vbe_index] = val;
597 }
4fa0f5d2
FB		 598 break;
599 case VBE_DISPI_INDEX_BANK:
42fc925e
FB		 600 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
601 val &= (s->vbe_bank_mask >> 2);
602 } else {
603 val &= s->vbe_bank_mask;
604 }
cae61cef 605 s->vbe_regs[s->vbe_index] = val;
26aa7d72 606 s->bank_offset = (val << 16);
4fa0f5d2
FB		 607 break;
608 case VBE_DISPI_INDEX_ENABLE:
8454df8b
FB		 609 if ((val & VBE_DISPI_ENABLED) &&
610 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
4fa0f5d2
FB		 611 int h, shift_control;
612
5fafdf24 613 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
4fa0f5d2 614 s->vbe_regs[VBE_DISPI_INDEX_XRES];
5fafdf24 615 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
4fa0f5d2
FB		 616 s->vbe_regs[VBE_DISPI_INDEX_YRES];
617 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
618 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
3b46e624 619
4fa0f5d2
FB		 620 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
621 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
622 else
5fafdf24 623 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
4fa0f5d2
FB		 624 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
625 s->vbe_start_addr = 0;
8454df8b 626
4fa0f5d2
FB		 627 /* clear the screen (should be done in BIOS) */
628 if (!(val & VBE_DISPI_NOCLEARMEM)) {
5fafdf24 629 memset(s->vram_ptr, 0,
4fa0f5d2
FB		 630 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
631 }
3b46e624 632
cae61cef
FB		 633 /* we initialize the VGA graphic mode (should be done
634 in BIOS) */
635 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
4fa0f5d2
FB		 636 s->cr[0x17] |= 3; /* no CGA modes */
637 s->cr[0x13] = s->vbe_line_offset >> 3;
638 /* width */
639 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
8454df8b 640 /* height (only meaningful if < 1024) */
4fa0f5d2
FB		 641 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
642 s->cr[0x12] = h;
5fafdf24 643 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
4fa0f5d2
FB		 644 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
645 /* line compare to 1023 */
646 s->cr[0x18] = 0xff;
647 s->cr[0x07] |= 0x10;
648 s->cr[0x09] |= 0x40;
3b46e624 649
4fa0f5d2
FB		 650 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
651 shift_control = 0;
652 s->sr[0x01] &= ~8; /* no double line */
653 } else {
654 shift_control = 2;
646be93b 655 s->sr[4] |= 0x08; /* set chain 4 mode */
141253b2 656 s->sr[2] |= 0x0f; /* activate all planes */
4fa0f5d2
FB		 657 }
658 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
659 s->cr[0x09] &= ~0x9f; /* no double scan */
cae61cef
FB		 660 } else {
661 /* XXX: the bios should do that */
26aa7d72 662 s->bank_offset = 0;
cae61cef 663 }
37dd208d 664 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
141253b2 665 s->vbe_regs[s->vbe_index] = val;
cae61cef
FB		 666 break;
667 case VBE_DISPI_INDEX_VIRT_WIDTH:
668 {
669 int w, h, line_offset;
670
671 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
672 return;
673 w = val;
674 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
675 line_offset = w >> 1;
676 else
677 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
678 h = s->vram_size / line_offset;
679 /* XXX: support weird bochs semantics ? */
680 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
681 return;
682 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
683 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
684 s->vbe_line_offset = line_offset;
685 }
686 break;
687 case VBE_DISPI_INDEX_X_OFFSET:
688 case VBE_DISPI_INDEX_Y_OFFSET:
689 {
690 int x;
691 s->vbe_regs[s->vbe_index] = val;
692 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
693 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
694 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
695 s->vbe_start_addr += x >> 1;
696 else
697 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr >>= 2;
4fa0f5d2
FB		 699 }
700 break;
701 default:
702 break;
703 }
4fa0f5d2
FB		 704 }
705}
706#endif
707
e89f66ec 708/* called for accesses between 0xa0000 and 0xc0000 */
798b0c25 709uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
e89f66ec 710{
a4193c8a 711 VGAState *s = opaque;
e89f66ec
FB		 712 int memory_map_mode, plane;
713 uint32_t ret;
3b46e624 714
e89f66ec
FB		 715 /* convert to VGA memory offset */
716 memory_map_mode = (s->gr[6] >> 2) & 3;
26aa7d72 717 addr &= 0x1ffff;
e89f66ec
FB		 718 switch(memory_map_mode) {
719 case 0:
e89f66ec
FB		 720 break;
721 case 1:
26aa7d72 722 if (addr >= 0x10000)
e89f66ec 723 return 0xff;
cae61cef 724 addr += s->bank_offset;
e89f66ec
FB		 725 break;
726 case 2:
26aa7d72 727 addr -= 0x10000;
e89f66ec
FB		 728 if (addr >= 0x8000)
729 return 0xff;
730 break;
731 default:
732 case 3:
26aa7d72 733 addr -= 0x18000;
c92b2e84
FB		 734 if (addr >= 0x8000)
735 return 0xff;
e89f66ec
FB		 736 break;
737 }
3b46e624 738
e89f66ec
FB		 739 if (s->sr[4] & 0x08) {
740 /* chain 4 mode : simplest access */
741 ret = s->vram_ptr[addr];
742 } else if (s->gr[5] & 0x10) {
743 /* odd/even mode (aka text mode mapping) */
744 plane = (s->gr[4] & 2) | (addr & 1);
745 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
746 } else {
747 /* standard VGA latched access */
748 s->latch = ((uint32_t *)s->vram_ptr)[addr];
749
750 if (!(s->gr[5] & 0x08)) {
751 /* read mode 0 */
752 plane = s->gr[4];
b8ed223b 753 ret = GET_PLANE(s->latch, plane);
e89f66ec
FB		 754 } else {
755 /* read mode 1 */
756 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
757 ret |= ret >> 16;
758 ret |= ret >> 8;
759 ret = (~ret) & 0xff;
760 }
761 }
762 return ret;
763}
764
a4193c8a 765static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
e89f66ec
FB		 766{
767 uint32_t v;
09a79b49 768#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a
FB		 769 v = vga_mem_readb(opaque, addr) << 8;
770 v |= vga_mem_readb(opaque, addr + 1);
09a79b49 771#else
a4193c8a
FB		 772 v = vga_mem_readb(opaque, addr);
773 v |= vga_mem_readb(opaque, addr + 1) << 8;
09a79b49 774#endif
e89f66ec
FB		 775 return v;
776}
777
a4193c8a 778static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
e89f66ec
FB		 779{
780 uint32_t v;
09a79b49 781#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a
FB		 782 v = vga_mem_readb(opaque, addr) << 24;
783 v |= vga_mem_readb(opaque, addr + 1) << 16;
784 v |= vga_mem_readb(opaque, addr + 2) << 8;
785 v |= vga_mem_readb(opaque, addr + 3);
09a79b49 786#else
a4193c8a
FB		 787 v = vga_mem_readb(opaque, addr);
788 v |= vga_mem_readb(opaque, addr + 1) << 8;
789 v |= vga_mem_readb(opaque, addr + 2) << 16;
790 v |= vga_mem_readb(opaque, addr + 3) << 24;
09a79b49 791#endif
e89f66ec
FB		 792 return v;
793}
794
e89f66ec 795/* called for accesses between 0xa0000 and 0xc0000 */
798b0c25 796void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
e89f66ec 797{
a4193c8a 798 VGAState *s = opaque;
546fa6ab 799 int memory_map_mode, plane, write_mode, b, func_select, mask;
e89f66ec
FB		 800 uint32_t write_mask, bit_mask, set_mask;
801
17b0018b 802#ifdef DEBUG_VGA_MEM
e89f66ec
FB		 803 printf("vga: [0x%x] = 0x%02x\n", addr, val);
804#endif
805 /* convert to VGA memory offset */
806 memory_map_mode = (s->gr[6] >> 2) & 3;
26aa7d72 807 addr &= 0x1ffff;
e89f66ec
FB		 808 switch(memory_map_mode) {
809 case 0:
e89f66ec
FB		 810 break;
811 case 1:
26aa7d72 812 if (addr >= 0x10000)
e89f66ec 813 return;
cae61cef 814 addr += s->bank_offset;
e89f66ec
FB		 815 break;
816 case 2:
26aa7d72 817 addr -= 0x10000;
e89f66ec
FB		 818 if (addr >= 0x8000)
819 return;
820 break;
821 default:
822 case 3:
26aa7d72 823 addr -= 0x18000;
c92b2e84
FB		 824 if (addr >= 0x8000)
825 return;
e89f66ec
FB		 826 break;
827 }
3b46e624 828
e89f66ec
FB		 829 if (s->sr[4] & 0x08) {
830 /* chain 4 mode : simplest access */
831 plane = addr & 3;
546fa6ab
FB		 832 mask = (1 << plane);
833 if (s->sr[2] & mask) {
e89f66ec 834 s->vram_ptr[addr] = val;
17b0018b 835#ifdef DEBUG_VGA_MEM
e89f66ec
FB		 836 printf("vga: chain4: [0x%x]\n", addr);
837#endif
546fa6ab 838 s->plane_updated |= mask; /* only used to detect font change */
4fa0f5d2 839 cpu_physical_memory_set_dirty(s->vram_offset + addr);
e89f66ec
FB		 840 }
841 } else if (s->gr[5] & 0x10) {
842 /* odd/even mode (aka text mode mapping) */
843 plane = (s->gr[4] & 2) | (addr & 1);
546fa6ab
FB		 844 mask = (1 << plane);
845 if (s->sr[2] & mask) {
e89f66ec
FB		 846 addr = ((addr & ~1) << 1) | plane;
847 s->vram_ptr[addr] = val;
17b0018b 848#ifdef DEBUG_VGA_MEM
e89f66ec
FB		 849 printf("vga: odd/even: [0x%x]\n", addr);
850#endif
546fa6ab 851 s->plane_updated |= mask; /* only used to detect font change */
4fa0f5d2 852 cpu_physical_memory_set_dirty(s->vram_offset + addr);
e89f66ec
FB		 853 }
854 } else {
855 /* standard VGA latched access */
856 write_mode = s->gr[5] & 3;
857 switch(write_mode) {
858 default:
859 case 0:
860 /* rotate */
861 b = s->gr[3] & 7;
862 val = ((val >> b) | (val << (8 - b))) & 0xff;
863 val |= val << 8;
864 val |= val << 16;
865
866 /* apply set/reset mask */
867 set_mask = mask16[s->gr[1]];
868 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
869 bit_mask = s->gr[8];
870 break;
871 case 1:
872 val = s->latch;
873 goto do_write;
874 case 2:
875 val = mask16[val & 0x0f];
876 bit_mask = s->gr[8];
877 break;
878 case 3:
879 /* rotate */
880 b = s->gr[3] & 7;
a41bc9af 881 val = (val >> b) | (val << (8 - b));
e89f66ec
FB		 882
883 bit_mask = s->gr[8] & val;
884 val = mask16[s->gr[0]];
885 break;
886 }
887
888 /* apply logical operation */
889 func_select = s->gr[3] >> 3;
890 switch(func_select) {
891 case 0:
892 default:
893 /* nothing to do */
894 break;
895 case 1:
896 /* and */
897 val &= s->latch;
898 break;
899 case 2:
900 /* or */
901 val |= s->latch;
902 break;
903 case 3:
904 /* xor */
905 val ^= s->latch;
906 break;
907 }
908
909 /* apply bit mask */
910 bit_mask |= bit_mask << 8;
911 bit_mask |= bit_mask << 16;
912 val = (val & bit_mask) | (s->latch & ~bit_mask);
913
914 do_write:
915 /* mask data according to sr[2] */
546fa6ab
FB		 916 mask = s->sr[2];
917 s->plane_updated |= mask; /* only used to detect font change */
918 write_mask = mask16[mask];
5fafdf24
TS		 919 ((uint32_t *)s->vram_ptr)[addr] =
920 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
e89f66ec 921 (val & write_mask);
17b0018b 922#ifdef DEBUG_VGA_MEM
5fafdf24 923 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
e89f66ec
FB		 924 addr * 4, write_mask, val);
925#endif
4fa0f5d2 926 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
e89f66ec
FB		 927 }
928}
929
a4193c8a 930static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
e89f66ec 931{
09a79b49 932#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a
FB		 933 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
934 vga_mem_writeb(opaque, addr + 1, val & 0xff);
09a79b49 935#else
a4193c8a
FB		 936 vga_mem_writeb(opaque, addr, val & 0xff);
937 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
09a79b49 938#endif
e89f66ec
FB		 939}
940
a4193c8a 941static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
e89f66ec 942{
09a79b49 943#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a
FB		 944 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
945 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
946 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
947 vga_mem_writeb(opaque, addr + 3, val & 0xff);
09a79b49 948#else
a4193c8a
FB		 949 vga_mem_writeb(opaque, addr, val & 0xff);
950 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
951 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
952 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
09a79b49 953#endif
e89f66ec
FB		 954}
955
e89f66ec
FB		 956typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
957 const uint8_t *font_ptr, int h,
958 uint32_t fgcol, uint32_t bgcol);
959typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
5fafdf24 960 const uint8_t *font_ptr, int h,
e89f66ec 961 uint32_t fgcol, uint32_t bgcol, int dup9);
5fafdf24 962typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
e89f66ec
FB		 963 const uint8_t *s, int width);
964
e89f66ec
FB		 965#define DEPTH 8
966#include "vga_template.h"
967
968#define DEPTH 15
969#include "vga_template.h"
970
a2502b58
BS		 971#define BGR_FORMAT
972#define DEPTH 15
973#include "vga_template.h"
974
975#define DEPTH 16
976#include "vga_template.h"
977
978#define BGR_FORMAT
e89f66ec
FB		 979#define DEPTH 16
980#include "vga_template.h"
981
982#define DEPTH 32
983#include "vga_template.h"
984
d3079cd2
FB		 985#define BGR_FORMAT
986#define DEPTH 32
987#include "vga_template.h"
988
17b0018b
FB		 989static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
990{
991 unsigned int col;
992 col = rgb_to_pixel8(r, g, b);
993 col |= col << 8;
994 col |= col << 16;
995 return col;
996}
997
998static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
999{
1000 unsigned int col;
1001 col = rgb_to_pixel15(r, g, b);
1002 col |= col << 16;
1003 return col;
1004}
1005
b29169d2
BS		 1006static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1007 unsigned int b)
1008{
1009 unsigned int col;
1010 col = rgb_to_pixel15bgr(r, g, b);
1011 col |= col << 16;
1012 return col;
1013}
1014
17b0018b
FB		 1015static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1016{
1017 unsigned int col;
1018 col = rgb_to_pixel16(r, g, b);
1019 col |= col << 16;
1020 return col;
1021}
1022
b29169d2
BS		 1023static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025{
1026 unsigned int col;
1027 col = rgb_to_pixel16bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030}
1031
17b0018b
FB		 1032static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1033{
1034 unsigned int col;
1035 col = rgb_to_pixel32(r, g, b);
1036 return col;
1037}
1038
d3079cd2
FB		 1039static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1040{
1041 unsigned int col;
1042 col = rgb_to_pixel32bgr(r, g, b);
1043 return col;
1044}
1045
e89f66ec
FB		 1046/* return true if the palette was modified */
1047static int update_palette16(VGAState *s)
1048{
17b0018b 1049 int full_update, i;
e89f66ec 1050 uint32_t v, col, *palette;
e89f66ec
FB		 1051
1052 full_update = 0;
1053 palette = s->last_palette;
1054 for(i = 0; i < 16; i++) {
1055 v = s->ar[i];
1056 if (s->ar[0x10] & 0x80)
1057 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1058 else
1059 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1060 v = v * 3;
5fafdf24
TS		 1061 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1062 c6_to_8(s->palette[v + 1]),
17b0018b
FB		 1063 c6_to_8(s->palette[v + 2]));
1064 if (col != palette[i]) {
1065 full_update = 1;
1066 palette[i] = col;
e89f66ec 1067 }
17b0018b
FB		 1068 }
1069 return full_update;
1070}
1071
1072/* return true if the palette was modified */
1073static int update_palette256(VGAState *s)
1074{
1075 int full_update, i;
1076 uint32_t v, col, *palette;
1077
1078 full_update = 0;
1079 palette = s->last_palette;
1080 v = 0;
1081 for(i = 0; i < 256; i++) {
37dd208d 1082 if (s->dac_8bit) {
5fafdf24
TS		 1083 col = s->rgb_to_pixel(s->palette[v],
1084 s->palette[v + 1],
37dd208d
FB		 1085 s->palette[v + 2]);
1086 } else {
5fafdf24
TS		 1087 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1088 c6_to_8(s->palette[v + 1]),
37dd208d
FB		 1089 c6_to_8(s->palette[v + 2]));
1090 }
e89f66ec
FB		 1091 if (col != palette[i]) {
1092 full_update = 1;
1093 palette[i] = col;
1094 }
17b0018b 1095 v += 3;
e89f66ec
FB		 1096 }
1097 return full_update;
1098}
1099
5fafdf24
TS		 1100static void vga_get_offsets(VGAState *s,
1101 uint32_t *pline_offset,
83acc96b
FB		 1102 uint32_t *pstart_addr,
1103 uint32_t *pline_compare)
e89f66ec 1104{
83acc96b 1105 uint32_t start_addr, line_offset, line_compare;
4fa0f5d2
FB		 1106#ifdef CONFIG_BOCHS_VBE
1107 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1108 line_offset = s->vbe_line_offset;
1109 start_addr = s->vbe_start_addr;
83acc96b 1110 line_compare = 65535;
4fa0f5d2
FB		 1111 } else
1112#endif
3b46e624 1113 {
4fa0f5d2
FB		 1114 /* compute line_offset in bytes */
1115 line_offset = s->cr[0x13];
4fa0f5d2 1116 line_offset <<= 3;
08e48902 1117
4fa0f5d2
FB		 1118 /* starting address */
1119 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
83acc96b
FB		 1120
1121 /* line compare */
5fafdf24 1122 line_compare = s->cr[0x18] |
83acc96b
FB		 1123 ((s->cr[0x07] & 0x10) << 4) |
1124 ((s->cr[0x09] & 0x40) << 3);
4fa0f5d2 1125 }
798b0c25
FB		 1126 *pline_offset = line_offset;
1127 *pstart_addr = start_addr;
83acc96b 1128 *pline_compare = line_compare;
798b0c25
FB		 1129}
1130
1131/* update start_addr and line_offset. Return TRUE if modified */
1132static int update_basic_params(VGAState *s)
1133{
1134 int full_update;
1135 uint32_t start_addr, line_offset, line_compare;
3b46e624 1136
798b0c25
FB		 1137 full_update = 0;
1138
83acc96b 1139 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
e89f66ec
FB		 1140
1141 if (line_offset != s->line_offset ||
1142 start_addr != s->start_addr ||
1143 line_compare != s->line_compare) {
1144 s->line_offset = line_offset;
1145 s->start_addr = start_addr;
1146 s->line_compare = line_compare;
1147 full_update = 1;
1148 }
1149 return full_update;
1150}
1151
b29169d2 1152#define NB_DEPTHS 7
d3079cd2
FB		 1153
1154static inline int get_depth_index(DisplayState *s)
e89f66ec 1155{
d3079cd2 1156 switch(s->depth) {
e89f66ec
FB		 1157 default:
1158 case 8:
1159 return 0;
1160 case 15:
b29169d2
BS		 1161 if (s->bgr)
1162 return 5;
1163 else
1164 return 1;
e89f66ec 1165 case 16:
b29169d2
BS		 1166 if (s->bgr)
1167 return 6;
1168 else
1169 return 2;
e89f66ec 1170 case 32:
d3079cd2
FB		 1171 if (s->bgr)
1172 return 4;
1173 else
1174 return 3;
e89f66ec
FB		 1175 }
1176}
1177
d3079cd2 1178static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
e89f66ec
FB		 1179 vga_draw_glyph8_8,
1180 vga_draw_glyph8_16,
1181 vga_draw_glyph8_16,
1182 vga_draw_glyph8_32,
d3079cd2 1183 vga_draw_glyph8_32,
b29169d2
BS		 1184 vga_draw_glyph8_16,
1185 vga_draw_glyph8_16,
e89f66ec
FB		 1186};
1187
d3079cd2 1188static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
17b0018b
FB		 1189 vga_draw_glyph16_8,
1190 vga_draw_glyph16_16,
1191 vga_draw_glyph16_16,
1192 vga_draw_glyph16_32,
d3079cd2 1193 vga_draw_glyph16_32,
b29169d2
BS		 1194 vga_draw_glyph16_16,
1195 vga_draw_glyph16_16,
17b0018b
FB		 1196};
1197
d3079cd2 1198static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
e89f66ec
FB		 1199 vga_draw_glyph9_8,
1200 vga_draw_glyph9_16,
1201 vga_draw_glyph9_16,
1202 vga_draw_glyph9_32,
d3079cd2 1203 vga_draw_glyph9_32,
b29169d2
BS		 1204 vga_draw_glyph9_16,
1205 vga_draw_glyph9_16,
e89f66ec 1206};
3b46e624 1207
e89f66ec
FB		 1208static const uint8_t cursor_glyph[32 * 4] = {
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1219 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1220 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1221 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
3b46e624 1225};
e89f66ec 1226
5fafdf24
TS		 1227/*
1228 * Text mode update
e89f66ec
FB		 1229 * Missing:
1230 * - double scan
5fafdf24 1231 * - double width
e89f66ec
FB		 1232 * - underline
1233 * - flashing
1234 */
1235static void vga_draw_text(VGAState *s, int full_update)
1236{
1237 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1238 int cx_min, cx_max, linesize, x_incr;
1239 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1240 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1241 const uint8_t *font_ptr, *font_base[2];
1242 int dup9, line_offset, depth_index;
1243 uint32_t *palette;
1244 uint32_t *ch_attr_ptr;
1245 vga_draw_glyph8_func *vga_draw_glyph8;
1246 vga_draw_glyph9_func *vga_draw_glyph9;
1247
1248 full_update |= update_palette16(s);
1249 palette = s->last_palette;
3b46e624 1250
e89f66ec
FB		 1251 /* compute font data address (in plane 2) */
1252 v = s->sr[3];
1078f663 1253 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1254 if (offset != s->font_offsets[0]) {
1255 s->font_offsets[0] = offset;
1256 full_update = 1;
1257 }
1258 font_base[0] = s->vram_ptr + offset;
1259
1078f663 1260 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1261 font_base[1] = s->vram_ptr + offset;
1262 if (offset != s->font_offsets[1]) {
1263 s->font_offsets[1] = offset;
1264 full_update = 1;
1265 }
546fa6ab
FB		 1266 if (s->plane_updated & (1 << 2)) {
1267 /* if the plane 2 was modified since the last display, it
1268 indicates the font may have been modified */
1269 s->plane_updated = 0;
1270 full_update = 1;
1271 }
e89f66ec
FB		 1272 full_update |= update_basic_params(s);
1273
1274 line_offset = s->line_offset;
1275 s1 = s->vram_ptr + (s->start_addr * 4);
1276
1277 /* total width & height */
1278 cheight = (s->cr[9] & 0x1f) + 1;
1279 cw = 8;
eccabc6e 1280 if (!(s->sr[1] & 0x01))
e89f66ec 1281 cw = 9;
17b0018b
FB		 1282 if (s->sr[1] & 0x08)
1283 cw = 16; /* NOTE: no 18 pixel wide */
e89f66ec
FB		 1284 x_incr = cw * ((s->ds->depth + 7) >> 3);
1285 width = (s->cr[0x01] + 1);
17b0018b
FB		 1286 if (s->cr[0x06] == 100) {
1287 /* ugly hack for CGA 160x100x16 - explain me the logic */
1288 height = 100;
1289 } else {
5fafdf24
TS		 1290 height = s->cr[0x12] |
1291 ((s->cr[0x07] & 0x02) << 7) |
17b0018b
FB		 1292 ((s->cr[0x07] & 0x40) << 3);
1293 height = (height + 1) / cheight;
1294 }
3294b949
FB		 1295 if ((height * width) > CH_ATTR_SIZE) {
1296 /* better than nothing: exit if transient size is too big */
1297 return;
1298 }
1299
e89f66ec 1300 if (width != s->last_width || height != s->last_height ||
eccabc6e 1301 cw != s->last_cw || cheight != s->last_ch) {
2aebb3eb
FB		 1302 s->last_scr_width = width * cw;
1303 s->last_scr_height = height * cheight;
c60e08d9 1304 qemu_console_resize(s->console, s->last_scr_width, s->last_scr_height);
e89f66ec
FB		 1305 s->last_width = width;
1306 s->last_height = height;
1307 s->last_ch = cheight;
1308 s->last_cw = cw;
1309 full_update = 1;
1310 }
1311 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1312 if (cursor_offset != s->cursor_offset ||
1313 s->cr[0xa] != s->cursor_start ||
1314 s->cr[0xb] != s->cursor_end) {
1315 /* if the cursor position changed, we update the old and new
1316 chars */
1317 if (s->cursor_offset < CH_ATTR_SIZE)
1318 s->last_ch_attr[s->cursor_offset] = -1;
1319 if (cursor_offset < CH_ATTR_SIZE)
1320 s->last_ch_attr[cursor_offset] = -1;
1321 s->cursor_offset = cursor_offset;
1322 s->cursor_start = s->cr[0xa];
1323 s->cursor_end = s->cr[0xb];
1324 }
39cf7803 1325 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
3b46e624 1326
d3079cd2 1327 depth_index = get_depth_index(s->ds);
17b0018b
FB		 1328 if (cw == 16)
1329 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1330 else
1331 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
e89f66ec 1332 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
3b46e624 1333
e89f66ec
FB		 1334 dest = s->ds->data;
1335 linesize = s->ds->linesize;
1336 ch_attr_ptr = s->last_ch_attr;
1337 for(cy = 0; cy < height; cy++) {
1338 d1 = dest;
1339 src = s1;
1340 cx_min = width;
1341 cx_max = -1;
1342 for(cx = 0; cx < width; cx++) {
1343 ch_attr = *(uint16_t *)src;
1344 if (full_update || ch_attr != *ch_attr_ptr) {
1345 if (cx < cx_min)
1346 cx_min = cx;
1347 if (cx > cx_max)
1348 cx_max = cx;
1349 *ch_attr_ptr = ch_attr;
1350#ifdef WORDS_BIGENDIAN
1351 ch = ch_attr >> 8;
1352 cattr = ch_attr & 0xff;
1353#else
1354 ch = ch_attr & 0xff;
1355 cattr = ch_attr >> 8;
1356#endif
1357 font_ptr = font_base[(cattr >> 3) & 1];
1358 font_ptr += 32 * 4 * ch;
1359 bgcol = palette[cattr >> 4];
1360 fgcol = palette[cattr & 0x0f];
17b0018b 1361 if (cw != 9) {
5fafdf24 1362 vga_draw_glyph8(d1, linesize,
e89f66ec
FB		 1363 font_ptr, cheight, fgcol, bgcol);
1364 } else {
1365 dup9 = 0;
1366 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1367 dup9 = 1;
5fafdf24 1368 vga_draw_glyph9(d1, linesize,
e89f66ec
FB		 1369 font_ptr, cheight, fgcol, bgcol, dup9);
1370 }
1371 if (src == cursor_ptr &&
1372 !(s->cr[0x0a] & 0x20)) {
1373 int line_start, line_last, h;
1374 /* draw the cursor */
1375 line_start = s->cr[0x0a] & 0x1f;
1376 line_last = s->cr[0x0b] & 0x1f;
1377 /* XXX: check that */
1378 if (line_last > cheight - 1)
1379 line_last = cheight - 1;
1380 if (line_last >= line_start && line_start < cheight) {
1381 h = line_last - line_start + 1;
1382 d = d1 + linesize * line_start;
17b0018b 1383 if (cw != 9) {
5fafdf24 1384 vga_draw_glyph8(d, linesize,
e89f66ec
FB		 1385 cursor_glyph, h, fgcol, bgcol);
1386 } else {
5fafdf24 1387 vga_draw_glyph9(d, linesize,
e89f66ec
FB		 1388 cursor_glyph, h, fgcol, bgcol, 1);
1389 }
1390 }
1391 }
1392 }
1393 d1 += x_incr;
1394 src += 4;
1395 ch_attr_ptr++;
1396 }
1397 if (cx_max != -1) {
5fafdf24 1398 dpy_update(s->ds, cx_min * cw, cy * cheight,
e89f66ec
FB		 1399 (cx_max - cx_min + 1) * cw, cheight);
1400 }
1401 dest += linesize * cheight;
1402 s1 += line_offset;
1403 }
1404}
1405
17b0018b
FB		 1406enum {
1407 VGA_DRAW_LINE2,
1408 VGA_DRAW_LINE2D2,
1409 VGA_DRAW_LINE4,
1410 VGA_DRAW_LINE4D2,
1411 VGA_DRAW_LINE8D2,
1412 VGA_DRAW_LINE8,
1413 VGA_DRAW_LINE15,
1414 VGA_DRAW_LINE16,
4fa0f5d2 1415 VGA_DRAW_LINE24,
17b0018b
FB		 1416 VGA_DRAW_LINE32,
1417 VGA_DRAW_LINE_NB,
1418};
1419
d3079cd2 1420static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
e89f66ec
FB		 1421 vga_draw_line2_8,
1422 vga_draw_line2_16,
1423 vga_draw_line2_16,
1424 vga_draw_line2_32,
d3079cd2 1425 vga_draw_line2_32,
b29169d2
BS		 1426 vga_draw_line2_16,
1427 vga_draw_line2_16,
e89f66ec 1428
17b0018b
FB		 1429 vga_draw_line2d2_8,
1430 vga_draw_line2d2_16,
1431 vga_draw_line2d2_16,
1432 vga_draw_line2d2_32,
d3079cd2 1433 vga_draw_line2d2_32,
b29169d2
BS		 1434 vga_draw_line2d2_16,
1435 vga_draw_line2d2_16,
17b0018b 1436
e89f66ec
FB		 1437 vga_draw_line4_8,
1438 vga_draw_line4_16,
1439 vga_draw_line4_16,
1440 vga_draw_line4_32,
d3079cd2 1441 vga_draw_line4_32,
b29169d2
BS		 1442 vga_draw_line4_16,
1443 vga_draw_line4_16,
e89f66ec 1444
17b0018b
FB		 1445 vga_draw_line4d2_8,
1446 vga_draw_line4d2_16,
1447 vga_draw_line4d2_16,
1448 vga_draw_line4d2_32,
d3079cd2 1449 vga_draw_line4d2_32,
b29169d2
BS		 1450 vga_draw_line4d2_16,
1451 vga_draw_line4d2_16,
17b0018b
FB		 1452
1453 vga_draw_line8d2_8,
1454 vga_draw_line8d2_16,
1455 vga_draw_line8d2_16,
1456 vga_draw_line8d2_32,
d3079cd2 1457 vga_draw_line8d2_32,
b29169d2
BS		 1458 vga_draw_line8d2_16,
1459 vga_draw_line8d2_16,
17b0018b 1460
e89f66ec
FB		 1461 vga_draw_line8_8,
1462 vga_draw_line8_16,
1463 vga_draw_line8_16,
1464 vga_draw_line8_32,
d3079cd2 1465 vga_draw_line8_32,
b29169d2
BS		 1466 vga_draw_line8_16,
1467 vga_draw_line8_16,
e89f66ec
FB		 1468
1469 vga_draw_line15_8,
1470 vga_draw_line15_15,
1471 vga_draw_line15_16,
1472 vga_draw_line15_32,
d3079cd2 1473 vga_draw_line15_32bgr,
b29169d2
BS		 1474 vga_draw_line15_15bgr,
1475 vga_draw_line15_16bgr,
e89f66ec
FB		 1476
1477 vga_draw_line16_8,
1478 vga_draw_line16_15,
1479 vga_draw_line16_16,
1480 vga_draw_line16_32,
d3079cd2 1481 vga_draw_line16_32bgr,
b29169d2
BS		 1482 vga_draw_line16_15bgr,
1483 vga_draw_line16_16bgr,
e89f66ec 1484
4fa0f5d2
FB		 1485 vga_draw_line24_8,
1486 vga_draw_line24_15,
1487 vga_draw_line24_16,
1488 vga_draw_line24_32,
d3079cd2 1489 vga_draw_line24_32bgr,
b29169d2
BS		 1490 vga_draw_line24_15bgr,
1491 vga_draw_line24_16bgr,
4fa0f5d2 1492
e89f66ec
FB		 1493 vga_draw_line32_8,
1494 vga_draw_line32_15,
1495 vga_draw_line32_16,
1496 vga_draw_line32_32,
d3079cd2 1497 vga_draw_line32_32bgr,
b29169d2
BS		 1498 vga_draw_line32_15bgr,
1499 vga_draw_line32_16bgr,
d3079cd2
FB		 1500};
1501
1502typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1503
1504static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1505 rgb_to_pixel8_dup,
1506 rgb_to_pixel15_dup,
1507 rgb_to_pixel16_dup,
1508 rgb_to_pixel32_dup,
1509 rgb_to_pixel32bgr_dup,
b29169d2
BS		 1510 rgb_to_pixel15bgr_dup,
1511 rgb_to_pixel16bgr_dup,
e89f66ec
FB		 1512};
1513
798b0c25
FB		 1514static int vga_get_bpp(VGAState *s)
1515{
1516 int ret;
1517#ifdef CONFIG_BOCHS_VBE
1518 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1519 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
5fafdf24 1520 } else
798b0c25
FB		 1521#endif
1522 {
1523 ret = 0;
1524 }
1525 return ret;
1526}
1527
a130a41e
FB		 1528static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1529{
1530 int width, height;
3b46e624 1531
8454df8b
FB		 1532#ifdef CONFIG_BOCHS_VBE
1533 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1534 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1535 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
5fafdf24 1536 } else
8454df8b
FB		 1537#endif
1538 {
1539 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1540 height = s->cr[0x12] |
1541 ((s->cr[0x07] & 0x02) << 7) |
8454df8b
FB		 1542 ((s->cr[0x07] & 0x40) << 3);
1543 height = (height + 1);
1544 }
a130a41e
FB		 1545 *pwidth = width;
1546 *pheight = height;
1547}
1548
a8aa669b
FB		 1549void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1550{
1551 int y;
1552 if (y1 >= VGA_MAX_HEIGHT)
1553 return;
1554 if (y2 >= VGA_MAX_HEIGHT)
1555 y2 = VGA_MAX_HEIGHT;
1556 for(y = y1; y < y2; y++) {
1557 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1558 }
1559}
1560
5fafdf24 1561/*
e89f66ec 1562 * graphic modes
e89f66ec
FB		 1563 */
1564static void vga_draw_graphic(VGAState *s, int full_update)
1565{
17b0018b 1566 int y1, y, update, page_min, page_max, linesize, y_start, double_scan, mask;
15342721 1567 int width, height, shift_control, line_offset, page0, page1, bwidth, bits;
a07cf92a 1568 int disp_width, multi_scan, multi_run;
e89f66ec 1569 uint8_t *d;
39cf7803 1570 uint32_t v, addr1, addr;
e89f66ec 1571 vga_draw_line_func *vga_draw_line;
3b46e624 1572
e89f66ec
FB		 1573 full_update |= update_basic_params(s);
1574
a130a41e 1575 s->get_resolution(s, &width, &height);
17b0018b 1576 disp_width = width;
09a79b49 1577
e89f66ec 1578 shift_control = (s->gr[0x05] >> 5) & 3;
f6c958c8
FB		 1579 double_scan = (s->cr[0x09] >> 7);
1580 if (shift_control != 1) {
1581 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
a07cf92a 1582 } else {
f6c958c8
FB		 1583 /* in CGA modes, multi_scan is ignored */
1584 /* XXX: is it correct ? */
1585 multi_scan = double_scan;
a07cf92a
FB		 1586 }
1587 multi_run = multi_scan;
17b0018b
FB		 1588 if (shift_control != s->shift_control ||
1589 double_scan != s->double_scan) {
e89f66ec
FB		 1590 full_update = 1;
1591 s->shift_control = shift_control;
17b0018b 1592 s->double_scan = double_scan;
e89f66ec 1593 }
3b46e624 1594
17b0018b
FB		 1595 if (shift_control == 0) {
1596 full_update |= update_palette16(s);
1597 if (s->sr[0x01] & 8) {
1598 v = VGA_DRAW_LINE4D2;
1599 disp_width <<= 1;
1600 } else {
1601 v = VGA_DRAW_LINE4;
1602 }
15342721 1603 bits = 4;
17b0018b
FB		 1604 } else if (shift_control == 1) {
1605 full_update |= update_palette16(s);
1606 if (s->sr[0x01] & 8) {
1607 v = VGA_DRAW_LINE2D2;
1608 disp_width <<= 1;
1609 } else {
1610 v = VGA_DRAW_LINE2;
1611 }
15342721 1612 bits = 4;
17b0018b 1613 } else {
798b0c25
FB		 1614 switch(s->get_bpp(s)) {
1615 default:
1616 case 0:
4fa0f5d2
FB		 1617 full_update |= update_palette256(s);
1618 v = VGA_DRAW_LINE8D2;
15342721 1619 bits = 4;
798b0c25
FB		 1620 break;
1621 case 8:
1622 full_update |= update_palette256(s);
1623 v = VGA_DRAW_LINE8;
15342721 1624 bits = 8;
798b0c25
FB		 1625 break;
1626 case 15:
1627 v = VGA_DRAW_LINE15;
15342721 1628 bits = 16;
798b0c25
FB		 1629 break;
1630 case 16:
1631 v = VGA_DRAW_LINE16;
15342721 1632 bits = 16;
798b0c25
FB		 1633 break;
1634 case 24:
1635 v = VGA_DRAW_LINE24;
15342721 1636 bits = 24;
798b0c25
FB		 1637 break;
1638 case 32:
1639 v = VGA_DRAW_LINE32;
15342721 1640 bits = 32;
798b0c25 1641 break;
4fa0f5d2 1642 }
17b0018b 1643 }
d3079cd2 1644 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
17b0018b
FB		 1645
1646 if (disp_width != s->last_width ||
1647 height != s->last_height) {
c60e08d9 1648 qemu_console_resize(s->console, disp_width, height);
2aebb3eb
FB		 1649 s->last_scr_width = disp_width;
1650 s->last_scr_height = height;
17b0018b
FB		 1651 s->last_width = disp_width;
1652 s->last_height = height;
1653 full_update = 1;
1654 }
a8aa669b
FB		 1655 if (s->cursor_invalidate)
1656 s->cursor_invalidate(s);
3b46e624 1657
e89f66ec 1658 line_offset = s->line_offset;
17b0018b 1659#if 0
f6c958c8 1660 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
17b0018b
FB		 1661 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1662#endif
e89f66ec 1663 addr1 = (s->start_addr * 4);
15342721 1664 bwidth = (width * bits + 7) / 8;
39cf7803 1665 y_start = -1;
e89f66ec
FB		 1666 page_min = 0x7fffffff;
1667 page_max = -1;
1668 d = s->ds->data;
1669 linesize = s->ds->linesize;
17b0018b 1670 y1 = 0;
e89f66ec
FB		 1671 for(y = 0; y < height; y++) {
1672 addr = addr1;
39cf7803 1673 if (!(s->cr[0x17] & 1)) {
17b0018b 1674 int shift;
e89f66ec 1675 /* CGA compatibility handling */
17b0018b
FB		 1676 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1677 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
e89f66ec 1678 }
39cf7803 1679 if (!(s->cr[0x17] & 2)) {
17b0018b 1680 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
e89f66ec 1681 }
4fa0f5d2
FB		 1682 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1683 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
5fafdf24 1684 update = full_update |
0a962c02
FB		 1685 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1686 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
4fa0f5d2 1687 if ((page1 - page0) > TARGET_PAGE_SIZE) {
39cf7803 1688 /* if wide line, can use another page */
5fafdf24 1689 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
0a962c02 1690 VGA_DIRTY_FLAG);
39cf7803 1691 }
a8aa669b
FB		 1692 /* explicit invalidation for the hardware cursor */
1693 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
e89f66ec 1694 if (update) {
39cf7803
FB		 1695 if (y_start < 0)
1696 y_start = y;
e89f66ec
FB		 1697 if (page0 < page_min)
1698 page_min = page0;
1699 if (page1 > page_max)
1700 page_max = page1;
1701 vga_draw_line(s, d, s->vram_ptr + addr, width);
a8aa669b
FB		 1702 if (s->cursor_draw_line)
1703 s->cursor_draw_line(s, d, y);
39cf7803
FB		 1704 } else {
1705 if (y_start >= 0) {
1706 /* flush to display */
5fafdf24 1707 dpy_update(s->ds, 0, y_start,
17b0018b 1708 disp_width, y - y_start);
39cf7803
FB		 1709 y_start = -1;
1710 }
e89f66ec 1711 }
a07cf92a 1712 if (!multi_run) {
f6c958c8
FB		 1713 mask = (s->cr[0x17] & 3) ^ 3;
1714 if ((y1 & mask) == mask)
1715 addr1 += line_offset;
1716 y1++;
a07cf92a
FB		 1717 multi_run = multi_scan;
1718 } else {
1719 multi_run--;
e89f66ec 1720 }
f6c958c8
FB		 1721 /* line compare acts on the displayed lines */
1722 if (y == s->line_compare)
1723 addr1 = 0;
e89f66ec
FB		 1724 d += linesize;
1725 }
39cf7803
FB		 1726 if (y_start >= 0) {
1727 /* flush to display */
5fafdf24 1728 dpy_update(s->ds, 0, y_start,
17b0018b 1729 disp_width, y - y_start);
39cf7803 1730 }
e89f66ec
FB		 1731 /* reset modified pages */
1732 if (page_max != -1) {
0a962c02
FB		 1733 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1734 VGA_DIRTY_FLAG);
e89f66ec 1735 }
a8aa669b 1736 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
e89f66ec
FB		 1737}
1738
2aebb3eb
FB		 1739static void vga_draw_blank(VGAState *s, int full_update)
1740{
1741 int i, w, val;
1742 uint8_t *d;
1743
1744 if (!full_update)
1745 return;
1746 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1747 return;
5fafdf24 1748 if (s->ds->depth == 8)
2aebb3eb
FB		 1749 val = s->rgb_to_pixel(0, 0, 0);
1750 else
1751 val = 0;
1752 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
1753 d = s->ds->data;
1754 for(i = 0; i < s->last_scr_height; i++) {
1755 memset(d, val, w);
1756 d += s->ds->linesize;
1757 }
5fafdf24 1758 dpy_update(s->ds, 0, 0,
2aebb3eb
FB		 1759 s->last_scr_width, s->last_scr_height);
1760}
1761
1762#define GMODE_TEXT 0
1763#define GMODE_GRAPH 1
5fafdf24 1764#define GMODE_BLANK 2
2aebb3eb 1765
95219897 1766static void vga_update_display(void *opaque)
e89f66ec 1767{
95219897 1768 VGAState *s = (VGAState *)opaque;
e89f66ec
FB		 1769 int full_update, graphic_mode;
1770
1771 if (s->ds->depth == 0) {
0f35920c 1772 /* nothing to do */
59a983b9 1773 } else {
5fafdf24 1774 s->rgb_to_pixel =
d3079cd2 1775 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
3b46e624 1776
e89f66ec 1777 full_update = 0;
2aebb3eb
FB		 1778 if (!(s->ar_index & 0x20)) {
1779 graphic_mode = GMODE_BLANK;
1780 } else {
1781 graphic_mode = s->gr[6] & 1;
1782 }
e89f66ec
FB		 1783 if (graphic_mode != s->graphic_mode) {
1784 s->graphic_mode = graphic_mode;
1785 full_update = 1;
1786 }
2aebb3eb
FB		 1787 switch(graphic_mode) {
1788 case GMODE_TEXT:
e89f66ec 1789 vga_draw_text(s, full_update);
2aebb3eb
FB		 1790 break;
1791 case GMODE_GRAPH:
1792 vga_draw_graphic(s, full_update);
1793 break;
1794 case GMODE_BLANK:
1795 default:
1796 vga_draw_blank(s, full_update);
1797 break;
1798 }
e89f66ec
FB		 1799 }
1800}
1801
a130a41e 1802/* force a full display refresh */
95219897 1803static void vga_invalidate_display(void *opaque)
a130a41e 1804{
95219897 1805 VGAState *s = (VGAState *)opaque;
3b46e624 1806
a130a41e
FB		 1807 s->last_width = -1;
1808 s->last_height = -1;
1809}
1810
59a983b9 1811static void vga_reset(VGAState *s)
e89f66ec
FB		 1812{
1813 memset(s, 0, sizeof(VGAState));
e89f66ec
FB		 1814 s->graphic_mode = -1; /* force full update */
1815}
1816
4d3b6f6e
AZ		 1817#define TEXTMODE_X(x) ((x) % width)
1818#define TEXTMODE_Y(x) ((x) / width)
1819#define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1820 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1821/* relay text rendering to the display driver
1822 * instead of doing a full vga_update_display() */
1823static void vga_update_text(void *opaque, console_ch_t *chardata)
1824{
1825 VGAState *s = (VGAState *) opaque;
1826 int graphic_mode, i, cursor_offset, cursor_visible;
1827 int cw, cheight, width, height, size, c_min, c_max;
1828 uint32_t *src;
1829 console_ch_t *dst, val;
1830 char msg_buffer[80];
5228c2d3 1831 int full_update = 0;
4d3b6f6e
AZ		 1832
1833 if (!(s->ar_index & 0x20)) {
1834 graphic_mode = GMODE_BLANK;
1835 } else {
1836 graphic_mode = s->gr[6] & 1;
1837 }
1838 if (graphic_mode != s->graphic_mode) {
1839 s->graphic_mode = graphic_mode;
1840 full_update = 1;
1841 }
1842 if (s->last_width == -1) {
1843 s->last_width = 0;
1844 full_update = 1;
1845 }
1846
1847 switch (graphic_mode) {
1848 case GMODE_TEXT:
1849 /* TODO: update palette */
1850 full_update |= update_basic_params(s);
1851
1852 /* total width & height */
1853 cheight = (s->cr[9] & 0x1f) + 1;
1854 cw = 8;
1855 if (!(s->sr[1] & 0x01))
1856 cw = 9;
1857 if (s->sr[1] & 0x08)
1858 cw = 16; /* NOTE: no 18 pixel wide */
1859 width = (s->cr[0x01] + 1);
1860 if (s->cr[0x06] == 100) {
1861 /* ugly hack for CGA 160x100x16 - explain me the logic */
1862 height = 100;
1863 } else {
1864 height = s->cr[0x12] |
1865 ((s->cr[0x07] & 0x02) << 7) |
1866 ((s->cr[0x07] & 0x40) << 3);
1867 height = (height + 1) / cheight;
1868 }
1869
1870 size = (height * width);
1871 if (size > CH_ATTR_SIZE) {
1872 if (!full_update)
1873 return;
1874
363a37d5
BS		 1875 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1876 width, height);
4d3b6f6e
AZ		 1877 break;
1878 }
1879
1880 if (width != s->last_width || height != s->last_height ||
1881 cw != s->last_cw || cheight != s->last_ch) {
1882 s->last_scr_width = width * cw;
1883 s->last_scr_height = height * cheight;
c60e08d9 1884 qemu_console_resize(s->console, width, height);
4d3b6f6e
AZ		 1885 s->last_width = width;
1886 s->last_height = height;
1887 s->last_ch = cheight;
1888 s->last_cw = cw;
1889 full_update = 1;
1890 }
1891
1892 /* Update "hardware" cursor */
1893 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1894 if (cursor_offset != s->cursor_offset ||
1895 s->cr[0xa] != s->cursor_start ||
1896 s->cr[0xb] != s->cursor_end || full_update) {
1897 cursor_visible = !(s->cr[0xa] & 0x20);
1898 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1899 dpy_cursor(s->ds,
1900 TEXTMODE_X(cursor_offset),
1901 TEXTMODE_Y(cursor_offset));
1902 else
1903 dpy_cursor(s->ds, -1, -1);
1904 s->cursor_offset = cursor_offset;
1905 s->cursor_start = s->cr[0xa];
1906 s->cursor_end = s->cr[0xb];
1907 }
1908
1909 src = (uint32_t *) s->vram_ptr + s->start_addr;
1910 dst = chardata;
1911
1912 if (full_update) {
1913 for (i = 0; i < size; src ++, dst ++, i ++)
1914 console_write_ch(dst, VMEM2CHTYPE(*src));
1915
1916 dpy_update(s->ds, 0, 0, width, height);
1917 } else {
1918 c_max = 0;
1919
1920 for (i = 0; i < size; src ++, dst ++, i ++) {
1921 console_write_ch(&val, VMEM2CHTYPE(*src));
1922 if (*dst != val) {
1923 *dst = val;
1924 c_max = i;
1925 break;
1926 }
1927 }
1928 c_min = i;
1929 for (; i < size; src ++, dst ++, i ++) {
1930 console_write_ch(&val, VMEM2CHTYPE(*src));
1931 if (*dst != val) {
1932 *dst = val;
1933 c_max = i;
1934 }
1935 }
1936
1937 if (c_min <= c_max) {
1938 i = TEXTMODE_Y(c_min);
1939 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1940 }
1941 }
1942
1943 return;
1944 case GMODE_GRAPH:
1945 if (!full_update)
1946 return;
1947
1948 s->get_resolution(s, &width, &height);
363a37d5
BS		 1949 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
1950 width, height);
4d3b6f6e
AZ		 1951 break;
1952 case GMODE_BLANK:
1953 default:
1954 if (!full_update)
1955 return;
1956
363a37d5 1957 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
4d3b6f6e
AZ		 1958 break;
1959 }
1960
1961 /* Display a message */
5228c2d3
AZ		 1962 s->last_width = 60;
1963 s->last_height = height = 3;
4d3b6f6e 1964 dpy_cursor(s->ds, -1, -1);
c60e08d9 1965 qemu_console_resize(s->console, s->last_width, height);
4d3b6f6e 1966
5228c2d3 1967 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
4d3b6f6e
AZ		 1968 console_write_ch(dst ++, ' ');
1969
1970 size = strlen(msg_buffer);
5228c2d3
AZ		 1971 width = (s->last_width - size) / 2;
1972 dst = chardata + s->last_width + width;
4d3b6f6e
AZ		 1973 for (i = 0; i < size; i ++)
1974 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
1975
5228c2d3 1976 dpy_update(s->ds, 0, 0, s->last_width, height);
4d3b6f6e
AZ		 1977}
1978
59a983b9 1979static CPUReadMemoryFunc *vga_mem_read[3] = {
e89f66ec
FB		 1980 vga_mem_readb,
1981 vga_mem_readw,
1982 vga_mem_readl,
1983};
1984
59a983b9 1985static CPUWriteMemoryFunc *vga_mem_write[3] = {
e89f66ec
FB		 1986 vga_mem_writeb,
1987 vga_mem_writew,
1988 vga_mem_writel,
1989};
1990
b0a21b53
FB		 1991static void vga_save(QEMUFile *f, void *opaque)
1992{
1993 VGAState *s = opaque;
1994 int i;
1995
d2269f6f
FB		 1996 if (s->pci_dev)
1997 pci_device_save(s->pci_dev, f);
1998
b0a21b53
FB		 1999 qemu_put_be32s(f, &s->latch);
2000 qemu_put_8s(f, &s->sr_index);
2001 qemu_put_buffer(f, s->sr, 8);
2002 qemu_put_8s(f, &s->gr_index);
2003 qemu_put_buffer(f, s->gr, 16);
2004 qemu_put_8s(f, &s->ar_index);
2005 qemu_put_buffer(f, s->ar, 21);
bee8d684 2006 qemu_put_be32(f, s->ar_flip_flop);
b0a21b53
FB		 2007 qemu_put_8s(f, &s->cr_index);
2008 qemu_put_buffer(f, s->cr, 256);
2009 qemu_put_8s(f, &s->msr);
2010 qemu_put_8s(f, &s->fcr);
bee8d684 2011 qemu_put_byte(f, s->st00);
b0a21b53
FB		 2012 qemu_put_8s(f, &s->st01);
2013
2014 qemu_put_8s(f, &s->dac_state);
2015 qemu_put_8s(f, &s->dac_sub_index);
2016 qemu_put_8s(f, &s->dac_read_index);
2017 qemu_put_8s(f, &s->dac_write_index);
2018 qemu_put_buffer(f, s->dac_cache, 3);
2019 qemu_put_buffer(f, s->palette, 768);
2020
bee8d684 2021 qemu_put_be32(f, s->bank_offset);
b0a21b53
FB		 2022#ifdef CONFIG_BOCHS_VBE
2023 qemu_put_byte(f, 1);
2024 qemu_put_be16s(f, &s->vbe_index);
2025 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2026 qemu_put_be16s(f, &s->vbe_regs[i]);
2027 qemu_put_be32s(f, &s->vbe_start_addr);
2028 qemu_put_be32s(f, &s->vbe_line_offset);
2029 qemu_put_be32s(f, &s->vbe_bank_mask);
2030#else
2031 qemu_put_byte(f, 0);
2032#endif
2033}
2034
2035static int vga_load(QEMUFile *f, void *opaque, int version_id)
2036{
2037 VGAState *s = opaque;
d2269f6f 2038 int is_vbe, i, ret;
b0a21b53 2039
d2269f6f 2040 if (version_id > 2)
b0a21b53
FB		 2041 return -EINVAL;
2042
d2269f6f
FB		 2043 if (s->pci_dev && version_id >= 2) {
2044 ret = pci_device_load(s->pci_dev, f);
2045 if (ret < 0)
2046 return ret;
2047 }
2048
b0a21b53
FB		 2049 qemu_get_be32s(f, &s->latch);
2050 qemu_get_8s(f, &s->sr_index);
2051 qemu_get_buffer(f, s->sr, 8);
2052 qemu_get_8s(f, &s->gr_index);
2053 qemu_get_buffer(f, s->gr, 16);
2054 qemu_get_8s(f, &s->ar_index);
2055 qemu_get_buffer(f, s->ar, 21);
bee8d684 2056 s->ar_flip_flop=qemu_get_be32(f);
b0a21b53
FB		 2057 qemu_get_8s(f, &s->cr_index);
2058 qemu_get_buffer(f, s->cr, 256);
2059 qemu_get_8s(f, &s->msr);
2060 qemu_get_8s(f, &s->fcr);
2061 qemu_get_8s(f, &s->st00);
2062 qemu_get_8s(f, &s->st01);
2063
2064 qemu_get_8s(f, &s->dac_state);
2065 qemu_get_8s(f, &s->dac_sub_index);
2066 qemu_get_8s(f, &s->dac_read_index);
2067 qemu_get_8s(f, &s->dac_write_index);
2068 qemu_get_buffer(f, s->dac_cache, 3);
2069 qemu_get_buffer(f, s->palette, 768);
2070
bee8d684 2071 s->bank_offset=qemu_get_be32(f);
b0a21b53
FB		 2072 is_vbe = qemu_get_byte(f);
2073#ifdef CONFIG_BOCHS_VBE
2074 if (!is_vbe)
2075 return -EINVAL;
2076 qemu_get_be16s(f, &s->vbe_index);
2077 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2078 qemu_get_be16s(f, &s->vbe_regs[i]);
2079 qemu_get_be32s(f, &s->vbe_start_addr);
2080 qemu_get_be32s(f, &s->vbe_line_offset);
2081 qemu_get_be32s(f, &s->vbe_bank_mask);
2082#else
2083 if (is_vbe)
2084 return -EINVAL;
2085#endif
2086
2087 /* force refresh */
2088 s->graphic_mode = -1;
2089 return 0;
2090}
2091
d2269f6f
FB		 2092typedef struct PCIVGAState {
2093 PCIDevice dev;
2094 VGAState vga_state;
2095} PCIVGAState;
2096
5fafdf24 2097static void vga_map(PCIDevice *pci_dev, int region_num,
1078f663
FB		 2098 uint32_t addr, uint32_t size, int type)
2099{
d2269f6f
FB		 2100 PCIVGAState *d = (PCIVGAState *)pci_dev;
2101 VGAState *s = &d->vga_state;
d5295253
FB		 2102 if (region_num == PCI_ROM_SLOT) {
2103 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2104 } else {
2105 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2106 }
1078f663
FB		 2107}
2108
5fafdf24 2109void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
798b0c25 2110 unsigned long vga_ram_offset, int vga_ram_size)
e89f66ec 2111{
17b0018b 2112 int i, j, v, b;
e89f66ec
FB		 2113
2114 for(i = 0;i < 256; i++) {
2115 v = 0;
2116 for(j = 0; j < 8; j++) {
2117 v |= ((i >> j) & 1) << (j * 4);
2118 }
2119 expand4[i] = v;
2120
2121 v = 0;
2122 for(j = 0; j < 4; j++) {
2123 v |= ((i >> (2 * j)) & 3) << (j * 4);
2124 }
2125 expand2[i] = v;
2126 }
17b0018b
FB		 2127 for(i = 0; i < 16; i++) {
2128 v = 0;
2129 for(j = 0; j < 4; j++) {
2130 b = ((i >> j) & 1);
2131 v |= b << (2 * j);
2132 v |= b << (2 * j + 1);
2133 }
2134 expand4to8[i] = v;
2135 }
e89f66ec
FB		 2136
2137 vga_reset(s);
2138
2139 s->vram_ptr = vga_ram_base;
2140 s->vram_offset = vga_ram_offset;
2141 s->vram_size = vga_ram_size;
2142 s->ds = ds;
798b0c25
FB		 2143 s->get_bpp = vga_get_bpp;
2144 s->get_offsets = vga_get_offsets;
a130a41e 2145 s->get_resolution = vga_get_resolution;
d34cab9f
TS		 2146 s->update = vga_update_display;
2147 s->invalidate = vga_invalidate_display;
2148 s->screen_dump = vga_screen_dump;
4d3b6f6e 2149 s->text_update = vga_update_text;
cb5a7aa8 2150 switch (vga_retrace_method) {
2151 case VGA_RETRACE_DUMB:
2152 s->retrace = vga_dumb_retrace;
2153 s->update_retrace_info = vga_dumb_update_retrace_info;
2154 break;
2155
2156 case VGA_RETRACE_PRECISE:
2157 s->retrace = vga_precise_retrace;
2158 s->update_retrace_info = vga_precise_update_retrace_info;
2159 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
2160 break;
2161 }
798b0c25
FB		 2162}
2163
d2269f6f 2164/* used by both ISA and PCI */
d34cab9f 2165void vga_init(VGAState *s)
798b0c25 2166{
d2269f6f 2167 int vga_io_memory;
7b17d41e 2168
d2269f6f 2169 register_savevm("vga", 0, 2, vga_save, vga_load, s);
b0a21b53 2170
0f35920c 2171 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
e89f66ec 2172
0f35920c
FB		 2173 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2174 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2175 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2176 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
e89f66ec 2177
0f35920c 2178 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
e89f66ec 2179
0f35920c
FB		 2180 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2181 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2182 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2183 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
26aa7d72 2184 s->bank_offset = 0;
e89f66ec 2185
4fa0f5d2
FB		 2186#ifdef CONFIG_BOCHS_VBE
2187 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
cae61cef 2188 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
09a79b49
FB		 2189#if defined (TARGET_I386)
2190 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2191 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
4fa0f5d2 2192
09a79b49
FB		 2193 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2194 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
646be93b
FB		 2195
2196 /* old Bochs IO ports */
09a79b49
FB		 2197 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2198 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
646be93b 2199
09a79b49 2200 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
5fafdf24 2201 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
09a79b49
FB		 2202#else
2203 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2204 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2205
2206 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2207 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
4fa0f5d2 2208#endif
09a79b49 2209#endif /* CONFIG_BOCHS_VBE */
4fa0f5d2 2210
a4193c8a 2211 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
5fafdf24 2212 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
26aa7d72 2213 vga_io_memory);
d2269f6f
FB		 2214}
2215
2abec30b
TS		 2216/* Memory mapped interface */
2217static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2218{
2219 VGAState *s = opaque;
2220
2221 return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xff;
2222}
2223
2224static void vga_mm_writeb (void *opaque,
2225 target_phys_addr_t addr, uint32_t value)
2226{
2227 VGAState *s = opaque;
2228
2229 vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xff);
2230}
2231
2232static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2233{
2234 VGAState *s = opaque;
2235
2236 return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xffff;
2237}
2238
2239static void vga_mm_writew (void *opaque,
2240 target_phys_addr_t addr, uint32_t value)
2241{
2242 VGAState *s = opaque;
2243
2244 vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xffff);
2245}
2246
2247static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2248{
2249 VGAState *s = opaque;
2250
2251 return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift);
2252}
2253
2254static void vga_mm_writel (void *opaque,
2255 target_phys_addr_t addr, uint32_t value)
2256{
2257 VGAState *s = opaque;
2258
2259 vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value);
2260}
2261
2262static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2263 &vga_mm_readb,
2264 &vga_mm_readw,
2265 &vga_mm_readl,
2266};
2267
2268static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2269 &vga_mm_writeb,
2270 &vga_mm_writew,
2271 &vga_mm_writel,
2272};
2273
2274static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2275 target_phys_addr_t ctrl_base, int it_shift)
2276{
2277 int s_ioport_ctrl, vga_io_memory;
2278
2279 s->base_ctrl = ctrl_base;
2280 s->it_shift = it_shift;
2281 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2282 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2283
2284 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2285
2286 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2287 s->bank_offset = 0;
2288 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2289}
2290
5fafdf24 2291int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
d2269f6f
FB		 2292 unsigned long vga_ram_offset, int vga_ram_size)
2293{
2294 VGAState *s;
2295
2296 s = qemu_mallocz(sizeof(VGAState));
2297 if (!s)
2298 return -1;
2299
2300 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2301 vga_init(s);
1078f663 2302
c60e08d9
PB		 2303 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2304 s->screen_dump, s->text_update, s);
d34cab9f 2305
4fa0f5d2 2306#ifdef CONFIG_BOCHS_VBE
d2269f6f 2307 /* XXX: use optimized standard vga accesses */
5fafdf24 2308 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
d2269f6f 2309 vga_ram_size, vga_ram_offset);
7138fcfb 2310#endif
d2269f6f
FB		 2311 return 0;
2312}
2313
2abec30b
TS		 2314int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
2315 unsigned long vga_ram_offset, int vga_ram_size,
2316 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2317 int it_shift)
2318{
2319 VGAState *s;
2320
2321 s = qemu_mallocz(sizeof(VGAState));
2322 if (!s)
2323 return -1;
2324
2325 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2326 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2327
c60e08d9
PB		 2328 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2329 s->screen_dump, s->text_update, s);
2abec30b
TS		 2330
2331#ifdef CONFIG_BOCHS_VBE
2332 /* XXX: use optimized standard vga accesses */
2333 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2334 vga_ram_size, vga_ram_offset);
2335#endif
2336 return 0;
2337}
2338
5fafdf24 2339int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
d2269f6f
FB		 2340 unsigned long vga_ram_offset, int vga_ram_size,
2341 unsigned long vga_bios_offset, int vga_bios_size)
2342{
2343 PCIVGAState *d;
2344 VGAState *s;
2345 uint8_t *pci_conf;
3b46e624 2346
5fafdf24 2347 d = (PCIVGAState *)pci_register_device(bus, "VGA",
d2269f6f
FB		 2348 sizeof(PCIVGAState),
2349 -1, NULL, NULL);
2350 if (!d)
2351 return -1;
2352 s = &d->vga_state;
3b46e624 2353
d2269f6f
FB		 2354 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2355 vga_init(s);
d34cab9f 2356
c60e08d9
PB		 2357 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2358 s->screen_dump, s->text_update, s);
d34cab9f 2359
d2269f6f 2360 s->pci_dev = &d->dev;
3b46e624 2361
d2269f6f
FB		 2362 pci_conf = d->dev.config;
2363 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2364 pci_conf[0x01] = 0x12;
2365 pci_conf[0x02] = 0x11;
2366 pci_conf[0x03] = 0x11;
5fafdf24 2367 pci_conf[0x0a] = 0x00; // VGA controller
d2269f6f
FB		 2368 pci_conf[0x0b] = 0x03;
2369 pci_conf[0x0e] = 0x00; // header_type
3b46e624 2370
d2269f6f 2371 /* XXX: vga_ram_size must be a power of two */
5fafdf24 2372 pci_register_io_region(&d->dev, 0, vga_ram_size,
d2269f6f
FB		 2373 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2374 if (vga_bios_size != 0) {
2375 unsigned int bios_total_size;
2376 s->bios_offset = vga_bios_offset;
2377 s->bios_size = vga_bios_size;
2378 /* must be a power of two */
2379 bios_total_size = 1;
2380 while (bios_total_size < vga_bios_size)
2381 bios_total_size <<= 1;
5fafdf24 2382 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
d2269f6f 2383 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
1078f663 2384 }
e89f66ec
FB		 2385 return 0;
2386}
59a983b9
FB		 2387
2388/********************************************************/
2389/* vga screen dump */
2390
2391static int vga_save_w, vga_save_h;
2392
5fafdf24 2393static void vga_save_dpy_update(DisplayState *s,
59a983b9
FB		 2394 int x, int y, int w, int h)
2395{
2396}
2397
2398static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2399{
2400 s->linesize = w * 4;
2401 s->data = qemu_malloc(h * s->linesize);
2402 vga_save_w = w;
2403 vga_save_h = h;
2404}
2405
2406static void vga_save_dpy_refresh(DisplayState *s)
2407{
2408}
2409
5fafdf24 2410int ppm_save(const char *filename, uint8_t *data,
f707cfba 2411 int w, int h, int linesize)
59a983b9
FB		 2412{
2413 FILE *f;
2414 uint8_t *d, *d1;
2415 unsigned int v;
2416 int y, x;
2417
2418 f = fopen(filename, "wb");
2419 if (!f)
2420 return -1;
2421 fprintf(f, "P6\n%d %d\n%d\n",
2422 w, h, 255);
2423 d1 = data;
2424 for(y = 0; y < h; y++) {
2425 d = d1;
2426 for(x = 0; x < w; x++) {
2427 v = *(uint32_t *)d;
2428 fputc((v >> 16) & 0xff, f);
2429 fputc((v >> 8) & 0xff, f);
2430 fputc((v) & 0xff, f);
2431 d += 4;
2432 }
2433 d1 += linesize;
2434 }
2435 fclose(f);
2436 return 0;
2437}
2438
2439/* save the vga display in a PPM image even if no display is
2440 available */
95219897 2441static void vga_screen_dump(void *opaque, const char *filename)
59a983b9 2442{
95219897 2443 VGAState *s = (VGAState *)opaque;
59a983b9 2444 DisplayState *saved_ds, ds1, *ds = &ds1;
3b46e624 2445
59a983b9 2446 /* XXX: this is a little hackish */
95219897 2447 vga_invalidate_display(s);
59a983b9
FB		 2448 saved_ds = s->ds;
2449
2450 memset(ds, 0, sizeof(DisplayState));
2451 ds->dpy_update = vga_save_dpy_update;
2452 ds->dpy_resize = vga_save_dpy_resize;
2453 ds->dpy_refresh = vga_save_dpy_refresh;
2454 ds->depth = 32;
2455
2456 s->ds = ds;
2457 s->graphic_mode = -1;
95219897 2458 vga_update_display(s);
3b46e624 2459
59a983b9 2460 if (ds->data) {
5fafdf24 2461 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
59a983b9
FB		 2462 s->ds->linesize);
2463 qemu_free(ds->data);
2464 }
2465 s->ds = saved_ds;
2466}
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