[qemu.git] / hw / timer / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licensed under the GPL.
 */

#include "hw/hw.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
#define PXA2XX_TIMER(obj) \
    OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)

typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;

typedef struct {
    uint32_t value;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    PXA2xxTimerInfo *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

struct PXA2xxTimerInfo {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t flags;

    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;

    qemu_irq irq4;
    PXA2xxTimer4 tm4[8];
};

#define PXA2XX_TIMER_HAVE_TM4	0

static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
    return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
}

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        get_ticks_per_sec(), s->freq);
        timer_mod(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        timer_del(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, get_ticks_per_sec());

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    get_ticks_per_sec(), s->tm4[counter].freq);
    timer_mod(s->tm4[n].tm.qtimer, new_qemu);
}

static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
                                  unsigned size)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                        s->lastload, s->freq, get_ticks_per_sec());
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, get_ticks_per_sec());
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                        s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm ++;
        /* fall through */
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
    badreg:
        hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, hwaddr offset,
                               uint64_t value, unsigned size)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
        break;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        value &= s->events;
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1)
            if (value & 1)
                qemu_irq_lower(s->timer[i].irq);
        if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
            qemu_irq_lower(s->irq4);
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm += 4;
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    default:
    badreg:
        hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
    }
}

static const MemoryRegionOps pxa2xx_timer_ops = {
    .read = pxa2xx_timer_read,
    .write = pxa2xx_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request();
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
    if (i->events & 0xff0)
        qemu_irq_raise(i->irq4);
}

static int pxa25x_timer_post_load(void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    pxa2xx_timer_update(s, now);

    if (pxa2xx_timer_has_tm4(s))
        for (i = 0; i < 8; i ++)
            pxa2xx_timer_update4(s, now, i);

    return 0;
}

static int pxa2xx_timer_init(SysBusDevice *dev)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
    int i;

    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    s->reset3 = 0;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        sysbus_init_irq(dev, &s->timer[i].irq);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                        pxa2xx_timer_tick, &s->timer[i]);
    }
    if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
        sysbus_init_irq(dev, &s->irq4);

        for (i = 0; i < 8; i ++) {
            s->tm4[i].tm.value = 0;
            s->tm4[i].tm.info = s;
            s->tm4[i].tm.num = i + 4;
            s->tm4[i].freq = 0;
            s->tm4[i].control = 0x0;
            s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                        pxa2xx_timer_tick4, &s->tm4[i]);
        }
    }

    memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_timer_ops, s,
                          "pxa2xx-timer", 0x00001000);
    sysbus_init_mmio(dev, &s->iomem);

    return 0;
}

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
    .name = "pxa2xx_timer0",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(value, PXA2xxTimer0),
        VMSTATE_END_OF_LIST(),
    },
};

static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
    .name = "pxa2xx_timer4",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_INT32(oldclock, PXA2xxTimer4),
        VMSTATE_INT32(clock, PXA2xxTimer4),
        VMSTATE_UINT64(lastload, PXA2xxTimer4),
        VMSTATE_UINT32(freq, PXA2xxTimer4),
        VMSTATE_UINT32(control, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    },
};

static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
    return pxa2xx_timer_has_tm4(opaque);
}

static const VMStateDescription vmstate_pxa2xx_timer_regs = {
    .name = "pxa2xx_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = pxa25x_timer_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(clock, PXA2xxTimerInfo),
        VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
        VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_UINT32(events, PXA2xxTimerInfo),
        VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
        VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
        VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
                        pxa2xx_timer_has_tm4_test, 0,
                        vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    }
};

static Property pxa25x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA25x timer";
    dc->props = pxa25x_timer_dev_properties;
}

static const TypeInfo pxa25x_timer_dev_info = {
    .name          = "pxa25x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa25x_timer_dev_class_init,
};

static Property pxa27x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA27x timer";
    dc->props = pxa27x_timer_dev_properties;
}

static const TypeInfo pxa27x_timer_dev_info = {
    .name          = "pxa27x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa27x_timer_dev_class_init,
};

static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc);

    sdc->init = pxa2xx_timer_init;
    dc->vmsd = &vmstate_pxa2xx_timer_regs;
}

static const TypeInfo pxa2xx_timer_type_info = {
    .name          = TYPE_PXA2XX_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .abstract      = true,
    .class_init    = pxa2xx_timer_class_init,
};

static void pxa2xx_timer_register_types(void)
{
    type_register_static(&pxa2xx_timer_type_info);
    type_register_static(&pxa25x_timer_dev_info);
    type_register_static(&pxa27x_timer_dev_info);
}

type_init(pxa2xx_timer_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
8e31bf38	7	* This code is licensed under the GPL.
a171fe39 AZ	8	*/
a171fe39 AZ	9
83c9f4ca	10	#include "hw/hw.h"
1de7afc9	11	#include "qemu/timer.h"
9c17d615	12	#include "sysemu/sysemu.h"
0d09e41a	13	#include "hw/arm/pxa.h"
83c9f4ca	14	#include "hw/sysbus.h"
a171fe39 AZ	15
	16	#define OSMR0 0x00
	17	#define OSMR1 0x04
	18	#define OSMR2 0x08
	19	#define OSMR3 0x0c
	20	#define OSMR4 0x80
	21	#define OSMR5 0x84
	22	#define OSMR6 0x88
	23	#define OSMR7 0x8c
	24	#define OSMR8 0x90
	25	#define OSMR9 0x94
	26	#define OSMR10 0x98
	27	#define OSMR11 0x9c
	28	#define OSCR 0x10 /* OS Timer Count */
	29	#define OSCR4 0x40
	30	#define OSCR5 0x44
	31	#define OSCR6 0x48
	32	#define OSCR7 0x4c
	33	#define OSCR8 0x50
	34	#define OSCR9 0x54
	35	#define OSCR10 0x58
	36	#define OSCR11 0x5c
	37	#define OSSR 0x14 /* Timer status register */
	38	#define OWER 0x18
	39	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	40	#define OMCR4 0xc0 /* OS Match Control registers */
	41	#define OMCR5 0xc4
	42	#define OMCR6 0xc8
	43	#define OMCR7 0xcc
	44	#define OMCR8 0xd0
	45	#define OMCR9 0xd4
	46	#define OMCR10 0xd8
	47	#define OMCR11 0xdc
	48	#define OSNR 0x20
	49
	50	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	51	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	52
	53	static int pxa2xx_timer4_freq[8] = {
	54	[0] = 0,
	55	[1] = 32768,
	56	[2] = 1000,
	57	[3] = 1,
	58	[4] = 1000000,
	59	/* [5] is the "Externally supplied clock". Assign if necessary. */
	60	[5 ... 7] = 0,
	61	};
	62
feea4361 AF	63	#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
	64	#define PXA2XX_TIMER(obj) \
	65	OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
	66
797e9542 DES	67	typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
797e9542 DES	68
bc24a225	69	typedef struct {
a171fe39	70	uint32_t value;
5251d196	71	qemu_irq irq;
a171fe39 AZ	72	QEMUTimer *qtimer;
a171fe39 AZ	73	int num;
797e9542	74	PXA2xxTimerInfo *info;
bc24a225	75	} PXA2xxTimer0;
a171fe39	76
bc24a225 PB	77	typedef struct {
bc24a225 PB	78	PXA2xxTimer0 tm;
a171fe39 AZ	79	int32_t oldclock;
	80	int32_t clock;
	81	uint64_t lastload;
	82	uint32_t freq;
	83	uint32_t control;
bc24a225	84	} PXA2xxTimer4;
a171fe39	85
797e9542	86	struct PXA2xxTimerInfo {
feea4361 AF	87	SysBusDevice parent_obj;
feea4361 AF	88
b755bde3	89	MemoryRegion iomem;
797e9542 DES	90	uint32_t flags;
797e9542 DES	91
a171fe39 AZ	92	int32_t clock;
	93	int32_t oldclock;
	94	uint64_t lastload;
	95	uint32_t freq;
bc24a225	96	PXA2xxTimer0 timer[4];
a171fe39 AZ	97	uint32_t events;
	98	uint32_t irq_enabled;
	99	uint32_t reset3;
a171fe39	100	uint32_t snapshot;
797e9542	101
4ff927cc	102	qemu_irq irq4;
797e9542	103	PXA2xxTimer4 tm4[8];
797e9542 DES	104	};
	105
	106	#define PXA2XX_TIMER_HAVE_TM4 0
	107
	108	static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
	109	{
	110	return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
	111	}
a171fe39 AZ	112
	113	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	114	{
d353eb43	115	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	116	int i;
	117	uint32_t now_vm;
	118	uint64_t new_qemu;
	119
	120	now_vm = s->clock +
6ee093c9	121	muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	122
	123	for (i = 0; i < 4; i ++) {
	124	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
6ee093c9	125	get_ticks_per_sec(), s->freq);
bc72ad67	126	timer_mod(s->timer[i].qtimer, new_qemu);
a171fe39 AZ	127	}
	128	}
	129
	130	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	131	{
d353eb43	132	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	133	uint32_t now_vm;
	134	uint64_t new_qemu;
	135	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	136	int counter;
	137
	138	if (s->tm4[n].control & (1 << 7))
	139	counter = n;
	140	else
	141	counter = counters[n];
	142
	143	if (!s->tm4[counter].freq) {
bc72ad67	144	timer_del(s->tm4[n].tm.qtimer);
a171fe39 AZ	145	return;
	146	}
	147
	148	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	149	s->tm4[counter].lastload,
6ee093c9	150	s->tm4[counter].freq, get_ticks_per_sec());
a171fe39	151
3bdd58a4	152	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
6ee093c9	153	get_ticks_per_sec(), s->tm4[counter].freq);
bc72ad67	154	timer_mod(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	155	}
a171fe39 AZ	156
a8170e5e	157	static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
b755bde3	158	unsigned size)
a171fe39	159	{
d353eb43	160	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	161	int tm = 0;
a171fe39 AZ	162
a171fe39 AZ	163	switch (offset) {
a171fe39 AZ	164	case OSMR3: tm ++;
de16017d	165	/* fall through */
a171fe39	166	case OSMR2: tm ++;
de16017d	167	/* fall through */
a171fe39	168	case OSMR1: tm ++;
de16017d	169	/* fall through */
a171fe39 AZ	170	case OSMR0:
	171	return s->timer[tm].value;
	172	case OSMR11: tm ++;
de16017d	173	/* fall through */
a171fe39	174	case OSMR10: tm ++;
de16017d	175	/* fall through */
a171fe39	176	case OSMR9: tm ++;
de16017d	177	/* fall through */
a171fe39	178	case OSMR8: tm ++;
de16017d	179	/* fall through */
a171fe39	180	case OSMR7: tm ++;
de16017d	181	/* fall through */
a171fe39	182	case OSMR6: tm ++;
de16017d	183	/* fall through */
a171fe39	184	case OSMR5: tm ++;
de16017d	185	/* fall through */
a171fe39	186	case OSMR4:
797e9542	187	if (!pxa2xx_timer_has_tm4(s))
a171fe39	188	goto badreg;
3bdd58a4	189	return s->tm4[tm].tm.value;
a171fe39	190	case OSCR:
bc72ad67	191	return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
6ee093c9	192	s->lastload, s->freq, get_ticks_per_sec());
a171fe39	193	case OSCR11: tm ++;
de16017d	194	/* fall through */
a171fe39	195	case OSCR10: tm ++;
de16017d	196	/* fall through */
a171fe39	197	case OSCR9: tm ++;
de16017d	198	/* fall through */
a171fe39	199	case OSCR8: tm ++;
de16017d	200	/* fall through */
a171fe39	201	case OSCR7: tm ++;
de16017d	202	/* fall through */
a171fe39	203	case OSCR6: tm ++;
de16017d	204	/* fall through */
a171fe39	205	case OSCR5: tm ++;
de16017d	206	/* fall through */
a171fe39	207	case OSCR4:
797e9542	208	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	209	goto badreg;
	210
	211	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	212	if (s->tm4[tm - 1].freq)
	213	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
bc72ad67	214	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
a171fe39	215	s->tm4[tm - 1].lastload,
6ee093c9	216	s->tm4[tm - 1].freq, get_ticks_per_sec());
a171fe39 AZ	217	else
	218	s->snapshot = s->tm4[tm - 1].clock;
	219	}
	220
	221	if (!s->tm4[tm].freq)
	222	return s->tm4[tm].clock;
bc72ad67	223	return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
6ee093c9	224	s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
a171fe39 AZ	225	case OIER:
	226	return s->irq_enabled;
	227	case OSSR: /* Status register */
	228	return s->events;
	229	case OWER:
	230	return s->reset3;
	231	case OMCR11: tm ++;
de16017d	232	/* fall through */
a171fe39	233	case OMCR10: tm ++;
de16017d	234	/* fall through */
a171fe39	235	case OMCR9: tm ++;
de16017d	236	/* fall through */
a171fe39	237	case OMCR8: tm ++;
de16017d	238	/* fall through */
a171fe39	239	case OMCR7: tm ++;
de16017d	240	/* fall through */
a171fe39	241	case OMCR6: tm ++;
de16017d	242	/* fall through */
a171fe39	243	case OMCR5: tm ++;
de16017d	244	/* fall through */
a171fe39	245	case OMCR4:
797e9542	246	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	247	goto badreg;
	248	return s->tm4[tm].control;
	249	case OSNR:
	250	return s->snapshot;
	251	default:
	252	badreg:
2ac71179	253	hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	254	}
	255
	256	return 0;
	257	}
	258
a8170e5e	259	static void pxa2xx_timer_write(void *opaque, hwaddr offset,
b755bde3	260	uint64_t value, unsigned size)
a171fe39 AZ	261	{
a171fe39 AZ	262	int i, tm = 0;
d353eb43	263	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	264
a171fe39 AZ	265	switch (offset) {
a171fe39 AZ	266	case OSMR3: tm ++;
de16017d	267	/* fall through */
a171fe39	268	case OSMR2: tm ++;
de16017d	269	/* fall through */
a171fe39	270	case OSMR1: tm ++;
de16017d	271	/* fall through */
a171fe39 AZ	272	case OSMR0:
a171fe39 AZ	273	s->timer[tm].value = value;
bc72ad67	274	pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
a171fe39 AZ	275	break;
a171fe39 AZ	276	case OSMR11: tm ++;
de16017d	277	/* fall through */
a171fe39	278	case OSMR10: tm ++;
de16017d	279	/* fall through */
a171fe39	280	case OSMR9: tm ++;
de16017d	281	/* fall through */
a171fe39	282	case OSMR8: tm ++;
de16017d	283	/* fall through */
a171fe39	284	case OSMR7: tm ++;
de16017d	285	/* fall through */
a171fe39	286	case OSMR6: tm ++;
de16017d	287	/* fall through */
a171fe39	288	case OSMR5: tm ++;
de16017d	289	/* fall through */
a171fe39	290	case OSMR4:
797e9542	291	if (!pxa2xx_timer_has_tm4(s))
a171fe39	292	goto badreg;
3bdd58a4	293	s->tm4[tm].tm.value = value;
bc72ad67	294	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	295	break;
	296	case OSCR:
	297	s->oldclock = s->clock;
bc72ad67	298	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	299	s->clock = value;
	300	pxa2xx_timer_update(s, s->lastload);
	301	break;
	302	case OSCR11: tm ++;
de16017d	303	/* fall through */
a171fe39	304	case OSCR10: tm ++;
de16017d	305	/* fall through */
a171fe39	306	case OSCR9: tm ++;
de16017d	307	/* fall through */
a171fe39	308	case OSCR8: tm ++;
de16017d	309	/* fall through */
a171fe39	310	case OSCR7: tm ++;
de16017d	311	/* fall through */
a171fe39	312	case OSCR6: tm ++;
de16017d	313	/* fall through */
a171fe39	314	case OSCR5: tm ++;
de16017d	315	/* fall through */
a171fe39	316	case OSCR4:
797e9542	317	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	318	goto badreg;
a171fe39 AZ	319	s->tm4[tm].oldclock = s->tm4[tm].clock;
bc72ad67	320	s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	321	s->tm4[tm].clock = value;
	322	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	323	break;
	324	case OIER:
	325	s->irq_enabled = value & 0xfff;
	326	break;
	327	case OSSR: /* Status register */
8034ce7d	328	value &= s->events;
a171fe39	329	s->events &= ~value;
8034ce7d AZ	330	for (i = 0; i < 4; i ++, value >>= 1)
8034ce7d AZ	331	if (value & 1)
5251d196	332	qemu_irq_lower(s->timer[i].irq);
8034ce7d AZ	333	if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
8034ce7d AZ	334	qemu_irq_lower(s->irq4);
a171fe39 AZ	335	break;
	336	case OWER: /* XXX: Reset on OSMR3 match? */
	337	s->reset3 = value;
	338	break;
	339	case OMCR7: tm ++;
de16017d	340	/* fall through */
a171fe39	341	case OMCR6: tm ++;
de16017d	342	/* fall through */
a171fe39	343	case OMCR5: tm ++;
de16017d	344	/* fall through */
a171fe39	345	case OMCR4:
797e9542	346	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	347	goto badreg;
	348	s->tm4[tm].control = value & 0x0ff;
	349	/* XXX Stop if running (shouldn't happen) */
	350	if ((value & (1 << 7)) \|\| tm == 0)
	351	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	352	else {
	353	s->tm4[tm].freq = 0;
bc72ad67	354	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	355	}
	356	break;
	357	case OMCR11: tm ++;
de16017d	358	/* fall through */
a171fe39	359	case OMCR10: tm ++;
de16017d	360	/* fall through */
a171fe39	361	case OMCR9: tm ++;
de16017d	362	/* fall through */
a171fe39	363	case OMCR8: tm += 4;
797e9542	364	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	365	goto badreg;
	366	s->tm4[tm].control = value & 0x3ff;
	367	/* XXX Stop if running (shouldn't happen) */
	368	if ((value & (1 << 7)) \|\| !(tm & 1))
	369	s->tm4[tm].freq =
	370	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	371	else {
	372	s->tm4[tm].freq = 0;
bc72ad67	373	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	374	}
	375	break;
	376	default:
	377	badreg:
2ac71179	378	hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	379	}
	380	}
	381
b755bde3 BC	382	static const MemoryRegionOps pxa2xx_timer_ops = {
	383	.read = pxa2xx_timer_read,
	384	.write = pxa2xx_timer_write,
	385	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	386	};
	387
	388	static void pxa2xx_timer_tick(void *opaque)
	389	{
bc24a225	390	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
797e9542	391	PXA2xxTimerInfo *i = t->info;
a171fe39 AZ	392
a171fe39 AZ	393	if (i->irq_enabled & (1 << t->num)) {
a171fe39	394	i->events \|= 1 << t->num;
5251d196	395	qemu_irq_raise(t->irq);
a171fe39 AZ	396	}
	397
	398	if (t->num == 3)
	399	if (i->reset3 & 1) {
	400	i->reset3 = 0;
3f582262	401	qemu_system_reset_request();
a171fe39 AZ	402	}
	403	}
	404
	405	static void pxa2xx_timer_tick4(void *opaque)
	406	{
bc24a225	407	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	408	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	409
3bdd58a4	410	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	411	if (t->control & (1 << 3))
	412	t->clock = 0;
	413	if (t->control & (1 << 6))
bc72ad67	414	pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
4ff927cc DES	415	if (i->events & 0xff0)
4ff927cc DES	416	qemu_irq_raise(i->irq4);
a171fe39 AZ	417	}
a171fe39 AZ	418
797e9542	419	static int pxa25x_timer_post_load(void *opaque, int version_id)
aa941b94	420	{
d353eb43	421	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	422	int64_t now;
	423	int i;
	424
bc72ad67	425	now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
aa941b94 AZ	426	pxa2xx_timer_update(s, now);
aa941b94 AZ	427
797e9542 DES	428	if (pxa2xx_timer_has_tm4(s))
797e9542 DES	429	for (i = 0; i < 8; i ++)
aa941b94	430	pxa2xx_timer_update4(s, now, i);
aa941b94 AZ	431
	432	return 0;
	433	}
	434
797e9542	435	static int pxa2xx_timer_init(SysBusDevice *dev)
a171fe39	436	{
feea4361	437	PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
a171fe39	438	int i;
a171fe39	439
a171fe39 AZ	440	s->irq_enabled = 0;
	441	s->oldclock = 0;
	442	s->clock = 0;
bc72ad67	443	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39	444	s->reset3 = 0;
a171fe39 AZ	445
	446	for (i = 0; i < 4; i ++) {
	447	s->timer[i].value = 0;
5251d196	448	sysbus_init_irq(dev, &s->timer[i].irq);
a171fe39 AZ	449	s->timer[i].info = s;
a171fe39 AZ	450	s->timer[i].num = i;
bc72ad67	451	s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a171fe39 AZ	452	pxa2xx_timer_tick, &s->timer[i]);
a171fe39 AZ	453	}
797e9542	454	if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
4ff927cc	455	sysbus_init_irq(dev, &s->irq4);
797e9542 DES	456
	457	for (i = 0; i < 8; i ++) {
	458	s->tm4[i].tm.value = 0;
	459	s->tm4[i].tm.info = s;
	460	s->tm4[i].tm.num = i + 4;
797e9542 DES	461	s->tm4[i].freq = 0;
797e9542 DES	462	s->tm4[i].control = 0x0;
bc72ad67	463	s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
797e9542 DES	464	pxa2xx_timer_tick4, &s->tm4[i]);
	465	}
	466	}
a171fe39	467
853dca12	468	memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_timer_ops, s,
b755bde3	469	"pxa2xx-timer", 0x00001000);
750ecd44	470	sysbus_init_mmio(dev, &s->iomem);
aa941b94	471
797e9542	472	return 0;
a171fe39 AZ	473	}
a171fe39 AZ	474
797e9542 DES	475	static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
797e9542 DES	476	.name = "pxa2xx_timer0",
8034ce7d AZ	477	.version_id = 2,
	478	.minimum_version_id = 2,
	479	.minimum_version_id_old = 2,
797e9542 DES	480	.fields = (VMStateField[]) {
797e9542 DES	481	VMSTATE_UINT32(value, PXA2xxTimer0),
797e9542 DES	482	VMSTATE_END_OF_LIST(),
	483	},
	484	};
	485
	486	static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
	487	.name = "pxa2xx_timer4",
	488	.version_id = 1,
	489	.minimum_version_id = 1,
	490	.minimum_version_id_old = 1,
	491	.fields = (VMStateField[]) {
	492	VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
	493	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	494	VMSTATE_INT32(oldclock, PXA2xxTimer4),
	495	VMSTATE_INT32(clock, PXA2xxTimer4),
	496	VMSTATE_UINT64(lastload, PXA2xxTimer4),
	497	VMSTATE_UINT32(freq, PXA2xxTimer4),
	498	VMSTATE_UINT32(control, PXA2xxTimer4),
	499	VMSTATE_END_OF_LIST(),
	500	},
	501	};
	502
	503	static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
a171fe39	504	{
797e9542	505	return pxa2xx_timer_has_tm4(opaque);
a171fe39 AZ	506	}
a171fe39 AZ	507
797e9542 DES	508	static const VMStateDescription vmstate_pxa2xx_timer_regs = {
	509	.name = "pxa2xx_timer",
	510	.version_id = 1,
	511	.minimum_version_id = 1,
	512	.minimum_version_id_old = 1,
	513	.post_load = pxa25x_timer_post_load,
	514	.fields = (VMStateField[]) {
	515	VMSTATE_INT32(clock, PXA2xxTimerInfo),
	516	VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
	517	VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
	518	VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
	519	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	520	VMSTATE_UINT32(events, PXA2xxTimerInfo),
	521	VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
	522	VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
	523	VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
	524	VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
	525	pxa2xx_timer_has_tm4_test, 0,
	526	vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
	527	VMSTATE_END_OF_LIST(),
a171fe39	528	}
797e9542 DES	529	};
797e9542 DES	530
999e12bb AL	531	static Property pxa25x_timer_dev_properties[] = {
	532	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
	533	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	534	PXA2XX_TIMER_HAVE_TM4, false),
999e12bb	535	DEFINE_PROP_END_OF_LIST(),
797e9542 DES	536	};
797e9542 DES	537
999e12bb AL	538	static void pxa25x_timer_dev_class_init(ObjectClass klass, void data)
999e12bb AL	539	{
39bffca2	540	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	541
39bffca2	542	dc->desc = "PXA25x timer";
39bffca2	543	dc->props = pxa25x_timer_dev_properties;
999e12bb AL	544	}
999e12bb AL	545
8c43a6f0	546	static const TypeInfo pxa25x_timer_dev_info = {
39bffca2	547	.name = "pxa25x-timer",
feea4361	548	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	549	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	550	.class_init = pxa25x_timer_dev_class_init,
999e12bb AL	551	};
	552
	553	static Property pxa27x_timer_dev_properties[] = {
	554	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
	555	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	556	PXA2XX_TIMER_HAVE_TM4, true),
999e12bb AL	557	DEFINE_PROP_END_OF_LIST(),
	558	};
	559
	560	static void pxa27x_timer_dev_class_init(ObjectClass klass, void data)
	561	{
39bffca2	562	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	563
39bffca2	564	dc->desc = "PXA27x timer";
39bffca2	565	dc->props = pxa27x_timer_dev_properties;
999e12bb AL	566	}
999e12bb AL	567
8c43a6f0	568	static const TypeInfo pxa27x_timer_dev_info = {
39bffca2	569	.name = "pxa27x-timer",
feea4361	570	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	571	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	572	.class_init = pxa27x_timer_dev_class_init,
797e9542 DES	573	};
797e9542 DES	574
feea4361 AF	575	static void pxa2xx_timer_class_init(ObjectClass oc, void data)
	576	{
	577	DeviceClass *dc = DEVICE_CLASS(oc);
	578	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc);
	579
	580	sdc->init = pxa2xx_timer_init;
	581	dc->vmsd = &vmstate_pxa2xx_timer_regs;
	582	}
	583
	584	static const TypeInfo pxa2xx_timer_type_info = {
	585	.name = TYPE_PXA2XX_TIMER,
	586	.parent = TYPE_SYS_BUS_DEVICE,
	587	.instance_size = sizeof(PXA2xxTimerInfo),
	588	.abstract = true,
	589	.class_init = pxa2xx_timer_class_init,
	590	};
	591
83f7d43a	592	static void pxa2xx_timer_register_types(void)
797e9542	593	{
feea4361	594	type_register_static(&pxa2xx_timer_type_info);
39bffca2 AL	595	type_register_static(&pxa25x_timer_dev_info);
39bffca2 AL	596	type_register_static(&pxa27x_timer_dev_info);
83f7d43a AF	597	}
	598
	599	type_init(pxa2xx_timer_register_types)