[qemu.git] / hw / display / ati_2d.c

/*
 * QEMU ATI SVGA emulation
 * 2D engine functions
 *
 * Copyright (c) 2019 BALATON Zoltan
 *
 * This work is licensed under the GNU GPL license version 2 or later.
 */

#include "qemu/osdep.h"
#include "ati_int.h"
#include "ati_regs.h"
#include "qemu/log.h"
#include "ui/pixel_ops.h"

/*
 * NOTE:
 * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
 * reinvent the wheel (unlikely to get better with a naive implementation than
 * existing libraries) and avoid (poorly) reimplementing gfx primitives.
 * That is unnecessary and would become a performance problem. Instead, try to
 * map to and reuse existing optimised facilities (e.g. pixman) wherever
 * possible.
 */

static int ati_bpp_from_datatype(ATIVGAState *s)
{
    switch (s->regs.dp_datatype & 0xf) {
    case 2:
        return 8;
    case 3:
    case 4:
        return 16;
    case 5:
        return 24;
    case 6:
        return 32;
    default:
        qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
                      s->regs.dp_datatype & 0xf);
        return 0;
    }
}

#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)

void ati_2d_blt(ATIVGAState *s)
{
    /* FIXME it is probably more complex than this and may need to be */
    /* rewritten but for now as a start just to get some output: */
    DisplaySurface *ds = qemu_console_surface(s->vga.con);
    DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
            s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
            surface_bits_per_pixel(ds),
            (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
    int dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
                 s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
    int dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
                 s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
    int bpp = ati_bpp_from_datatype(s);
    int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
    uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
                        s->regs.dst_offset : s->regs.default_offset);

    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
        dst_bits += s->regs.crtc_offset & 0x07ffffff;
        dst_stride *= bpp;
    }
    uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
    if (dst_bits >= end || dst_bits + dst_x + (dst_y + s->regs.dst_height) *
        dst_stride >= end) {
        qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
        return;
    }
    DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
            s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
            s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
            s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
            s->regs.dst_width, s->regs.dst_height,
            (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
            (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
    switch (s->regs.dp_mix & GMC_ROP3_MASK) {
    case ROP3_SRCCOPY:
    {
        int src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
                     s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
        int src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
                     s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
        int src_stride = DEFAULT_CNTL ?
                         s->regs.src_pitch : s->regs.default_pitch;
        uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
                            s->regs.src_offset : s->regs.default_offset);

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
            src_bits += s->regs.crtc_offset & 0x07ffffff;
            src_stride *= bpp;
        }
        if (src_bits >= end || src_bits + src_x +
            (src_y + s->regs.dst_height) * src_stride >= end) {
            qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
            return;
        }

        src_stride /= sizeof(uint32_t);
        dst_stride /= sizeof(uint32_t);
        DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
                src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
                src_x, src_y, dst_x, dst_y,
                s->regs.dst_width, s->regs.dst_height);
        if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
            s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
            pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
                       src_stride, dst_stride, bpp, bpp,
                       src_x, src_y, dst_x, dst_y,
                       s->regs.dst_width, s->regs.dst_height);
        } else {
            /* FIXME: We only really need a temporary if src and dst overlap */
            int llb = s->regs.dst_width * (bpp / 8);
            int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
            uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *
                                     s->regs.dst_height);
            pixman_blt((uint32_t *)src_bits, tmp,
                       src_stride, tmp_stride, bpp, bpp,
                       src_x, src_y, 0, 0,
                       s->regs.dst_width, s->regs.dst_height);
            pixman_blt(tmp, (uint32_t *)dst_bits,
                       tmp_stride, dst_stride, bpp, bpp,
                       0, 0, dst_x, dst_y,
                       s->regs.dst_width, s->regs.dst_height);
            g_free(tmp);
        }
        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
                                    s->regs.dst_offset +
                                    dst_y * surface_stride(ds),
                                    s->regs.dst_height * surface_stride(ds));
        }
        s->regs.dst_x += s->regs.dst_width;
        s->regs.dst_y += s->regs.dst_height;
        break;
    }
    case ROP3_PATCOPY:
    case ROP3_BLACKNESS:
    case ROP3_WHITENESS:
    {
        uint32_t filler = 0;

        switch (s->regs.dp_mix & GMC_ROP3_MASK) {
        case ROP3_PATCOPY:
            filler = s->regs.dp_brush_frgd_clr;
            break;
        case ROP3_BLACKNESS:
            filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],
                     s->vga.palette[1], s->vga.palette[2]);
            break;
        case ROP3_WHITENESS:
            filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],
                     s->vga.palette[4], s->vga.palette[5]);
            break;
        }

        dst_stride /= sizeof(uint32_t);
        DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
                dst_bits, dst_stride, bpp,
                s->regs.dst_x, s->regs.dst_y,
                s->regs.dst_width, s->regs.dst_height,
                filler);
        pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
                    s->regs.dst_x, s->regs.dst_y,
                    s->regs.dst_width, s->regs.dst_height,
                    filler);
        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
                                    s->regs.dst_offset +
                                    dst_y * surface_stride(ds),
                                    s->regs.dst_height * surface_stride(ds));
        }
        s->regs.dst_y += s->regs.dst_height;
        break;
    }
    default:
        qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
                      (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
    }
}
Commit	Line	Data
862b4a29 BZ	1	/*
	2	* QEMU ATI SVGA emulation
	3	* 2D engine functions
	4	*
	5	* Copyright (c) 2019 BALATON Zoltan
	6	*
	7	* This work is licensed under the GNU GPL license version 2 or later.
	8	*/
	9
bbfff196	10	#include "qemu/osdep.h"
862b4a29 BZ	11	#include "ati_int.h"
	12	#include "ati_regs.h"
	13	#include "qemu/log.h"
	14	#include "ui/pixel_ops.h"
	15
	16	/*
	17	* NOTE:
	18	* This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
	19	* reinvent the wheel (unlikely to get better with a naive implementation than
	20	* existing libraries) and avoid (poorly) reimplementing gfx primitives.
	21	* That is unnecessary and would become a performance problem. Instead, try to
	22	* map to and reuse existing optimised facilities (e.g. pixman) wherever
	23	* possible.
	24	*/
	25
	26	static int ati_bpp_from_datatype(ATIVGAState *s)
	27	{
	28	switch (s->regs.dp_datatype & 0xf) {
	29	case 2:
	30	return 8;
	31	case 3:
	32	case 4:
	33	return 16;
	34	case 5:
	35	return 24;
	36	case 6:
	37	return 32;
	38	default:
	39	qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
	40	s->regs.dp_datatype & 0xf);
	41	return 0;
	42	}
	43	}
	44
c799d2ee BZ	45	#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
c799d2ee BZ	46
862b4a29 BZ	47	void ati_2d_blt(ATIVGAState *s)
	48	{
	49	/* FIXME it is probably more complex than this and may need to be */
	50	/* rewritten but for now as a start just to get some output: */
	51	DisplaySurface *ds = qemu_console_surface(s->vga.con);
	52	DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
	53	s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
	54	surface_bits_per_pixel(ds),
	55	(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
584acf34 BZ	56	int dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
	57	s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
	58	int dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
	59	s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
c799d2ee BZ	60	int bpp = ati_bpp_from_datatype(s);
	61	int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
	62	uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
	63	s->regs.dst_offset : s->regs.default_offset);
	64
	65	if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
	66	dst_bits += s->regs.crtc_offset & 0x07ffffff;
	67	dst_stride *= bpp;
	68	}
	69	uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
584acf34	70	if (dst_bits >= end \|\| dst_bits + dst_x + (dst_y + s->regs.dst_height) *
c799d2ee BZ	71	dst_stride >= end) {
	72	qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
	73	return;
	74	}
584acf34	75	DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
866ad5f5 BZ	76	s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
866ad5f5 BZ	77	s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
862b4a29	78	s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
584acf34 BZ	79	s->regs.dst_width, s->regs.dst_height,
	80	(s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
	81	(s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
862b4a29 BZ	82	switch (s->regs.dp_mix & GMC_ROP3_MASK) {
	83	case ROP3_SRCCOPY:
	84	{
584acf34 BZ	85	int src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
	86	s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
	87	int src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
	88	s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
c799d2ee BZ	89	int src_stride = DEFAULT_CNTL ?
	90	s->regs.src_pitch : s->regs.default_pitch;
	91	uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
	92	s->regs.src_offset : s->regs.default_offset);
862b4a29 BZ	93
	94	if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
	95	src_bits += s->regs.crtc_offset & 0x07ffffff;
862b4a29	96	src_stride *= bpp;
862b4a29	97	}
584acf34 BZ	98	if (src_bits >= end \|\| src_bits + src_x +
584acf34 BZ	99	(src_y + s->regs.dst_height) * src_stride >= end) {
c799d2ee BZ	100	qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
	101	return;
	102	}
	103
862b4a29 BZ	104	src_stride /= sizeof(uint32_t);
862b4a29 BZ	105	dst_stride /= sizeof(uint32_t);
862b4a29 BZ	106	DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
862b4a29 BZ	107	src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
584acf34	108	src_x, src_y, dst_x, dst_y,
862b4a29	109	s->regs.dst_width, s->regs.dst_height);
584acf34 BZ	110	if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
	111	s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
	112	pixman_blt((uint32_t )src_bits, (uint32_t )dst_bits,
	113	src_stride, dst_stride, bpp, bpp,
	114	src_x, src_y, dst_x, dst_y,
	115	s->regs.dst_width, s->regs.dst_height);
	116	} else {
	117	/* FIXME: We only really need a temporary if src and dst overlap */
	118	int llb = s->regs.dst_width * (bpp / 8);
	119	int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
	120	uint32_t tmp = g_malloc(tmp_stride sizeof(uint32_t) *
	121	s->regs.dst_height);
	122	pixman_blt((uint32_t *)src_bits, tmp,
	123	src_stride, tmp_stride, bpp, bpp,
	124	src_x, src_y, 0, 0,
	125	s->regs.dst_width, s->regs.dst_height);
	126	pixman_blt(tmp, (uint32_t *)dst_bits,
	127	tmp_stride, dst_stride, bpp, bpp,
	128	0, 0, dst_x, dst_y,
	129	s->regs.dst_width, s->regs.dst_height);
	130	g_free(tmp);
	131	}
862b4a29 BZ	132	if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
	133	dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
	134	s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
	135	memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
	136	s->regs.dst_offset +
584acf34	137	dst_y * surface_stride(ds),
862b4a29 BZ	138	s->regs.dst_height * surface_stride(ds));
	139	}
	140	s->regs.dst_x += s->regs.dst_width;
	141	s->regs.dst_y += s->regs.dst_height;
	142	break;
	143	}
	144	case ROP3_PATCOPY:
	145	case ROP3_BLACKNESS:
	146	case ROP3_WHITENESS:
	147	{
862b4a29	148	uint32_t filler = 0;
862b4a29 BZ	149
	150	switch (s->regs.dp_mix & GMC_ROP3_MASK) {
	151	case ROP3_PATCOPY:
a3812741	152	filler = s->regs.dp_brush_frgd_clr;
862b4a29 BZ	153	break;
862b4a29 BZ	154	case ROP3_BLACKNESS:
a3812741 BZ	155	filler = 0xffUL << 24 \| rgb_to_pixel32(s->vga.palette[0],
a3812741 BZ	156	s->vga.palette[1], s->vga.palette[2]);
862b4a29 BZ	157	break;
862b4a29 BZ	158	case ROP3_WHITENESS:
a3812741 BZ	159	filler = 0xffUL << 24 \| rgb_to_pixel32(s->vga.palette[3],
a3812741 BZ	160	s->vga.palette[4], s->vga.palette[5]);
862b4a29 BZ	161	break;
	162	}
	163
c799d2ee	164	dst_stride /= sizeof(uint32_t);
862b4a29 BZ	165	DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
	166	dst_bits, dst_stride, bpp,
	167	s->regs.dst_x, s->regs.dst_y,
	168	s->regs.dst_width, s->regs.dst_height,
	169	filler);
862b4a29	170	pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
c799d2ee BZ	171	s->regs.dst_x, s->regs.dst_y,
	172	s->regs.dst_width, s->regs.dst_height,
	173	filler);
862b4a29 BZ	174	if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
	175	dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
	176	s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
	177	memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
	178	s->regs.dst_offset +
584acf34	179	dst_y * surface_stride(ds),
862b4a29 BZ	180	s->regs.dst_height * surface_stride(ds));
	181	}
	182	s->regs.dst_y += s->regs.dst_height;
	183	break;
	184	}
	185	default:
	186	qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
	187	(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
	188	}
	189	}