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[qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
0e607a80 26#include "host-utils.h"
4c5b10b7 27#include "hw/pc.h"
408392b3 28#include "hw/apic.h"
35bed8ee 29#include "ioport.h"
05330448 30
bb0300dc
GN		 31#ifdef CONFIG_KVM_PARA
32#include <linux/kvm_para.h>
33#endif
34//
05330448
AL		 35//#define DEBUG_KVM
36
37#ifdef DEBUG_KVM
8c0d577e 38#define DPRINTF(fmt, ...) \
05330448
AL		 39 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
40#else
8c0d577e 41#define DPRINTF(fmt, ...) \
05330448
AL		 42 do { } while (0)
43#endif
44
1a03675d
GC		 45#define MSR_KVM_WALL_CLOCK 0x11
46#define MSR_KVM_SYSTEM_TIME 0x12
47
b827df58
AK		 48#ifdef KVM_CAP_EXT_CPUID
49
50static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
51{
52 struct kvm_cpuid2 *cpuid;
53 int r, size;
54
55 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
56 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
57 cpuid->nent = max;
58 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 59 if (r == 0 && cpuid->nent >= max) {
60 r = -E2BIG;
61 }
b827df58
AK		 62 if (r < 0) {
63 if (r == -E2BIG) {
64 qemu_free(cpuid);
65 return NULL;
66 } else {
67 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
68 strerror(-r));
69 exit(1);
70 }
71 }
72 return cpuid;
73}
74
c958a8bd
SY		 75uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
76 uint32_t index, int reg)
b827df58
AK		 77{
78 struct kvm_cpuid2 *cpuid;
79 int i, max;
80 uint32_t ret = 0;
81 uint32_t cpuid_1_edx;
82
83 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
84 return -1U;
85 }
86
87 max = 1;
88 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
89 max *= 2;
90 }
91
92 for (i = 0; i < cpuid->nent; ++i) {
c958a8bd
SY		 93 if (cpuid->entries[i].function == function &&
94 cpuid->entries[i].index == index) {
b827df58
AK		 95 switch (reg) {
96 case R_EAX:
97 ret = cpuid->entries[i].eax;
98 break;
99 case R_EBX:
100 ret = cpuid->entries[i].ebx;
101 break;
102 case R_ECX:
103 ret = cpuid->entries[i].ecx;
104 break;
105 case R_EDX:
106 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 107 switch (function) {
108 case 1:
109 /* KVM before 2.6.30 misreports the following features */
110 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
111 break;
112 case 0x80000001:
b827df58
AK		 113 /* On Intel, kvm returns cpuid according to the Intel spec,
114 * so add missing bits according to the AMD spec:
115 */
c958a8bd 116 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
c1667e40 117 ret |= cpuid_1_edx & 0x183f7ff;
19ccb8ea 118 break;
b827df58
AK		 119 }
120 break;
121 }
122 }
123 }
124
125 qemu_free(cpuid);
126
127 return ret;
128}
129
130#else
131
c958a8bd
SY		 132uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
133 uint32_t index, int reg)
b827df58
AK		 134{
135 return -1U;
136}
137
138#endif
139
bb0300dc
GN		 140#ifdef CONFIG_KVM_PARA
141struct kvm_para_features {
142 int cap;
143 int feature;
144} para_features[] = {
145#ifdef KVM_CAP_CLOCKSOURCE
146 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
147#endif
148#ifdef KVM_CAP_NOP_IO_DELAY
149 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
150#endif
151#ifdef KVM_CAP_PV_MMU
152 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
bb0300dc
GN		 153#endif
154 { -1, -1 }
155};
156
157static int get_para_features(CPUState *env)
158{
159 int i, features = 0;
160
161 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
162 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
163 features |= (1 << para_features[i].feature);
164 }
165
166 return features;
167}
168#endif
169
05330448
AL		 170int kvm_arch_init_vcpu(CPUState *env)
171{
172 struct {
486bd5a2
AL		 173 struct kvm_cpuid2 cpuid;
174 struct kvm_cpuid_entry2 entries[100];
05330448 175 } __attribute__((packed)) cpuid_data;
486bd5a2 176 uint32_t limit, i, j, cpuid_i;
a33609ca 177 uint32_t unused;
bb0300dc
GN		 178 struct kvm_cpuid_entry2 *c;
179#ifdef KVM_CPUID_SIGNATURE
180 uint32_t signature[3];
181#endif
05330448 182
f8d926e9
JK		 183 env->mp_state = KVM_MP_STATE_RUNNABLE;
184
c958a8bd 185 env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
6c0d7ee8
AP		 186
187 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
c958a8bd 188 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
6c0d7ee8
AP		 189 env->cpuid_ext_features |= i;
190
457dfed6 191 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 192 0, R_EDX);
457dfed6 193 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 194 0, R_ECX);
6c1f42fe 195
05330448
AL		 196 cpuid_i = 0;
197
bb0300dc
GN		 198#ifdef CONFIG_KVM_PARA
199 /* Paravirtualization CPUIDs */
200 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
201 c = &cpuid_data.entries[cpuid_i++];
202 memset(c, 0, sizeof(*c));
203 c->function = KVM_CPUID_SIGNATURE;
204 c->eax = 0;
205 c->ebx = signature[0];
206 c->ecx = signature[1];
207 c->edx = signature[2];
208
209 c = &cpuid_data.entries[cpuid_i++];
210 memset(c, 0, sizeof(*c));
211 c->function = KVM_CPUID_FEATURES;
212 c->eax = env->cpuid_kvm_features & get_para_features(env);
213#endif
214
a33609ca 215 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 216
217 for (i = 0; i <= limit; i++) {
bb0300dc 218 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 219
220 switch (i) {
a36b1029
AL		 221 case 2: {
222 /* Keep reading function 2 till all the input is received */
223 int times;
224
a36b1029 225 c->function = i;
a33609ca
AL		 226 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
227 KVM_CPUID_FLAG_STATE_READ_NEXT;
228 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
229 times = c->eax & 0xff;
a36b1029
AL		 230
231 for (j = 1; j < times; ++j) {
a33609ca 232 c = &cpuid_data.entries[cpuid_i++];
a36b1029 233 c->function = i;
a33609ca
AL		 234 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
235 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 236 }
237 break;
238 }
486bd5a2
AL		 239 case 4:
240 case 0xb:
241 case 0xd:
242 for (j = 0; ; j++) {
486bd5a2
AL		 243 c->function = i;
244 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
245 c->index = j;
a33609ca 246 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 247
a33609ca 248 if (i == 4 && c->eax == 0)
486bd5a2 249 break;
a33609ca 250 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 251 break;
a33609ca 252 if (i == 0xd && c->eax == 0)
486bd5a2 253 break;
a33609ca
AL		 254
255 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 256 }
257 break;
258 default:
486bd5a2 259 c->function = i;
a33609ca
AL		 260 c->flags = 0;
261 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 262 break;
263 }
05330448 264 }
a33609ca 265 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 266
267 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 268 c = &cpuid_data.entries[cpuid_i++];
05330448 269
05330448 270 c->function = i;
a33609ca
AL		 271 c->flags = 0;
272 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 273 }
274
275 cpuid_data.cpuid.nent = cpuid_i;
276
486bd5a2 277 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 278}
279
caa5af0f
JK		 280void kvm_arch_reset_vcpu(CPUState *env)
281{
e73223a5 282 env->exception_injected = -1;
0e607a80 283 env->interrupt_injected = -1;
a0fb002c
JK		 284 env->nmi_injected = 0;
285 env->nmi_pending = 0;
ddced198
MT		 286 if (kvm_irqchip_in_kernel()) {
287 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
288 KVM_MP_STATE_UNINITIALIZED;
289 } else {
290 env->mp_state = KVM_MP_STATE_RUNNABLE;
291 }
caa5af0f
JK		 292}
293
05330448
AL		 294static int kvm_has_msr_star(CPUState *env)
295{
296 static int has_msr_star;
297 int ret;
298
299 /* first time */
300 if (has_msr_star == 0) {
301 struct kvm_msr_list msr_list, *kvm_msr_list;
302
303 has_msr_star = -1;
304
305 /* Obtain MSR list from KVM. These are the MSRs that we must
306 * save/restore */
4c9f7372 307 msr_list.nmsrs = 0;
05330448 308 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 309 if (ret < 0 && ret != -E2BIG) {
05330448 310 return 0;
6fb6d245 311 }
d9db889f
JK		 312 /* Old kernel modules had a bug and could write beyond the provided
313 memory. Allocate at least a safe amount of 1K. */
314 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
315 msr_list.nmsrs *
316 sizeof(msr_list.indices[0])));
05330448 317
55308450 318 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 319 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
320 if (ret >= 0) {
321 int i;
322
323 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
324 if (kvm_msr_list->indices[i] == MSR_STAR) {
325 has_msr_star = 1;
326 break;
327 }
328 }
329 }
330
331 free(kvm_msr_list);
332 }
333
334 if (has_msr_star == 1)
335 return 1;
336 return 0;
337}
338
20420430
SY		 339static int kvm_init_identity_map_page(KVMState *s)
340{
341#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
342 int ret;
343 uint64_t addr = 0xfffbc000;
344
345 if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
346 return 0;
347 }
348
349 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
350 if (ret < 0) {
351 fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
352 return ret;
353 }
354#endif
355 return 0;
356}
357
05330448
AL		 358int kvm_arch_init(KVMState *s, int smp_cpus)
359{
360 int ret;
361
362 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
363 * directly. In order to use vm86 mode, a TSS is needed. Since this
364 * must be part of guest physical memory, we need to allocate it. Older
365 * versions of KVM just assumed that it would be at the end of physical
366 * memory but that doesn't work with more than 4GB of memory. We simply
367 * refuse to work with those older versions of KVM. */
984b5181 368 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 369 if (ret <= 0) {
370 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
371 return ret;
372 }
373
374 /* this address is 3 pages before the bios, and the bios should present
375 * as unavaible memory. FIXME, need to ensure the e820 map deals with
376 * this?
377 */
4c5b10b7
JS		 378 /*
379 * Tell fw_cfg to notify the BIOS to reserve the range.
380 */
381 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
382 perror("e820_add_entry() table is full");
383 exit(1);
384 }
20420430
SY		 385 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
386 if (ret < 0) {
387 return ret;
388 }
389
390 return kvm_init_identity_map_page(s);
05330448
AL		 391}
392
393static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
394{
395 lhs->selector = rhs->selector;
396 lhs->base = rhs->base;
397 lhs->limit = rhs->limit;
398 lhs->type = 3;
399 lhs->present = 1;
400 lhs->dpl = 3;
401 lhs->db = 0;
402 lhs->s = 1;
403 lhs->l = 0;
404 lhs->g = 0;
405 lhs->avl = 0;
406 lhs->unusable = 0;
407}
408
409static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
410{
411 unsigned flags = rhs->flags;
412 lhs->selector = rhs->selector;
413 lhs->base = rhs->base;
414 lhs->limit = rhs->limit;
415 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
416 lhs->present = (flags & DESC_P_MASK) != 0;
417 lhs->dpl = rhs->selector & 3;
418 lhs->db = (flags >> DESC_B_SHIFT) & 1;
419 lhs->s = (flags & DESC_S_MASK) != 0;
420 lhs->l = (flags >> DESC_L_SHIFT) & 1;
421 lhs->g = (flags & DESC_G_MASK) != 0;
422 lhs->avl = (flags & DESC_AVL_MASK) != 0;
423 lhs->unusable = 0;
424}
425
426static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
427{
428 lhs->selector = rhs->selector;
429 lhs->base = rhs->base;
430 lhs->limit = rhs->limit;
431 lhs->flags =
432 (rhs->type << DESC_TYPE_SHIFT)
433 | (rhs->present * DESC_P_MASK)
434 | (rhs->dpl << DESC_DPL_SHIFT)
435 | (rhs->db << DESC_B_SHIFT)
436 | (rhs->s * DESC_S_MASK)
437 | (rhs->l << DESC_L_SHIFT)
438 | (rhs->g * DESC_G_MASK)
439 | (rhs->avl * DESC_AVL_MASK);
440}
441
442static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
443{
444 if (set)
445 *kvm_reg = *qemu_reg;
446 else
447 *qemu_reg = *kvm_reg;
448}
449
450static int kvm_getput_regs(CPUState *env, int set)
451{
452 struct kvm_regs regs;
453 int ret = 0;
454
455 if (!set) {
456 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
457 if (ret < 0)
458 return ret;
459 }
460
461 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
462 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
463 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
464 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
465 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
466 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
467 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
468 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
469#ifdef TARGET_X86_64
470 kvm_getput_reg(&regs.r8, &env->regs[8], set);
471 kvm_getput_reg(&regs.r9, &env->regs[9], set);
472 kvm_getput_reg(&regs.r10, &env->regs[10], set);
473 kvm_getput_reg(&regs.r11, &env->regs[11], set);
474 kvm_getput_reg(&regs.r12, &env->regs[12], set);
475 kvm_getput_reg(&regs.r13, &env->regs[13], set);
476 kvm_getput_reg(&regs.r14, &env->regs[14], set);
477 kvm_getput_reg(&regs.r15, &env->regs[15], set);
478#endif
479
480 kvm_getput_reg(&regs.rflags, &env->eflags, set);
481 kvm_getput_reg(&regs.rip, &env->eip, set);
482
483 if (set)
484 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
485
486 return ret;
487}
488
489static int kvm_put_fpu(CPUState *env)
490{
491 struct kvm_fpu fpu;
492 int i;
493
494 memset(&fpu, 0, sizeof fpu);
495 fpu.fsw = env->fpus & ~(7 << 11);
496 fpu.fsw |= (env->fpstt & 7) << 11;
497 fpu.fcw = env->fpuc;
498 for (i = 0; i < 8; ++i)
499 fpu.ftwx |= (!env->fptags[i]) << i;
500 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
501 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
502 fpu.mxcsr = env->mxcsr;
503
504 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
505}
506
f1665b21
SY		 507#ifdef KVM_CAP_XSAVE
508#define XSAVE_CWD_RIP 2
509#define XSAVE_CWD_RDP 4
510#define XSAVE_MXCSR 6
511#define XSAVE_ST_SPACE 8
512#define XSAVE_XMM_SPACE 40
513#define XSAVE_XSTATE_BV 128
514#define XSAVE_YMMH_SPACE 144
515#endif
516
517static int kvm_put_xsave(CPUState *env)
518{
519#ifdef KVM_CAP_XSAVE
520 int i;
521 struct kvm_xsave* xsave;
522 uint16_t cwd, swd, twd, fop;
523
524 if (!kvm_has_xsave())
525 return kvm_put_fpu(env);
526
527 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
528 memset(xsave, 0, sizeof(struct kvm_xsave));
529 cwd = swd = twd = fop = 0;
530 swd = env->fpus & ~(7 << 11);
531 swd |= (env->fpstt & 7) << 11;
532 cwd = env->fpuc;
533 for (i = 0; i < 8; ++i)
534 twd |= (!env->fptags[i]) << i;
535 xsave->region[0] = (uint32_t)(swd << 16) + cwd;
536 xsave->region[1] = (uint32_t)(fop << 16) + twd;
537 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
538 sizeof env->fpregs);
539 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
540 sizeof env->xmm_regs);
541 xsave->region[XSAVE_MXCSR] = env->mxcsr;
542 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
543 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
544 sizeof env->ymmh_regs);
545 return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
546#else
547 return kvm_put_fpu(env);
548#endif
549}
550
551static int kvm_put_xcrs(CPUState *env)
552{
553#ifdef KVM_CAP_XCRS
554 struct kvm_xcrs xcrs;
555
556 if (!kvm_has_xcrs())
557 return 0;
558
559 xcrs.nr_xcrs = 1;
560 xcrs.flags = 0;
561 xcrs.xcrs[0].xcr = 0;
562 xcrs.xcrs[0].value = env->xcr0;
563 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
564#else
565 return 0;
566#endif
567}
568
05330448
AL		 569static int kvm_put_sregs(CPUState *env)
570{
571 struct kvm_sregs sregs;
572
0e607a80
JK		 573 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
574 if (env->interrupt_injected >= 0) {
575 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
576 (uint64_t)1 << (env->interrupt_injected % 64);
577 }
05330448
AL		 578
579 if ((env->eflags & VM_MASK)) {
580 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
581 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
582 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
583 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
584 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
585 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
586 } else {
587 set_seg(&sregs.cs, &env->segs[R_CS]);
588 set_seg(&sregs.ds, &env->segs[R_DS]);
589 set_seg(&sregs.es, &env->segs[R_ES]);
590 set_seg(&sregs.fs, &env->segs[R_FS]);
591 set_seg(&sregs.gs, &env->segs[R_GS]);
592 set_seg(&sregs.ss, &env->segs[R_SS]);
593
594 if (env->cr[0] & CR0_PE_MASK) {
595 /* force ss cpl to cs cpl */
596 sregs.ss.selector = (sregs.ss.selector & ~3) |
597 (sregs.cs.selector & 3);
598 sregs.ss.dpl = sregs.ss.selector & 3;
599 }
600 }
601
602 set_seg(&sregs.tr, &env->tr);
603 set_seg(&sregs.ldt, &env->ldt);
604
605 sregs.idt.limit = env->idt.limit;
606 sregs.idt.base = env->idt.base;
607 sregs.gdt.limit = env->gdt.limit;
608 sregs.gdt.base = env->gdt.base;
609
610 sregs.cr0 = env->cr[0];
611 sregs.cr2 = env->cr[2];
612 sregs.cr3 = env->cr[3];
613 sregs.cr4 = env->cr[4];
614
4a942cea
BS		 615 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
616 sregs.apic_base = cpu_get_apic_base(env->apic_state);
05330448
AL		 617
618 sregs.efer = env->efer;
619
620 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
621}
622
623static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
624 uint32_t index, uint64_t value)
625{
626 entry->index = index;
627 entry->data = value;
628}
629
ea643051 630static int kvm_put_msrs(CPUState *env, int level)
05330448
AL		 631{
632 struct {
633 struct kvm_msrs info;
634 struct kvm_msr_entry entries[100];
635 } msr_data;
636 struct kvm_msr_entry *msrs = msr_data.entries;
637 int n = 0;
638
639 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
640 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
641 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
642 if (kvm_has_msr_star(env))
643 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
05330448
AL		 644#ifdef TARGET_X86_64
645 /* FIXME if lm capable */
646 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
647 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
648 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
649 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
650#endif
ea643051
JK		 651 if (level == KVM_PUT_FULL_STATE) {
652 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
653 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
654 env->system_time_msr);
655 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
656 }
1a03675d 657
05330448
AL		 658 msr_data.info.nmsrs = n;
659
660 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
661
662}
663
664
665static int kvm_get_fpu(CPUState *env)
666{
667 struct kvm_fpu fpu;
668 int i, ret;
669
670 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
671 if (ret < 0)
672 return ret;
673
674 env->fpstt = (fpu.fsw >> 11) & 7;
675 env->fpus = fpu.fsw;
676 env->fpuc = fpu.fcw;
677 for (i = 0; i < 8; ++i)
678 env->fptags[i] = !((fpu.ftwx >> i) & 1);
679 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
680 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
681 env->mxcsr = fpu.mxcsr;
682
683 return 0;
684}
685
f1665b21
SY		 686static int kvm_get_xsave(CPUState *env)
687{
688#ifdef KVM_CAP_XSAVE
689 struct kvm_xsave* xsave;
690 int ret, i;
691 uint16_t cwd, swd, twd, fop;
692
693 if (!kvm_has_xsave())
694 return kvm_get_fpu(env);
695
696 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
697 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
698 if (ret < 0)
699 return ret;
700
701 cwd = (uint16_t)xsave->region[0];
702 swd = (uint16_t)(xsave->region[0] >> 16);
703 twd = (uint16_t)xsave->region[1];
704 fop = (uint16_t)(xsave->region[1] >> 16);
705 env->fpstt = (swd >> 11) & 7;
706 env->fpus = swd;
707 env->fpuc = cwd;
708 for (i = 0; i < 8; ++i)
709 env->fptags[i] = !((twd >> i) & 1);
710 env->mxcsr = xsave->region[XSAVE_MXCSR];
711 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
712 sizeof env->fpregs);
713 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
714 sizeof env->xmm_regs);
715 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
716 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
717 sizeof env->ymmh_regs);
718 return 0;
719#else
720 return kvm_get_fpu(env);
721#endif
722}
723
724static int kvm_get_xcrs(CPUState *env)
725{
726#ifdef KVM_CAP_XCRS
727 int i, ret;
728 struct kvm_xcrs xcrs;
729
730 if (!kvm_has_xcrs())
731 return 0;
732
733 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
734 if (ret < 0)
735 return ret;
736
737 for (i = 0; i < xcrs.nr_xcrs; i++)
738 /* Only support xcr0 now */
739 if (xcrs.xcrs[0].xcr == 0) {
740 env->xcr0 = xcrs.xcrs[0].value;
741 break;
742 }
743 return 0;
744#else
745 return 0;
746#endif
747}
748
05330448
AL		 749static int kvm_get_sregs(CPUState *env)
750{
751 struct kvm_sregs sregs;
752 uint32_t hflags;
0e607a80 753 int bit, i, ret;
05330448
AL		 754
755 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
756 if (ret < 0)
757 return ret;
758
0e607a80
JK		 759 /* There can only be one pending IRQ set in the bitmap at a time, so try
760 to find it and save its number instead (-1 for none). */
761 env->interrupt_injected = -1;
762 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
763 if (sregs.interrupt_bitmap[i]) {
764 bit = ctz64(sregs.interrupt_bitmap[i]);
765 env->interrupt_injected = i * 64 + bit;
766 break;
767 }
768 }
05330448
AL		 769
770 get_seg(&env->segs[R_CS], &sregs.cs);
771 get_seg(&env->segs[R_DS], &sregs.ds);
772 get_seg(&env->segs[R_ES], &sregs.es);
773 get_seg(&env->segs[R_FS], &sregs.fs);
774 get_seg(&env->segs[R_GS], &sregs.gs);
775 get_seg(&env->segs[R_SS], &sregs.ss);
776
777 get_seg(&env->tr, &sregs.tr);
778 get_seg(&env->ldt, &sregs.ldt);
779
780 env->idt.limit = sregs.idt.limit;
781 env->idt.base = sregs.idt.base;
782 env->gdt.limit = sregs.gdt.limit;
783 env->gdt.base = sregs.gdt.base;
784
785 env->cr[0] = sregs.cr0;
786 env->cr[2] = sregs.cr2;
787 env->cr[3] = sregs.cr3;
788 env->cr[4] = sregs.cr4;
789
4a942cea 790 cpu_set_apic_base(env->apic_state, sregs.apic_base);
05330448
AL		 791
792 env->efer = sregs.efer;
4a942cea 793 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
05330448
AL		 794
795#define HFLAG_COPY_MASK ~( \
796 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
797 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
798 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
799 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
800
801
802
803 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
804 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
805 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
806 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
807 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
808 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
809 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
810
811 if (env->efer & MSR_EFER_LMA) {
812 hflags |= HF_LMA_MASK;
813 }
814
815 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
816 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
817 } else {
818 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
819 (DESC_B_SHIFT - HF_CS32_SHIFT);
820 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
821 (DESC_B_SHIFT - HF_SS32_SHIFT);
822 if (!(env->cr[0] & CR0_PE_MASK) ||
823 (env->eflags & VM_MASK) ||
824 !(hflags & HF_CS32_MASK)) {
825 hflags |= HF_ADDSEG_MASK;
826 } else {
827 hflags |= ((env->segs[R_DS].base |
828 env->segs[R_ES].base |
829 env->segs[R_SS].base) != 0) <<
830 HF_ADDSEG_SHIFT;
831 }
832 }
833 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 834
835 return 0;
836}
837
838static int kvm_get_msrs(CPUState *env)
839{
840 struct {
841 struct kvm_msrs info;
842 struct kvm_msr_entry entries[100];
843 } msr_data;
844 struct kvm_msr_entry *msrs = msr_data.entries;
845 int ret, i, n;
846
847 n = 0;
848 msrs[n++].index = MSR_IA32_SYSENTER_CS;
849 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
850 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
851 if (kvm_has_msr_star(env))
852 msrs[n++].index = MSR_STAR;
853 msrs[n++].index = MSR_IA32_TSC;
854#ifdef TARGET_X86_64
855 /* FIXME lm_capable_kernel */
856 msrs[n++].index = MSR_CSTAR;
857 msrs[n++].index = MSR_KERNELGSBASE;
858 msrs[n++].index = MSR_FMASK;
859 msrs[n++].index = MSR_LSTAR;
860#endif
1a03675d
GC		 861 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
862 msrs[n++].index = MSR_KVM_WALL_CLOCK;
863
05330448
AL		 864 msr_data.info.nmsrs = n;
865 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
866 if (ret < 0)
867 return ret;
868
869 for (i = 0; i < ret; i++) {
870 switch (msrs[i].index) {
871 case MSR_IA32_SYSENTER_CS:
872 env->sysenter_cs = msrs[i].data;
873 break;
874 case MSR_IA32_SYSENTER_ESP:
875 env->sysenter_esp = msrs[i].data;
876 break;
877 case MSR_IA32_SYSENTER_EIP:
878 env->sysenter_eip = msrs[i].data;
879 break;
880 case MSR_STAR:
881 env->star = msrs[i].data;
882 break;
883#ifdef TARGET_X86_64
884 case MSR_CSTAR:
885 env->cstar = msrs[i].data;
886 break;
887 case MSR_KERNELGSBASE:
888 env->kernelgsbase = msrs[i].data;
889 break;
890 case MSR_FMASK:
891 env->fmask = msrs[i].data;
892 break;
893 case MSR_LSTAR:
894 env->lstar = msrs[i].data;
895 break;
896#endif
897 case MSR_IA32_TSC:
898 env->tsc = msrs[i].data;
899 break;
1a03675d
GC		 900 case MSR_KVM_SYSTEM_TIME:
901 env->system_time_msr = msrs[i].data;
902 break;
903 case MSR_KVM_WALL_CLOCK:
904 env->wall_clock_msr = msrs[i].data;
905 break;
05330448
AL		 906 }
907 }
908
909 return 0;
910}
911
9bdbe550
HB		 912static int kvm_put_mp_state(CPUState *env)
913{
914 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
915
916 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
917}
918
919static int kvm_get_mp_state(CPUState *env)
920{
921 struct kvm_mp_state mp_state;
922 int ret;
923
924 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
925 if (ret < 0) {
926 return ret;
927 }
928 env->mp_state = mp_state.mp_state;
929 return 0;
930}
931
ea643051 932static int kvm_put_vcpu_events(CPUState *env, int level)
a0fb002c
JK		 933{
934#ifdef KVM_CAP_VCPU_EVENTS
935 struct kvm_vcpu_events events;
936
937 if (!kvm_has_vcpu_events()) {
938 return 0;
939 }
940
31827373
JK		 941 events.exception.injected = (env->exception_injected >= 0);
942 events.exception.nr = env->exception_injected;
a0fb002c
JK		 943 events.exception.has_error_code = env->has_error_code;
944 events.exception.error_code = env->error_code;
945
946 events.interrupt.injected = (env->interrupt_injected >= 0);
947 events.interrupt.nr = env->interrupt_injected;
948 events.interrupt.soft = env->soft_interrupt;
949
950 events.nmi.injected = env->nmi_injected;
951 events.nmi.pending = env->nmi_pending;
952 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
953
954 events.sipi_vector = env->sipi_vector;
955
ea643051
JK		 956 events.flags = 0;
957 if (level >= KVM_PUT_RESET_STATE) {
958 events.flags |=
959 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
960 }
aee028b9 961
a0fb002c
JK		 962 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
963#else
964 return 0;
965#endif
966}
967
968static int kvm_get_vcpu_events(CPUState *env)
969{
970#ifdef KVM_CAP_VCPU_EVENTS
971 struct kvm_vcpu_events events;
972 int ret;
973
974 if (!kvm_has_vcpu_events()) {
975 return 0;
976 }
977
978 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
979 if (ret < 0) {
980 return ret;
981 }
31827373 982 env->exception_injected =
a0fb002c
JK		 983 events.exception.injected ? events.exception.nr : -1;
984 env->has_error_code = events.exception.has_error_code;
985 env->error_code = events.exception.error_code;
986
987 env->interrupt_injected =
988 events.interrupt.injected ? events.interrupt.nr : -1;
989 env->soft_interrupt = events.interrupt.soft;
990
991 env->nmi_injected = events.nmi.injected;
992 env->nmi_pending = events.nmi.pending;
993 if (events.nmi.masked) {
994 env->hflags2 |= HF2_NMI_MASK;
995 } else {
996 env->hflags2 &= ~HF2_NMI_MASK;
997 }
998
999 env->sipi_vector = events.sipi_vector;
1000#endif
1001
1002 return 0;
1003}
1004
b0b1d690
JK		 1005static int kvm_guest_debug_workarounds(CPUState *env)
1006{
1007 int ret = 0;
1008#ifdef KVM_CAP_SET_GUEST_DEBUG
1009 unsigned long reinject_trap = 0;
1010
1011 if (!kvm_has_vcpu_events()) {
1012 if (env->exception_injected == 1) {
1013 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1014 } else if (env->exception_injected == 3) {
1015 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1016 }
1017 env->exception_injected = -1;
1018 }
1019
1020 /*
1021 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1022 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1023 * by updating the debug state once again if single-stepping is on.
1024 * Another reason to call kvm_update_guest_debug here is a pending debug
1025 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1026 * reinject them via SET_GUEST_DEBUG.
1027 */
1028 if (reinject_trap ||
1029 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1030 ret = kvm_update_guest_debug(env, reinject_trap);
1031 }
1032#endif /* KVM_CAP_SET_GUEST_DEBUG */
1033 return ret;
1034}
1035
ff44f1a3
JK		 1036static int kvm_put_debugregs(CPUState *env)
1037{
1038#ifdef KVM_CAP_DEBUGREGS
1039 struct kvm_debugregs dbgregs;
1040 int i;
1041
1042 if (!kvm_has_debugregs()) {
1043 return 0;
1044 }
1045
1046 for (i = 0; i < 4; i++) {
1047 dbgregs.db[i] = env->dr[i];
1048 }
1049 dbgregs.dr6 = env->dr[6];
1050 dbgregs.dr7 = env->dr[7];
1051 dbgregs.flags = 0;
1052
1053 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1054#else
1055 return 0;
1056#endif
1057}
1058
1059static int kvm_get_debugregs(CPUState *env)
1060{
1061#ifdef KVM_CAP_DEBUGREGS
1062 struct kvm_debugregs dbgregs;
1063 int i, ret;
1064
1065 if (!kvm_has_debugregs()) {
1066 return 0;
1067 }
1068
1069 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1070 if (ret < 0) {
1071 return ret;
1072 }
1073 for (i = 0; i < 4; i++) {
1074 env->dr[i] = dbgregs.db[i];
1075 }
1076 env->dr[4] = env->dr[6] = dbgregs.dr6;
1077 env->dr[5] = env->dr[7] = dbgregs.dr7;
1078#endif
1079
1080 return 0;
1081}
1082
ea375f9a 1083int kvm_arch_put_registers(CPUState *env, int level)
05330448
AL		 1084{
1085 int ret;
1086
dbaa07c4
JK		 1087 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1088
05330448
AL		 1089 ret = kvm_getput_regs(env, 1);
1090 if (ret < 0)
1091 return ret;
1092
f1665b21
SY		 1093 ret = kvm_put_xsave(env);
1094 if (ret < 0)
1095 return ret;
1096
1097 ret = kvm_put_xcrs(env);
05330448
AL		 1098 if (ret < 0)
1099 return ret;
1100
1101 ret = kvm_put_sregs(env);
1102 if (ret < 0)
1103 return ret;
1104
ea643051 1105 ret = kvm_put_msrs(env, level);
05330448
AL		 1106 if (ret < 0)
1107 return ret;
1108
ea643051
JK		 1109 if (level >= KVM_PUT_RESET_STATE) {
1110 ret = kvm_put_mp_state(env);
1111 if (ret < 0)
1112 return ret;
1113 }
f8d926e9 1114
ea643051 1115 ret = kvm_put_vcpu_events(env, level);
a0fb002c
JK		 1116 if (ret < 0)
1117 return ret;
1118
b0b1d690
JK		 1119 /* must be last */
1120 ret = kvm_guest_debug_workarounds(env);
1121 if (ret < 0)
1122 return ret;
1123
ff44f1a3
JK		 1124 ret = kvm_put_debugregs(env);
1125 if (ret < 0)
1126 return ret;
1127
05330448
AL		 1128 return 0;
1129}
1130
1131int kvm_arch_get_registers(CPUState *env)
1132{
1133 int ret;
1134
dbaa07c4
JK		 1135 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1136
05330448
AL		 1137 ret = kvm_getput_regs(env, 0);
1138 if (ret < 0)
1139 return ret;
1140
f1665b21
SY		 1141 ret = kvm_get_xsave(env);
1142 if (ret < 0)
1143 return ret;
1144
1145 ret = kvm_get_xcrs(env);
05330448
AL		 1146 if (ret < 0)
1147 return ret;
1148
1149 ret = kvm_get_sregs(env);
1150 if (ret < 0)
1151 return ret;
1152
1153 ret = kvm_get_msrs(env);
1154 if (ret < 0)
1155 return ret;
1156
5a2e3c2e
JK		 1157 ret = kvm_get_mp_state(env);
1158 if (ret < 0)
1159 return ret;
1160
a0fb002c
JK		 1161 ret = kvm_get_vcpu_events(env);
1162 if (ret < 0)
1163 return ret;
1164
ff44f1a3
JK		 1165 ret = kvm_get_debugregs(env);
1166 if (ret < 0)
1167 return ret;
1168
05330448
AL		 1169 return 0;
1170}
1171
1172int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1173{
1174 /* Try to inject an interrupt if the guest can accept it */
1175 if (run->ready_for_interrupt_injection &&
1176 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1177 (env->eflags & IF_MASK)) {
1178 int irq;
1179
1180 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1181 irq = cpu_get_pic_interrupt(env);
1182 if (irq >= 0) {
1183 struct kvm_interrupt intr;
1184 intr.irq = irq;
1185 /* FIXME: errors */
8c0d577e 1186 DPRINTF("injected interrupt %d\n", irq);
05330448
AL		 1187 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1188 }
1189 }
1190
1191 /* If we have an interrupt but the guest is not ready to receive an
1192 * interrupt, request an interrupt window exit. This will
1193 * cause a return to userspace as soon as the guest is ready to
1194 * receive interrupts. */
1195 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1196 run->request_interrupt_window = 1;
1197 else
1198 run->request_interrupt_window = 0;
1199
8c0d577e 1200 DPRINTF("setting tpr\n");
4a942cea 1201 run->cr8 = cpu_get_apic_tpr(env->apic_state);
05330448
AL		 1202
1203 return 0;
1204}
1205
1206int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1207{
1208 if (run->if_flag)
1209 env->eflags |= IF_MASK;
1210 else
1211 env->eflags &= ~IF_MASK;
1212
4a942cea
BS		 1213 cpu_set_apic_tpr(env->apic_state, run->cr8);
1214 cpu_set_apic_base(env->apic_state, run->apic_base);
05330448
AL		 1215
1216 return 0;
1217}
1218
0af691d7
MT		 1219int kvm_arch_process_irqchip_events(CPUState *env)
1220{
1221 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1222 kvm_cpu_synchronize_state(env);
1223 do_cpu_init(env);
1224 env->exception_index = EXCP_HALTED;
1225 }
1226
1227 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1228 kvm_cpu_synchronize_state(env);
1229 do_cpu_sipi(env);
1230 }
1231
1232 return env->halted;
1233}
1234
05330448
AL		 1235static int kvm_handle_halt(CPUState *env)
1236{
1237 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1238 (env->eflags & IF_MASK)) &&
1239 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1240 env->halted = 1;
1241 env->exception_index = EXCP_HLT;
1242 return 0;
1243 }
1244
1245 return 1;
1246}
1247
1248int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1249{
1250 int ret = 0;
1251
1252 switch (run->exit_reason) {
1253 case KVM_EXIT_HLT:
8c0d577e 1254 DPRINTF("handle_hlt\n");
05330448
AL		 1255 ret = kvm_handle_halt(env);
1256 break;
1257 }
1258
1259 return ret;
1260}
e22a25c9
AL		 1261
1262#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 1263int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1264{
38972938 1265 static const uint8_t int3 = 0xcc;
64bf3f4e 1266
e22a25c9 1267 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 1268 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 1269 return -EINVAL;
1270 return 0;
1271}
1272
1273int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1274{
1275 uint8_t int3;
1276
1277 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1278 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1279 return -EINVAL;
1280 return 0;
1281}
1282
1283static struct {
1284 target_ulong addr;
1285 int len;
1286 int type;
1287} hw_breakpoint[4];
1288
1289static int nb_hw_breakpoint;
1290
1291static int find_hw_breakpoint(target_ulong addr, int len, int type)
1292{
1293 int n;
1294
1295 for (n = 0; n < nb_hw_breakpoint; n++)
1296 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1297 (hw_breakpoint[n].len == len || len == -1))
1298 return n;
1299 return -1;
1300}
1301
1302int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1303 target_ulong len, int type)
1304{
1305 switch (type) {
1306 case GDB_BREAKPOINT_HW:
1307 len = 1;
1308 break;
1309 case GDB_WATCHPOINT_WRITE:
1310 case GDB_WATCHPOINT_ACCESS:
1311 switch (len) {
1312 case 1:
1313 break;
1314 case 2:
1315 case 4:
1316 case 8:
1317 if (addr & (len - 1))
1318 return -EINVAL;
1319 break;
1320 default:
1321 return -EINVAL;
1322 }
1323 break;
1324 default:
1325 return -ENOSYS;
1326 }
1327
1328 if (nb_hw_breakpoint == 4)
1329 return -ENOBUFS;
1330
1331 if (find_hw_breakpoint(addr, len, type) >= 0)
1332 return -EEXIST;
1333
1334 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1335 hw_breakpoint[nb_hw_breakpoint].len = len;
1336 hw_breakpoint[nb_hw_breakpoint].type = type;
1337 nb_hw_breakpoint++;
1338
1339 return 0;
1340}
1341
1342int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1343 target_ulong len, int type)
1344{
1345 int n;
1346
1347 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1348 if (n < 0)
1349 return -ENOENT;
1350
1351 nb_hw_breakpoint--;
1352 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1353
1354 return 0;
1355}
1356
1357void kvm_arch_remove_all_hw_breakpoints(void)
1358{
1359 nb_hw_breakpoint = 0;
1360}
1361
1362static CPUWatchpoint hw_watchpoint;
1363
1364int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1365{
1366 int handle = 0;
1367 int n;
1368
1369 if (arch_info->exception == 1) {
1370 if (arch_info->dr6 & (1 << 14)) {
1371 if (cpu_single_env->singlestep_enabled)
1372 handle = 1;
1373 } else {
1374 for (n = 0; n < 4; n++)
1375 if (arch_info->dr6 & (1 << n))
1376 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1377 case 0x0:
1378 handle = 1;
1379 break;
1380 case 0x1:
1381 handle = 1;
1382 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1383 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1384 hw_watchpoint.flags = BP_MEM_WRITE;
1385 break;
1386 case 0x3:
1387 handle = 1;
1388 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1389 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1390 hw_watchpoint.flags = BP_MEM_ACCESS;
1391 break;
1392 }
1393 }
1394 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1395 handle = 1;
1396
b0b1d690
JK		 1397 if (!handle) {
1398 cpu_synchronize_state(cpu_single_env);
1399 assert(cpu_single_env->exception_injected == -1);
1400
1401 cpu_single_env->exception_injected = arch_info->exception;
1402 cpu_single_env->has_error_code = 0;
1403 }
e22a25c9
AL		 1404
1405 return handle;
1406}
1407
1408void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1409{
1410 const uint8_t type_code[] = {
1411 [GDB_BREAKPOINT_HW] = 0x0,
1412 [GDB_WATCHPOINT_WRITE] = 0x1,
1413 [GDB_WATCHPOINT_ACCESS] = 0x3
1414 };
1415 const uint8_t len_code[] = {
1416 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1417 };
1418 int n;
1419
1420 if (kvm_sw_breakpoints_active(env))
1421 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1422
1423 if (nb_hw_breakpoint > 0) {
1424 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1425 dbg->arch.debugreg[7] = 0x0600;
1426 for (n = 0; n < nb_hw_breakpoint; n++) {
1427 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1428 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1429 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1430 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1431 }
1432 }
f1665b21
SY		 1433 /* Legal xcr0 for loading */
1434 env->xcr0 = 1;
e22a25c9
AL		 1435}
1436#endif /* KVM_CAP_SET_GUEST_DEBUG */
4513d923
GN		 1437
1438bool kvm_arch_stop_on_emulation_error(CPUState *env)
1439{
1440 return !(env->cr[0] & CR0_PE_MASK) ||
1441 ((env->segs[R_CS].selector & 3) != 3);
1442}
1443
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