[qemu.git] / hw / mips_jazz.c

/*
 * QEMU MIPS Jazz support
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "mips.h"
#include "mips_cpudevs.h"
#include "pc.h"
#include "isa.h"
#include "fdc.h"
#include "sysemu.h"
#include "arch_init.h"
#include "boards.h"
#include "net.h"
#include "esp.h"
#include "mips-bios.h"
#include "loader.h"
#include "mc146818rtc.h"
#include "blockdev.h"
#include "sysbus.h"
#include "exec-memory.h"

enum jazz_model_e
{
    JAZZ_MAGNUM,
    JAZZ_PICA61,
};

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);
}

static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
    return cpu_inw(0x71);
}

static void rtc_write(void *opaque, target_phys_addr_t addr,
                      uint64_t val, unsigned size)
{
    cpu_outw(0x71, val & 0xff);
}

static const MemoryRegionOps rtc_ops = {
    .read = rtc_read,
    .write = rtc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
                               unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
    return 0xff;
}

static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
}

static const MemoryRegionOps dma_dummy_ops = {
    .read = dma_dummy_read,
    .write = dma_dummy_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

static void cpu_request_exit(void *opaque, int irq, int level)
{
    CPUState *env = cpu_single_env;

    if (env && level) {
        cpu_exit(env);
    }
}

static void mips_jazz_init(MemoryRegion *address_space,
                           MemoryRegion *address_space_io,
                           ram_addr_t ram_size,
                           const char *cpu_model,
                           enum jazz_model_e jazz_model)
{
    char *filename;
    int bios_size, n;
    CPUState *env;
    qemu_irq *rc4030, *i8259;
    rc4030_dma *dmas;
    void* rc4030_opaque;
    MemoryRegion *rtc = g_new(MemoryRegion, 1);
    MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
    NICInfo *nd;
    DeviceState *dev;
    SysBusDevice *sysbus;
    ISADevice *pit;
    DriveInfo *fds[MAX_FD];
    qemu_irq esp_reset, dma_enable;
    qemu_irq *cpu_exit_irq;
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    MemoryRegion *bios2 = g_new(MemoryRegion, 1);

    /* init CPUs */
    if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
        cpu_model = "R4000";
#else
        /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
        cpu_model = "24Kf";
#endif
    }
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    qemu_register_reset(main_cpu_reset, env);

    /* allocate RAM */
    memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
    memory_region_add_subregion(address_space, 0, ram);

    memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
    memory_region_set_readonly(bios, true);
    memory_region_init_alias(bios2, "mips_jazz.bios", bios,
                             0, MAGNUM_BIOS_SIZE);
    memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
    memory_region_add_subregion(address_space, 0xfff00000LL, bios2);

    /* load the BIOS image. */
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    if (filename) {
        bios_size = load_image_targphys(filename, 0xfff00000LL,
                                        MAGNUM_BIOS_SIZE);
        g_free(filename);
    } else {
        bios_size = -1;
    }
    if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
        fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
                bios_name);
        exit(1);
    }

    /* Init CPU internal devices */
    cpu_mips_irq_init_cpu(env);
    cpu_mips_clock_init(env);

    /* Chipset */
    rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
    memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
    memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);

    /* ISA devices */
    i8259 = i8259_init(env->irq[4]);
    isa_bus_new(NULL, address_space_io);
    isa_bus_irqs(i8259);
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
    DMA_init(0, cpu_exit_irq);
    pit = pit_init(0x40, 0);
    pcspk_init(pit);

    /* ISA IO space at 0x90000000 */
    isa_mmio_init(0x90000000, 0x01000000);
    isa_mem_base = 0x11000000;

    /* Video card */
    switch (jazz_model) {
    case JAZZ_MAGNUM:
        dev = qdev_create(NULL, "sysbus-g364");
        qdev_init_nofail(dev);
        sysbus = sysbus_from_qdev(dev);
        sysbus_mmio_map(sysbus, 0, 0x60080000);
        sysbus_mmio_map(sysbus, 1, 0x40000000);
        sysbus_connect_irq(sysbus, 0, rc4030[3]);
        {
            /* Simple ROM, so user doesn't have to provide one */
            MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
            memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
            memory_region_set_readonly(rom_mr, true);
            uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
            memory_region_add_subregion(address_space, 0x60000000, rom_mr);
            rom[0] = 0x10; /* Mips G364 */
        }
        break;
    case JAZZ_PICA61:
        isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
        break;
    default:
        break;
    }

    /* Network controller */
    for (n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];
        if (!nd->model)
            nd->model = g_strdup("dp83932");
        if (strcmp(nd->model, "dp83932") == 0) {
            dp83932_init(nd, 0x80001000, 2, rc4030[4],
                         rc4030_opaque, rc4030_dma_memory_rw);
            break;
        } else if (strcmp(nd->model, "?") == 0) {
            fprintf(stderr, "qemu: Supported NICs: dp83932\n");
            exit(1);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
            exit(1);
        }
    }

    /* SCSI adapter */
    esp_init(0x80002000, 0,
             rc4030_dma_read, rc4030_dma_write, dmas[0],
             rc4030[5], &esp_reset, &dma_enable);

    /* Floppy */
    if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
        fprintf(stderr, "qemu: too many floppy drives\n");
        exit(1);
    }
    for (n = 0; n < MAX_FD; n++) {
        fds[n] = drive_get(IF_FLOPPY, 0, n);
    }
    fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);

    /* Real time clock */
    rtc_init(1980, NULL);
    memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
    memory_region_add_subregion(address_space, 0x80004000, rtc);

    /* Keyboard (i8042) */
    i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);

    /* Serial ports */
    if (serial_hds[0]) {
#ifdef TARGET_WORDS_BIGENDIAN
        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
#else
        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
#endif
    }
    if (serial_hds[1]) {
#ifdef TARGET_WORDS_BIGENDIAN
        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
#else
        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
#endif
    }

    /* Parallel port */
    if (parallel_hds[0])
        parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);

    /* Sound card */
    /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
    audio_init(i8259, NULL);

    /* NVRAM */
    dev = qdev_create(NULL, "ds1225y");
    qdev_init_nofail(dev);
    sysbus = sysbus_from_qdev(dev);
    sysbus_mmio_map(sysbus, 0, 0x80009000);

    /* LED indicator */
    jazz_led_init(0x8000f000);
}

static
void mips_magnum_init (ram_addr_t ram_size,
                       const char *boot_device,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
        mips_jazz_init(get_system_memory(), get_system_io(),
                       ram_size, cpu_model, JAZZ_MAGNUM);
}

static
void mips_pica61_init (ram_addr_t ram_size,
                       const char *boot_device,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
    mips_jazz_init(get_system_memory(), get_system_io(),
                   ram_size, cpu_model, JAZZ_PICA61);
}

static QEMUMachine mips_magnum_machine = {
    .name = "magnum",
    .desc = "MIPS Magnum",
    .init = mips_magnum_init,
    .use_scsi = 1,
};

static QEMUMachine mips_pica61_machine = {
    .name = "pica61",
    .desc = "Acer Pica 61",
    .init = mips_pica61_init,
    .use_scsi = 1,
};

static void mips_jazz_machine_init(void)
{
    qemu_register_machine(&mips_magnum_machine);
    qemu_register_machine(&mips_pica61_machine);
}

machine_init(mips_jazz_machine_init);
Commit	Line	Data
4ce7ff6e AJ	1	/*
	2	* QEMU MIPS Jazz support
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "hw.h"
	26	#include "mips.h"
b970ea8f	27	#include "mips_cpudevs.h"
4ce7ff6e AJ	28	#include "pc.h"
	29	#include "isa.h"
	30	#include "fdc.h"
	31	#include "sysemu.h"
0dfa5ef9	32	#include "arch_init.h"
4ce7ff6e AJ	33	#include "boards.h"
4ce7ff6e AJ	34	#include "net.h"
1cd3af54	35	#include "esp.h"
bba831e8	36	#include "mips-bios.h"
ca20cf32	37	#include "loader.h"
1d914fa0	38	#include "mc146818rtc.h"
2446333c	39	#include "blockdev.h"
cd3e2409	40	#include "sysbus.h"
be20f9e9	41	#include "exec-memory.h"
4ce7ff6e	42
4ce7ff6e AJ	43	enum jazz_model_e
	44	{
	45	JAZZ_MAGNUM,
c171148c	46	JAZZ_PICA61,
4ce7ff6e AJ	47	};
	48
	49	static void main_cpu_reset(void *opaque)
	50	{
	51	CPUState *env = opaque;
	52	cpu_reset(env);
	53	}
	54
60581b37	55	static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
4ce7ff6e	56	{
afcea8cb	57	return cpu_inw(0x71);
4ce7ff6e AJ	58	}
4ce7ff6e AJ	59
60581b37 AK	60	static void rtc_write(void *opaque, target_phys_addr_t addr,
60581b37 AK	61	uint64_t val, unsigned size)
4ce7ff6e	62	{
afcea8cb	63	cpu_outw(0x71, val & 0xff);
4ce7ff6e AJ	64	}
4ce7ff6e AJ	65
60581b37 AK	66	static const MemoryRegionOps rtc_ops = {
	67	.read = rtc_read,
	68	.write = rtc_write,
	69	.endianness = DEVICE_NATIVE_ENDIAN,
4ce7ff6e AJ	70	};
4ce7ff6e AJ	71
60581b37 AK	72	static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
60581b37 AK	73	unsigned size)
c6945b15 AJ	74	{
	75	/* Nothing to do. That is only to ensure that
	76	* the current DMA acknowledge cycle is completed. */
60581b37	77	return 0xff;
c6945b15 AJ	78	}
c6945b15 AJ	79
60581b37 AK	80	static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
	81	uint64_t val, unsigned size)
	82	{
	83	/* Nothing to do. That is only to ensure that
	84	* the current DMA acknowledge cycle is completed. */
	85	}
c6945b15	86
60581b37 AK	87	static const MemoryRegionOps dma_dummy_ops = {
	88	.read = dma_dummy_read,
	89	.write = dma_dummy_write,
	90	.endianness = DEVICE_NATIVE_ENDIAN,
c6945b15 AJ	91	};
c6945b15 AJ	92
4ce7ff6e AJ	93	#define MAGNUM_BIOS_SIZE_MAX 0x7e000
	94	#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
	95
4556bd8b BS	96	static void cpu_request_exit(void *opaque, int irq, int level)
	97	{
	98	CPUState *env = cpu_single_env;
	99
	100	if (env && level) {
	101	cpu_exit(env);
	102	}
	103	}
	104
c2d0d012 RH	105	static void mips_jazz_init(MemoryRegion *address_space,
	106	MemoryRegion *address_space_io,
	107	ram_addr_t ram_size,
	108	const char *cpu_model,
	109	enum jazz_model_e jazz_model)
4ce7ff6e	110	{
5cea8590	111	char *filename;
4ce7ff6e AJ	112	int bios_size, n;
	113	CPUState *env;
	114	qemu_irq rc4030, i8259;
c6945b15	115	rc4030_dma *dmas;
68238a9e	116	void* rc4030_opaque;
60581b37 AK	117	MemoryRegion *rtc = g_new(MemoryRegion, 1);
60581b37 AK	118	MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
a65f56ee	119	NICInfo *nd;
cd3e2409 HP	120	DeviceState *dev;
cd3e2409 HP	121	SysBusDevice *sysbus;
64d7e9a4	122	ISADevice *pit;
fd8014e1	123	DriveInfo *fds[MAX_FD];
73d74342	124	qemu_irq esp_reset, dma_enable;
4556bd8b	125	qemu_irq *cpu_exit_irq;
60581b37 AK	126	MemoryRegion *ram = g_new(MemoryRegion, 1);
	127	MemoryRegion *bios = g_new(MemoryRegion, 1);
	128	MemoryRegion *bios2 = g_new(MemoryRegion, 1);
4ce7ff6e AJ	129
	130	/* init CPUs */
	131	if (cpu_model == NULL) {
	132	#ifdef TARGET_MIPS64
	133	cpu_model = "R4000";
	134	#else
	135	/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
	136	cpu_model = "24Kf";
	137	#endif
	138	}
	139	env = cpu_init(cpu_model);
	140	if (!env) {
	141	fprintf(stderr, "Unable to find CPU definition\n");
	142	exit(1);
	143	}
a08d4367	144	qemu_register_reset(main_cpu_reset, env);
4ce7ff6e AJ	145
4ce7ff6e AJ	146	/* allocate RAM */
60581b37 AK	147	memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
60581b37 AK	148	memory_region_add_subregion(address_space, 0, ram);
dcac9679	149
60581b37 AK	150	memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
	151	memory_region_set_readonly(bios, true);
	152	memory_region_init_alias(bios2, "mips_jazz.bios", bios,
	153	0, MAGNUM_BIOS_SIZE);
	154	memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
	155	memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
4ce7ff6e AJ	156
4ce7ff6e AJ	157	/* load the BIOS image. */
c6945b15 AJ	158	if (bios_name == NULL)
c6945b15 AJ	159	bios_name = BIOS_FILENAME;
5cea8590 PB	160	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	161	if (filename) {
	162	bios_size = load_image_targphys(filename, 0xfff00000LL,
	163	MAGNUM_BIOS_SIZE);
7267c094	164	g_free(filename);
5cea8590 PB	165	} else {
	166	bios_size = -1;
	167	}
4ce7ff6e AJ	168	if (bios_size < 0 \|\| bios_size > MAGNUM_BIOS_SIZE) {
4ce7ff6e AJ	169	fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
5cea8590	170	bios_name);
4ce7ff6e AJ	171	exit(1);
	172	}
	173
4ce7ff6e AJ	174	/* Init CPU internal devices */
	175	cpu_mips_irq_init_cpu(env);
	176	cpu_mips_clock_init(env);
	177
	178	/* Chipset */
68238a9e	179	rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
60581b37 AK	180	memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
60581b37 AK	181	memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
4ce7ff6e AJ	182
	183	/* ISA devices */
	184	i8259 = i8259_init(env->irq[4]);
c2d0d012	185	isa_bus_new(NULL, address_space_io);
5041fccd	186	isa_bus_irqs(i8259);
4556bd8b BS	187	cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
4556bd8b BS	188	DMA_init(0, cpu_exit_irq);
64d7e9a4	189	pit = pit_init(0x40, 0);
4ce7ff6e AJ	190	pcspk_init(pit);
	191
	192	/* ISA IO space at 0x90000000 */
968d683c	193	isa_mmio_init(0x90000000, 0x01000000);
4ce7ff6e AJ	194	isa_mem_base = 0x11000000;
	195
	196	/* Video card */
	197	switch (jazz_model) {
	198	case JAZZ_MAGNUM:
97a3f6ff HP	199	dev = qdev_create(NULL, "sysbus-g364");
	200	qdev_init_nofail(dev);
	201	sysbus = sysbus_from_qdev(dev);
	202	sysbus_mmio_map(sysbus, 0, 0x60080000);
	203	sysbus_mmio_map(sysbus, 1, 0x40000000);
	204	sysbus_connect_irq(sysbus, 0, rc4030[3]);
	205	{
	206	/* Simple ROM, so user doesn't have to provide one */
60581b37 AK	207	MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
	208	memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
	209	memory_region_set_readonly(rom_mr, true);
	210	uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
	211	memory_region_add_subregion(address_space, 0x60000000, rom_mr);
97a3f6ff HP	212	rom[0] = 0x10; /* Mips G364 */
97a3f6ff HP	213	}
4ce7ff6e	214	break;
c171148c	215	case JAZZ_PICA61:
be20f9e9	216	isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
c171148c	217	break;
4ce7ff6e AJ	218	default:
	219	break;
	220	}
	221
	222	/* Network controller */
a65f56ee AJ	223	for (n = 0; n < nb_nics; n++) {
	224	nd = &nd_table[n];
	225	if (!nd->model)
7267c094	226	nd->model = g_strdup("dp83932");
a65f56ee AJ	227	if (strcmp(nd->model, "dp83932") == 0) {
	228	dp83932_init(nd, 0x80001000, 2, rc4030[4],
	229	rc4030_opaque, rc4030_dma_memory_rw);
	230	break;
	231	} else if (strcmp(nd->model, "?") == 0) {
	232	fprintf(stderr, "qemu: Supported NICs: dp83932\n");
	233	exit(1);
	234	} else {
	235	fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
	236	exit(1);
	237	}
	238	}
4ce7ff6e AJ	239
4ce7ff6e AJ	240	/* SCSI adapter */
cfb9de9c PB	241	esp_init(0x80002000, 0,
cfb9de9c PB	242	rc4030_dma_read, rc4030_dma_write, dmas[0],
73d74342	243	rc4030[5], &esp_reset, &dma_enable);
4ce7ff6e AJ	244
	245	/* Floppy */
	246	if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
	247	fprintf(stderr, "qemu: too many floppy drives\n");
	248	exit(1);
	249	}
	250	for (n = 0; n < MAX_FD; n++) {
fd8014e1	251	fds[n] = drive_get(IF_FLOPPY, 0, n);
4ce7ff6e	252	}
2091ba23	253	fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
4ce7ff6e AJ	254
4ce7ff6e AJ	255	/* Real time clock */
7d932dfd	256	rtc_init(1980, NULL);
60581b37 AK	257	memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
60581b37 AK	258	memory_region_add_subregion(address_space, 0x80004000, rtc);
4ce7ff6e AJ	259
4ce7ff6e AJ	260	/* Keyboard (i8042) */
4efbe58f	261	i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
4ce7ff6e AJ	262
4ce7ff6e AJ	263	/* Serial ports */
2d48377a BS	264	if (serial_hds[0]) {
	265	#ifdef TARGET_WORDS_BIGENDIAN
	266	serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
	267	#else
	268	serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
	269	#endif
	270	}
	271	if (serial_hds[1]) {
	272	#ifdef TARGET_WORDS_BIGENDIAN
	273	serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
	274	#else
	275	serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
	276	#endif
	277	}
4ce7ff6e AJ	278
	279	/* Parallel port */
	280	if (parallel_hds[0])
	281	parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
	282
	283	/* Sound card */
	284	/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
0dfa5ef9	285	audio_init(i8259, NULL);
4ce7ff6e	286
cd3e2409 HP	287	/* NVRAM */
	288	dev = qdev_create(NULL, "ds1225y");
	289	qdev_init_nofail(dev);
	290	sysbus = sysbus_from_qdev(dev);
	291	sysbus_mmio_map(sysbus, 0, 0x80009000);
4ce7ff6e AJ	292
4ce7ff6e AJ	293	/* LED indicator */
3023f332	294	jazz_led_init(0x8000f000);
4ce7ff6e AJ	295	}
	296
	297	static
c227f099	298	void mips_magnum_init (ram_addr_t ram_size,
3023f332	299	const char *boot_device,
4ce7ff6e AJ	300	const char kernel_filename, const char kernel_cmdline,
	301	const char initrd_filename, const char cpu_model)
	302	{
c2d0d012 RH	303	mips_jazz_init(get_system_memory(), get_system_io(),
c2d0d012 RH	304	ram_size, cpu_model, JAZZ_MAGNUM);
4ce7ff6e AJ	305	}
4ce7ff6e AJ	306
c171148c	307	static
c227f099	308	void mips_pica61_init (ram_addr_t ram_size,
3023f332	309	const char *boot_device,
c171148c AJ	310	const char kernel_filename, const char kernel_cmdline,
	311	const char initrd_filename, const char cpu_model)
	312	{
c2d0d012 RH	313	mips_jazz_init(get_system_memory(), get_system_io(),
c2d0d012 RH	314	ram_size, cpu_model, JAZZ_PICA61);
c171148c AJ	315	}
c171148c AJ	316
f80f9ec9	317	static QEMUMachine mips_magnum_machine = {
eec2743e TS	318	.name = "magnum",
	319	.desc = "MIPS Magnum",
	320	.init = mips_magnum_init,
c6945b15	321	.use_scsi = 1,
4ce7ff6e	322	};
c171148c	323
f80f9ec9	324	static QEMUMachine mips_pica61_machine = {
eec2743e TS	325	.name = "pica61",
	326	.desc = "Acer Pica 61",
	327	.init = mips_pica61_init,
c6945b15	328	.use_scsi = 1,
c171148c	329	};
f80f9ec9 AL	330
	331	static void mips_jazz_machine_init(void)
	332	{
	333	qemu_register_machine(&mips_magnum_machine);
	334	qemu_register_machine(&mips_pica61_machine);
	335	}
	336
	337	machine_init(mips_jazz_machine_init);