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5fafdf24 | 1 | /* |
423f0742 PB |
2 | * General purpose implementation of a simple periodic countdown timer. |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * | |
6 | * This code is licenced under the GNU LGPL. | |
7 | */ | |
87ecb68b PB |
8 | #include "hw.h" |
9 | #include "qemu-timer.h" | |
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10 | |
11 | ||
12 | struct ptimer_state | |
13 | { | |
14 | int enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ | |
8d05ea8a BS |
15 | uint64_t limit; |
16 | uint64_t delta; | |
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17 | uint32_t period_frac; |
18 | int64_t period; | |
19 | int64_t last_event; | |
20 | int64_t next_event; | |
21 | QEMUBH *bh; | |
22 | QEMUTimer *timer; | |
23 | }; | |
24 | ||
25 | /* Use a bottom-half routine to avoid reentrancy issues. */ | |
26 | static void ptimer_trigger(ptimer_state *s) | |
27 | { | |
28 | if (s->bh) { | |
29 | qemu_bh_schedule(s->bh); | |
30 | } | |
31 | } | |
32 | ||
33 | static void ptimer_reload(ptimer_state *s) | |
34 | { | |
35 | if (s->delta == 0) { | |
36 | ptimer_trigger(s); | |
37 | s->delta = s->limit; | |
38 | } | |
39 | if (s->delta == 0 || s->period == 0) { | |
40 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
41 | s->enabled = 0; | |
42 | return; | |
43 | } | |
44 | ||
45 | s->last_event = s->next_event; | |
46 | s->next_event = s->last_event + s->delta * s->period; | |
47 | if (s->period_frac) { | |
48 | s->next_event += ((int64_t)s->period_frac * s->delta) >> 32; | |
49 | } | |
50 | qemu_mod_timer(s->timer, s->next_event); | |
51 | } | |
52 | ||
53 | static void ptimer_tick(void *opaque) | |
54 | { | |
55 | ptimer_state *s = (ptimer_state *)opaque; | |
56 | ptimer_trigger(s); | |
57 | s->delta = 0; | |
58 | if (s->enabled == 2) { | |
59 | s->enabled = 0; | |
60 | } else { | |
61 | ptimer_reload(s); | |
62 | } | |
63 | } | |
64 | ||
8d05ea8a | 65 | uint64_t ptimer_get_count(ptimer_state *s) |
423f0742 PB |
66 | { |
67 | int64_t now; | |
8d05ea8a | 68 | uint64_t counter; |
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69 | |
70 | if (s->enabled) { | |
71 | now = qemu_get_clock(vm_clock); | |
72 | /* Figure out the current counter value. */ | |
73 | if (now - s->next_event > 0 | |
74 | || s->period == 0) { | |
75 | /* Prevent timer underflowing if it should already have | |
76 | triggered. */ | |
77 | counter = 0; | |
78 | } else { | |
8d05ea8a BS |
79 | uint64_t rem; |
80 | uint64_t div; | |
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81 | |
82 | rem = s->next_event - now; | |
83 | div = s->period; | |
84 | counter = rem / div; | |
85 | } | |
86 | } else { | |
87 | counter = s->delta; | |
88 | } | |
89 | return counter; | |
90 | } | |
91 | ||
8d05ea8a | 92 | void ptimer_set_count(ptimer_state *s, uint64_t count) |
423f0742 PB |
93 | { |
94 | s->delta = count; | |
95 | if (s->enabled) { | |
96 | s->next_event = qemu_get_clock(vm_clock); | |
97 | ptimer_reload(s); | |
98 | } | |
99 | } | |
100 | ||
101 | void ptimer_run(ptimer_state *s, int oneshot) | |
102 | { | |
98fc5614 PB |
103 | if (s->enabled) { |
104 | return; | |
105 | } | |
423f0742 PB |
106 | if (s->period == 0) { |
107 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
108 | return; | |
109 | } | |
110 | s->enabled = oneshot ? 2 : 1; | |
111 | s->next_event = qemu_get_clock(vm_clock); | |
112 | ptimer_reload(s); | |
113 | } | |
114 | ||
8d05ea8a | 115 | /* Pause a timer. Note that this may cause it to "lose" time, even if it |
423f0742 PB |
116 | is immediately restarted. */ |
117 | void ptimer_stop(ptimer_state *s) | |
118 | { | |
119 | if (!s->enabled) | |
120 | return; | |
121 | ||
122 | s->delta = ptimer_get_count(s); | |
123 | qemu_del_timer(s->timer); | |
124 | s->enabled = 0; | |
125 | } | |
126 | ||
127 | /* Set counter increment interval in nanoseconds. */ | |
128 | void ptimer_set_period(ptimer_state *s, int64_t period) | |
129 | { | |
423f0742 PB |
130 | s->period = period; |
131 | s->period_frac = 0; | |
8d05ea8a BS |
132 | if (s->enabled) { |
133 | s->next_event = qemu_get_clock(vm_clock); | |
134 | ptimer_reload(s); | |
135 | } | |
423f0742 PB |
136 | } |
137 | ||
138 | /* Set counter frequency in Hz. */ | |
139 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | |
140 | { | |
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141 | s->period = 1000000000ll / freq; |
142 | s->period_frac = (1000000000ll << 32) / freq; | |
8d05ea8a BS |
143 | if (s->enabled) { |
144 | s->next_event = qemu_get_clock(vm_clock); | |
145 | ptimer_reload(s); | |
146 | } | |
423f0742 PB |
147 | } |
148 | ||
149 | /* Set the initial countdown value. If reload is nonzero then also set | |
150 | count = limit. */ | |
8d05ea8a | 151 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) |
423f0742 | 152 | { |
423f0742 PB |
153 | s->limit = limit; |
154 | if (reload) | |
155 | s->delta = limit; | |
62ea5b0b | 156 | if (s->enabled && reload) { |
8d05ea8a BS |
157 | s->next_event = qemu_get_clock(vm_clock); |
158 | ptimer_reload(s); | |
159 | } | |
160 | } | |
161 | ||
162 | void qemu_put_ptimer(QEMUFile *f, ptimer_state *s) | |
163 | { | |
164 | qemu_put_byte(f, s->enabled); | |
165 | qemu_put_be64s(f, &s->limit); | |
166 | qemu_put_be64s(f, &s->delta); | |
167 | qemu_put_be32s(f, &s->period_frac); | |
2ca83a8d BS |
168 | qemu_put_be64s(f, &s->period); |
169 | qemu_put_be64s(f, &s->last_event); | |
170 | qemu_put_be64s(f, &s->next_event); | |
8d05ea8a BS |
171 | qemu_put_timer(f, s->timer); |
172 | } | |
173 | ||
174 | void qemu_get_ptimer(QEMUFile *f, ptimer_state *s) | |
175 | { | |
176 | s->enabled = qemu_get_byte(f); | |
177 | qemu_get_be64s(f, &s->limit); | |
178 | qemu_get_be64s(f, &s->delta); | |
179 | qemu_get_be32s(f, &s->period_frac); | |
2ca83a8d BS |
180 | qemu_get_be64s(f, &s->period); |
181 | qemu_get_be64s(f, &s->last_event); | |
182 | qemu_get_be64s(f, &s->next_event); | |
8d05ea8a | 183 | qemu_get_timer(f, s->timer); |
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184 | } |
185 | ||
186 | ptimer_state *ptimer_init(QEMUBH *bh) | |
187 | { | |
188 | ptimer_state *s; | |
189 | ||
190 | s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state)); | |
191 | s->bh = bh; | |
192 | s->timer = qemu_new_timer(vm_clock, ptimer_tick, s); | |
193 | return s; | |
194 | } | |
195 |