]> Git Repo - qemu.git/blame - hw/bt.h
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
virtio-blk-s390: switch to the new API.
[qemu.git] / hw / bt.h
CommitLineData
1ae26a18
AZ		 1/*
2 * QEMU Bluetooth HCI helpers.
3 *
4 * Copyright (C) 2007 OpenMoko, Inc.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
4e38eb54
AZ		 7 * Useful definitions taken from BlueZ project's headers.
8 * Copyright (C) 2000-2001 Qualcomm Incorporated
9 * Copyright (C) 2002-2003 Maxim Krasnyansky <[email protected]>
10 * Copyright (C) 2002-2006 Marcel Holtmann <[email protected]>
11 *
1ae26a18
AZ		 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
8167ee88 23 * along with this program; if not, see <http://www.gnu.org/licenses/>.
1ae26a18
AZ		 24 */
25
cb9c377f
PB		 26#ifndef HW_BT_H
27#define HW_BT_H 1
28
5202ef94
IM		 29#include "hw/irq.h"
30
1ae26a18
AZ		 31/* BD Address */
32typedef struct {
33 uint8_t b[6];
541dc0d4 34} QEMU_PACKED bdaddr_t;
1ae26a18 35
c227f099
AL		 36#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}})
37#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
38#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}})
1ae26a18
AZ		 39
40/* Copy, swap, convert BD Address */
c227f099 41static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2)
1ae26a18 42{
c227f099 43 return memcmp(ba1, ba2, sizeof(bdaddr_t));
1ae26a18 44}
c227f099 45static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src)
1ae26a18 46{
c227f099 47 memcpy(dst, src, sizeof(bdaddr_t));
1ae26a18
AZ		 48}
49
50#define BAINIT(orig) { .b = { \
51 (orig)->b[0], (orig)->b[1], (orig)->b[2], \
52 (orig)->b[3], (orig)->b[4], (orig)->b[5], \
53}, }
54
55/* The twisted structures of a bluetooth environment */
56struct bt_device_s;
57struct bt_scatternet_s;
58struct bt_piconet_s;
59struct bt_link_s;
60
61struct bt_scatternet_s {
62 struct bt_device_s *slave;
63};
64
65struct bt_link_s {
66 struct bt_device_s *slave, *host;
67 uint16_t handle; /* Master (host) side handle */
68 uint16_t acl_interval;
69 enum {
70 acl_active,
71 acl_hold,
72 acl_sniff,
73 acl_parked,
74 } acl_mode;
75};
76
77struct bt_device_s {
78 int lt_addr;
c227f099 79 bdaddr_t bd_addr;
1ae26a18
AZ		 80 int mtu;
81 int setup;
82 struct bt_scatternet_s *net;
83
84 uint8_t key[16];
85 int key_present;
86 uint8_t class[3];
87
88 uint8_t reject_reason;
89
90 uint64_t lmp_caps;
91 const char *lmp_name;
92 void (*lmp_connection_request)(struct bt_link_s *link);
93 void (*lmp_connection_complete)(struct bt_link_s *link);
94 void (*lmp_disconnect_master)(struct bt_link_s *link);
95 void (*lmp_disconnect_slave)(struct bt_link_s *link);
96 void (*lmp_acl_data)(struct bt_link_s *link, const uint8_t *data,
97 int start, int len);
98 void (*lmp_acl_resp)(struct bt_link_s *link, const uint8_t *data,
99 int start, int len);
100 void (*lmp_mode_change)(struct bt_link_s *link);
101
102 void (*handle_destroy)(struct bt_device_s *device);
103 struct bt_device_s *next; /* Next in the piconet/scatternet */
104
105 int inquiry_scan;
106 int page_scan;
107
108 uint16_t clkoff; /* Note: Always little-endian */
109};
110
111/* bt.c */
112void bt_device_init(struct bt_device_s *dev, struct bt_scatternet_s *net);
113void bt_device_done(struct bt_device_s *dev);
58a26b47 114
4e38eb54
AZ		 115/* bt-hci.c */
116struct HCIInfo *bt_new_hci(struct bt_scatternet_s *net);
117
ab2b6f50
AZ		 118/* bt-vhci.c */
119void bt_vhci_init(struct HCIInfo *info);
120
58a26b47
AZ		 121/* bt-hci-csr.c */
122enum {
123 csrhci_pin_reset,
124 csrhci_pin_wakeup,
125 __csrhci_pins,
126};
127qemu_irq *csrhci_pins_get(CharDriverState *chr);
128CharDriverState *uart_hci_init(qemu_irq wakeup);
129
4d2d181c
AZ		 130/* bt-l2cap.c */
131struct bt_l2cap_device_s;
132struct bt_l2cap_conn_params_s;
133struct bt_l2cap_psm_s;
134void bt_l2cap_device_init(struct bt_l2cap_device_s *dev,
135 struct bt_scatternet_s *net);
136void bt_l2cap_device_done(struct bt_l2cap_device_s *dev);
137void bt_l2cap_psm_register(struct bt_l2cap_device_s *dev, int psm,
138 int min_mtu, int (*new_channel)(struct bt_l2cap_device_s *dev,
139 struct bt_l2cap_conn_params_s *params));
140
141struct bt_l2cap_device_s {
142 struct bt_device_s device;
143 struct bt_l2cap_psm_s *first_psm;
144};
145
146struct bt_l2cap_conn_params_s {
147 /* Input */
148 uint8_t *(*sdu_out)(struct bt_l2cap_conn_params_s *chan, int len);
149 void (*sdu_submit)(struct bt_l2cap_conn_params_s *chan);
150 int remote_mtu;
151 /* Output */
152 void *opaque;
153 void (*sdu_in)(void *opaque, const uint8_t *data, int len);
154 void (*close)(void *opaque);
155};
156
157enum bt_l2cap_psm_predef {
158 BT_PSM_SDP = 0x0001,
159 BT_PSM_RFCOMM = 0x0003,
160 BT_PSM_TELEPHONY = 0x0005,
161 BT_PSM_TCS = 0x0007,
162 BT_PSM_BNEP = 0x000f,
163 BT_PSM_HID_CTRL = 0x0011,
164 BT_PSM_HID_INTR = 0x0013,
165 BT_PSM_UPNP = 0x0015,
166 BT_PSM_AVCTP = 0x0017,
167 BT_PSM_AVDTP = 0x0019,
168};
169
170/* bt-sdp.c */
171void bt_l2cap_sdp_init(struct bt_l2cap_device_s *dev);
172
ab2b6f50
AZ		 173/* bt-hid.c */
174struct bt_device_s *bt_mouse_init(struct bt_scatternet_s *net);
175struct bt_device_s *bt_tablet_init(struct bt_scatternet_s *net);
176struct bt_device_s *bt_keyboard_init(struct bt_scatternet_s *net);
177
58a26b47
AZ		 178/* Link Management Protocol layer defines */
179
180#define LLID_ACLU_CONT 0x1
181#define LLID_ACLU_START 0x2
182#define LLID_ACLC 0x3
183
184enum lmp_pdu_type {
185 LMP_NAME_REQ = 0x0001,
186 LMP_NAME_RES = 0x0002,
187 LMP_ACCEPTED = 0x0003,
188 LMP_NOT_ACCEPTED = 0x0004,
189 LMP_CLKOFFSET_REQ = 0x0005,
190 LMP_CLKOFFSET_RES = 0x0006,
191 LMP_DETACH = 0x0007,
192 LMP_IN_RAND = 0x0008,
193 LMP_COMB_KEY = 0x0009,
194 LMP_UNIT_KEY = 0x000a,
195 LMP_AU_RAND = 0x000b,
196 LMP_SRES = 0x000c,
197 LMP_TEMP_RAND = 0x000d,
198 LMP_TEMP_KEY = 0x000e,
199 LMP_CRYPT_MODE_REQ = 0x000f,
200 LMP_CRYPT_KEY_SIZE_REQ = 0x0010,
201 LMP_START_ENCRYPT_REQ = 0x0011,
202 LMP_STOP_ENCRYPT_REQ = 0x0012,
203 LMP_SWITCH_REQ = 0x0013,
204 LMP_HOLD = 0x0014,
205 LMP_HOLD_REQ = 0x0015,
206 LMP_SNIFF_REQ = 0x0017,
207 LMP_UNSNIFF_REQ = 0x0018,
208 LMP_LMP_PARK_REQ = 0x0019,
209 LMP_SET_BCAST_SCAN_WND = 0x001b,
210 LMP_MODIFY_BEACON = 0x001c,
211 LMP_UNPARK_BD_ADDR_REQ = 0x001d,
212 LMP_UNPARK_PM_ADDR_REQ = 0x001e,
213 LMP_INCR_POWER_REQ = 0x001f,
214 LMP_DECR_POWER_REQ = 0x0020,
215 LMP_MAX_POWER = 0x0021,
216 LMP_MIN_POWER = 0x0022,
217 LMP_AUTO_RATE = 0x0023,
218 LMP_PREFERRED_RATE = 0x0024,
219 LMP_VERSION_REQ = 0x0025,
220 LMP_VERSION_RES = 0x0026,
221 LMP_FEATURES_REQ = 0x0027,
222 LMP_FEATURES_RES = 0x0028,
223 LMP_QUALITY_OF_SERVICE = 0x0029,
224 LMP_QOS_REQ = 0x002a,
225 LMP_RM_SCO_LINK_REQ = 0x002b,
226 LMP_SCO_LINK_REQ = 0x002c,
227 LMP_MAX_SLOT = 0x002d,
228 LMP_MAX_SLOT_REQ = 0x002e,
229 LMP_TIMING_ACCURACY_REQ = 0x002f,
230 LMP_TIMING_ACCURACY_RES = 0x0030,
231 LMP_SETUP_COMPLETE = 0x0031,
232 LMP_USE_SEMIPERM_KEY = 0x0032,
233 LMP_HOST_CONNECTION_REQ = 0x0033,
234 LMP_SLOT_OFFSET = 0x0034,
235 LMP_PAGE_MODE_REQ = 0x0035,
236 LMP_PAGE_SCAN_MODE_REQ = 0x0036,
237 LMP_SUPERVISION_TIMEOUT = 0x0037,
238 LMP_TEST_ACTIVATE = 0x0038,
239 LMP_TEST_CONTROL = 0x0039,
240 LMP_CRYPT_KEY_MASK_REQ = 0x003a,
241 LMP_CRYPT_KEY_MASK_RES = 0x003b,
242 LMP_SET_AFH = 0x003c,
243 LMP_ACCEPTED_EXT = 0x7f01,
244 LMP_NOT_ACCEPTED_EXT = 0x7f02,
245 LMP_FEATURES_REQ_EXT = 0x7f03,
246 LMP_FEATURES_RES_EXT = 0x7f04,
247 LMP_PACKET_TYPE_TBL_REQ = 0x7f0b,
248 LMP_ESCO_LINK_REQ = 0x7f0c,
249 LMP_RM_ESCO_LINK_REQ = 0x7f0d,
250 LMP_CHANNEL_CLASS_REQ = 0x7f10,
251 LMP_CHANNEL_CLASS = 0x7f11,
252};
253
254/* Host Controller Interface layer defines */
255
256enum hci_packet_type {
257 HCI_COMMAND_PKT = 0x01,
258 HCI_ACLDATA_PKT = 0x02,
259 HCI_SCODATA_PKT = 0x03,
260 HCI_EVENT_PKT = 0x04,
261 HCI_VENDOR_PKT = 0xff,
262};
263
264enum bt_packet_type {
265 HCI_2DH1 = 1 << 1,
266 HCI_3DH1 = 1 << 2,
267 HCI_DM1 = 1 << 3,
268 HCI_DH1 = 1 << 4,
269 HCI_2DH3 = 1 << 8,
270 HCI_3DH3 = 1 << 9,
271 HCI_DM3 = 1 << 10,
272 HCI_DH3 = 1 << 11,
273 HCI_2DH5 = 1 << 12,
274 HCI_3DH5 = 1 << 13,
275 HCI_DM5 = 1 << 14,
276 HCI_DH5 = 1 << 15,
277};
278
279enum sco_packet_type {
280 HCI_HV1 = 1 << 5,
281 HCI_HV2 = 1 << 6,
282 HCI_HV3 = 1 << 7,
283};
284
285enum ev_packet_type {
286 HCI_EV3 = 1 << 3,
287 HCI_EV4 = 1 << 4,
288 HCI_EV5 = 1 << 5,
289 HCI_2EV3 = 1 << 6,
290 HCI_3EV3 = 1 << 7,
291 HCI_2EV5 = 1 << 8,
292 HCI_3EV5 = 1 << 9,
293};
294
295enum hci_error_code {
296 HCI_SUCCESS = 0x00,
297 HCI_UNKNOWN_COMMAND = 0x01,
298 HCI_NO_CONNECTION = 0x02,
299 HCI_HARDWARE_FAILURE = 0x03,
300 HCI_PAGE_TIMEOUT = 0x04,
301 HCI_AUTHENTICATION_FAILURE = 0x05,
302 HCI_PIN_OR_KEY_MISSING = 0x06,
303 HCI_MEMORY_FULL = 0x07,
304 HCI_CONNECTION_TIMEOUT = 0x08,
305 HCI_MAX_NUMBER_OF_CONNECTIONS = 0x09,
306 HCI_MAX_NUMBER_OF_SCO_CONNECTIONS = 0x0a,
307 HCI_ACL_CONNECTION_EXISTS = 0x0b,
308 HCI_COMMAND_DISALLOWED = 0x0c,
309 HCI_REJECTED_LIMITED_RESOURCES = 0x0d,
310 HCI_REJECTED_SECURITY = 0x0e,
311 HCI_REJECTED_PERSONAL = 0x0f,
312 HCI_HOST_TIMEOUT = 0x10,
313 HCI_UNSUPPORTED_FEATURE = 0x11,
314 HCI_INVALID_PARAMETERS = 0x12,
315 HCI_OE_USER_ENDED_CONNECTION = 0x13,
316 HCI_OE_LOW_RESOURCES = 0x14,
317 HCI_OE_POWER_OFF = 0x15,
318 HCI_CONNECTION_TERMINATED = 0x16,
319 HCI_REPEATED_ATTEMPTS = 0x17,
320 HCI_PAIRING_NOT_ALLOWED = 0x18,
321 HCI_UNKNOWN_LMP_PDU = 0x19,
322 HCI_UNSUPPORTED_REMOTE_FEATURE = 0x1a,
323 HCI_SCO_OFFSET_REJECTED = 0x1b,
324 HCI_SCO_INTERVAL_REJECTED = 0x1c,
325 HCI_AIR_MODE_REJECTED = 0x1d,
326 HCI_INVALID_LMP_PARAMETERS = 0x1e,
327 HCI_UNSPECIFIED_ERROR = 0x1f,
328 HCI_UNSUPPORTED_LMP_PARAMETER_VALUE = 0x20,
329 HCI_ROLE_CHANGE_NOT_ALLOWED = 0x21,
330 HCI_LMP_RESPONSE_TIMEOUT = 0x22,
331 HCI_LMP_ERROR_TRANSACTION_COLLISION = 0x23,
332 HCI_LMP_PDU_NOT_ALLOWED = 0x24,
333 HCI_ENCRYPTION_MODE_NOT_ACCEPTED = 0x25,
334 HCI_UNIT_LINK_KEY_USED = 0x26,
335 HCI_QOS_NOT_SUPPORTED = 0x27,
336 HCI_INSTANT_PASSED = 0x28,
337 HCI_PAIRING_NOT_SUPPORTED = 0x29,
338 HCI_TRANSACTION_COLLISION = 0x2a,
339 HCI_QOS_UNACCEPTABLE_PARAMETER = 0x2c,
340 HCI_QOS_REJECTED = 0x2d,
341 HCI_CLASSIFICATION_NOT_SUPPORTED = 0x2e,
342 HCI_INSUFFICIENT_SECURITY = 0x2f,
343 HCI_PARAMETER_OUT_OF_RANGE = 0x30,
344 HCI_ROLE_SWITCH_PENDING = 0x32,
345 HCI_SLOT_VIOLATION = 0x34,
346 HCI_ROLE_SWITCH_FAILED = 0x35,
347};
348
349enum acl_flag_bits {
350 ACL_CONT = 1 << 0,
351 ACL_START = 1 << 1,
352 ACL_ACTIVE_BCAST = 1 << 2,
353 ACL_PICO_BCAST = 1 << 3,
354};
355
356enum baseband_link_type {
357 SCO_LINK = 0x00,
358 ACL_LINK = 0x01,
359};
360
361enum lmp_feature_bits0 {
362 LMP_3SLOT = 1 << 0,
363 LMP_5SLOT = 1 << 1,
364 LMP_ENCRYPT = 1 << 2,
365 LMP_SOFFSET = 1 << 3,
366 LMP_TACCURACY = 1 << 4,
367 LMP_RSWITCH = 1 << 5,
368 LMP_HOLD_MODE = 1 << 6,
369 LMP_SNIFF_MODE = 1 << 7,
370};
371
372enum lmp_feature_bits1 {
373 LMP_PARK = 1 << 0,
374 LMP_RSSI = 1 << 1,
375 LMP_QUALITY = 1 << 2,
376 LMP_SCO = 1 << 3,
377 LMP_HV2 = 1 << 4,
378 LMP_HV3 = 1 << 5,
379 LMP_ULAW = 1 << 6,
380 LMP_ALAW = 1 << 7,
381};
382
383enum lmp_feature_bits2 {
384 LMP_CVSD = 1 << 0,
385 LMP_PSCHEME = 1 << 1,
386 LMP_PCONTROL = 1 << 2,
387 LMP_TRSP_SCO = 1 << 3,
388 LMP_BCAST_ENC = 1 << 7,
389};
390
391enum lmp_feature_bits3 {
392 LMP_EDR_ACL_2M = 1 << 1,
393 LMP_EDR_ACL_3M = 1 << 2,
394 LMP_ENH_ISCAN = 1 << 3,
395 LMP_ILACE_ISCAN = 1 << 4,
396 LMP_ILACE_PSCAN = 1 << 5,
397 LMP_RSSI_INQ = 1 << 6,
398 LMP_ESCO = 1 << 7,
399};
400
401enum lmp_feature_bits4 {
402 LMP_EV4 = 1 << 0,
403 LMP_EV5 = 1 << 1,
404 LMP_AFH_CAP_SLV = 1 << 3,
405 LMP_AFH_CLS_SLV = 1 << 4,
406 LMP_EDR_3SLOT = 1 << 7,
407};
408
409enum lmp_feature_bits5 {
410 LMP_EDR_5SLOT = 1 << 0,
411 LMP_SNIFF_SUBR = 1 << 1,
412 LMP_AFH_CAP_MST = 1 << 3,
413 LMP_AFH_CLS_MST = 1 << 4,
414 LMP_EDR_ESCO_2M = 1 << 5,
415 LMP_EDR_ESCO_3M = 1 << 6,
416 LMP_EDR_3S_ESCO = 1 << 7,
417};
418
419enum lmp_feature_bits6 {
420 LMP_EXT_INQ = 1 << 0,
421};
422
423enum lmp_feature_bits7 {
424 LMP_EXT_FEAT = 1 << 7,
425};
426
427enum hci_link_policy {
428 HCI_LP_RSWITCH = 1 << 0,
429 HCI_LP_HOLD = 1 << 1,
430 HCI_LP_SNIFF = 1 << 2,
431 HCI_LP_PARK = 1 << 3,
432};
433
434enum hci_link_mode {
435 HCI_LM_ACCEPT = 1 << 15,
436 HCI_LM_MASTER = 1 << 0,
437 HCI_LM_AUTH = 1 << 1,
438 HCI_LM_ENCRYPT = 1 << 2,
439 HCI_LM_TRUSTED = 1 << 3,
440 HCI_LM_RELIABLE = 1 << 4,
441 HCI_LM_SECURE = 1 << 5,
442};
443
444/* HCI Commands */
445
446/* Link Control */
447#define OGF_LINK_CTL 0x01
448
449#define OCF_INQUIRY 0x0001
450typedef struct {
451 uint8_t lap[3];
452 uint8_t length; /* 1.28s units */
453 uint8_t num_rsp;
541dc0d4 454} QEMU_PACKED inquiry_cp;
58a26b47
AZ		 455#define INQUIRY_CP_SIZE 5
456
457typedef struct {
458 uint8_t status;
c227f099 459 bdaddr_t bdaddr;
541dc0d4 460} QEMU_PACKED status_bdaddr_rp;
58a26b47
AZ		 461#define STATUS_BDADDR_RP_SIZE 7
462
463#define OCF_INQUIRY_CANCEL 0x0002
464
465#define OCF_PERIODIC_INQUIRY 0x0003
466typedef struct {
467 uint16_t max_period; /* 1.28s units */
468 uint16_t min_period; /* 1.28s units */
469 uint8_t lap[3];
470 uint8_t length; /* 1.28s units */
471 uint8_t num_rsp;
541dc0d4 472} QEMU_PACKED periodic_inquiry_cp;
58a26b47
AZ		 473#define PERIODIC_INQUIRY_CP_SIZE 9
474
475#define OCF_EXIT_PERIODIC_INQUIRY 0x0004
476
477#define OCF_CREATE_CONN 0x0005
478typedef struct {
c227f099 479 bdaddr_t bdaddr;
58a26b47
AZ		 480 uint16_t pkt_type;
481 uint8_t pscan_rep_mode;
482 uint8_t pscan_mode;
483 uint16_t clock_offset;
484 uint8_t role_switch;
541dc0d4 485} QEMU_PACKED create_conn_cp;
58a26b47
AZ		 486#define CREATE_CONN_CP_SIZE 13
487
488#define OCF_DISCONNECT 0x0006
489typedef struct {
490 uint16_t handle;
491 uint8_t reason;
541dc0d4 492} QEMU_PACKED disconnect_cp;
58a26b47
AZ		 493#define DISCONNECT_CP_SIZE 3
494
495#define OCF_ADD_SCO 0x0007
496typedef struct {
497 uint16_t handle;
498 uint16_t pkt_type;
541dc0d4 499} QEMU_PACKED add_sco_cp;
58a26b47
AZ		 500#define ADD_SCO_CP_SIZE 4
501
502#define OCF_CREATE_CONN_CANCEL 0x0008
503typedef struct {
504 uint8_t status;
c227f099 505 bdaddr_t bdaddr;
541dc0d4 506} QEMU_PACKED create_conn_cancel_cp;
58a26b47
AZ		 507#define CREATE_CONN_CANCEL_CP_SIZE 6
508
509typedef struct {
510 uint8_t status;
c227f099 511 bdaddr_t bdaddr;
541dc0d4 512} QEMU_PACKED create_conn_cancel_rp;
58a26b47
AZ		 513#define CREATE_CONN_CANCEL_RP_SIZE 7
514
515#define OCF_ACCEPT_CONN_REQ 0x0009
516typedef struct {
c227f099 517 bdaddr_t bdaddr;
58a26b47 518 uint8_t role;
541dc0d4 519} QEMU_PACKED accept_conn_req_cp;
58a26b47
AZ		 520#define ACCEPT_CONN_REQ_CP_SIZE 7
521
522#define OCF_REJECT_CONN_REQ 0x000A
523typedef struct {
c227f099 524 bdaddr_t bdaddr;
58a26b47 525 uint8_t reason;
541dc0d4 526} QEMU_PACKED reject_conn_req_cp;
58a26b47
AZ		 527#define REJECT_CONN_REQ_CP_SIZE 7
528
529#define OCF_LINK_KEY_REPLY 0x000B
530typedef struct {
c227f099 531 bdaddr_t bdaddr;
58a26b47 532 uint8_t link_key[16];
541dc0d4 533} QEMU_PACKED link_key_reply_cp;
58a26b47
AZ		 534#define LINK_KEY_REPLY_CP_SIZE 22
535
536#define OCF_LINK_KEY_NEG_REPLY 0x000C
537
538#define OCF_PIN_CODE_REPLY 0x000D
539typedef struct {
c227f099 540 bdaddr_t bdaddr;
58a26b47
AZ		 541 uint8_t pin_len;
542 uint8_t pin_code[16];
541dc0d4 543} QEMU_PACKED pin_code_reply_cp;
58a26b47
AZ		 544#define PIN_CODE_REPLY_CP_SIZE 23
545
546#define OCF_PIN_CODE_NEG_REPLY 0x000E
547
548#define OCF_SET_CONN_PTYPE 0x000F
549typedef struct {
550 uint16_t handle;
551 uint16_t pkt_type;
541dc0d4 552} QEMU_PACKED set_conn_ptype_cp;
58a26b47
AZ		 553#define SET_CONN_PTYPE_CP_SIZE 4
554
555#define OCF_AUTH_REQUESTED 0x0011
556typedef struct {
557 uint16_t handle;
541dc0d4 558} QEMU_PACKED auth_requested_cp;
58a26b47
AZ		 559#define AUTH_REQUESTED_CP_SIZE 2
560
561#define OCF_SET_CONN_ENCRYPT 0x0013
562typedef struct {
563 uint16_t handle;
564 uint8_t encrypt;
541dc0d4 565} QEMU_PACKED set_conn_encrypt_cp;
58a26b47
AZ		 566#define SET_CONN_ENCRYPT_CP_SIZE 3
567
568#define OCF_CHANGE_CONN_LINK_KEY 0x0015
569typedef struct {
570 uint16_t handle;
541dc0d4 571} QEMU_PACKED change_conn_link_key_cp;
58a26b47
AZ		 572#define CHANGE_CONN_LINK_KEY_CP_SIZE 2
573
574#define OCF_MASTER_LINK_KEY 0x0017
575typedef struct {
576 uint8_t key_flag;
541dc0d4 577} QEMU_PACKED master_link_key_cp;
58a26b47
AZ		 578#define MASTER_LINK_KEY_CP_SIZE 1
579
580#define OCF_REMOTE_NAME_REQ 0x0019
581typedef struct {
c227f099 582 bdaddr_t bdaddr;
58a26b47
AZ		 583 uint8_t pscan_rep_mode;
584 uint8_t pscan_mode;
585 uint16_t clock_offset;
541dc0d4 586} QEMU_PACKED remote_name_req_cp;
58a26b47
AZ		 587#define REMOTE_NAME_REQ_CP_SIZE 10
588
589#define OCF_REMOTE_NAME_REQ_CANCEL 0x001A
590typedef struct {
c227f099 591 bdaddr_t bdaddr;
541dc0d4 592} QEMU_PACKED remote_name_req_cancel_cp;
58a26b47
AZ		 593#define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6
594
595typedef struct {
596 uint8_t status;
c227f099 597 bdaddr_t bdaddr;
541dc0d4 598} QEMU_PACKED remote_name_req_cancel_rp;
58a26b47
AZ		 599#define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7
600
601#define OCF_READ_REMOTE_FEATURES 0x001B
602typedef struct {
603 uint16_t handle;
541dc0d4 604} QEMU_PACKED read_remote_features_cp;
58a26b47
AZ		 605#define READ_REMOTE_FEATURES_CP_SIZE 2
606
607#define OCF_READ_REMOTE_EXT_FEATURES 0x001C
608typedef struct {
609 uint16_t handle;
610 uint8_t page_num;
541dc0d4 611} QEMU_PACKED read_remote_ext_features_cp;
58a26b47
AZ		 612#define READ_REMOTE_EXT_FEATURES_CP_SIZE 3
613
614#define OCF_READ_REMOTE_VERSION 0x001D
615typedef struct {
616 uint16_t handle;
541dc0d4 617} QEMU_PACKED read_remote_version_cp;
58a26b47
AZ		 618#define READ_REMOTE_VERSION_CP_SIZE 2
619
620#define OCF_READ_CLOCK_OFFSET 0x001F
621typedef struct {
622 uint16_t handle;
541dc0d4 623} QEMU_PACKED read_clock_offset_cp;
58a26b47
AZ		 624#define READ_CLOCK_OFFSET_CP_SIZE 2
625
626#define OCF_READ_LMP_HANDLE 0x0020
627typedef struct {
628 uint16_t handle;
541dc0d4 629} QEMU_PACKED read_lmp_handle_cp;
58a26b47
AZ		 630#define READ_LMP_HANDLE_CP_SIZE 2
631
632typedef struct {
633 uint8_t status;
634 uint16_t handle;
635 uint8_t lmp_handle;
636 uint32_t reserved;
541dc0d4 637} QEMU_PACKED read_lmp_handle_rp;
58a26b47
AZ		 638#define READ_LMP_HANDLE_RP_SIZE 8
639
640#define OCF_SETUP_SYNC_CONN 0x0028
641typedef struct {
642 uint16_t handle;
643 uint32_t tx_bandwith;
644 uint32_t rx_bandwith;
645 uint16_t max_latency;
646 uint16_t voice_setting;
647 uint8_t retrans_effort;
648 uint16_t pkt_type;
541dc0d4 649} QEMU_PACKED setup_sync_conn_cp;
58a26b47
AZ		 650#define SETUP_SYNC_CONN_CP_SIZE 17
651
652#define OCF_ACCEPT_SYNC_CONN_REQ 0x0029
653typedef struct {
c227f099 654 bdaddr_t bdaddr;
58a26b47
AZ		 655 uint32_t tx_bandwith;
656 uint32_t rx_bandwith;
657 uint16_t max_latency;
658 uint16_t voice_setting;
659 uint8_t retrans_effort;
660 uint16_t pkt_type;
541dc0d4 661} QEMU_PACKED accept_sync_conn_req_cp;
58a26b47
AZ		 662#define ACCEPT_SYNC_CONN_REQ_CP_SIZE 21
663
664#define OCF_REJECT_SYNC_CONN_REQ 0x002A
665typedef struct {
c227f099 666 bdaddr_t bdaddr;
58a26b47 667 uint8_t reason;
541dc0d4 668} QEMU_PACKED reject_sync_conn_req_cp;
58a26b47
AZ		 669#define REJECT_SYNC_CONN_REQ_CP_SIZE 7
670
671/* Link Policy */
672#define OGF_LINK_POLICY 0x02
673
674#define OCF_HOLD_MODE 0x0001
675typedef struct {
676 uint16_t handle;
677 uint16_t max_interval;
678 uint16_t min_interval;
541dc0d4 679} QEMU_PACKED hold_mode_cp;
58a26b47
AZ		 680#define HOLD_MODE_CP_SIZE 6
681
682#define OCF_SNIFF_MODE 0x0003
683typedef struct {
684 uint16_t handle;
685 uint16_t max_interval;
686 uint16_t min_interval;
687 uint16_t attempt;
688 uint16_t timeout;
541dc0d4 689} QEMU_PACKED sniff_mode_cp;
58a26b47
AZ		 690#define SNIFF_MODE_CP_SIZE 10
691
692#define OCF_EXIT_SNIFF_MODE 0x0004
693typedef struct {
694 uint16_t handle;
541dc0d4 695} QEMU_PACKED exit_sniff_mode_cp;
58a26b47
AZ		 696#define EXIT_SNIFF_MODE_CP_SIZE 2
697
698#define OCF_PARK_MODE 0x0005
699typedef struct {
700 uint16_t handle;
701 uint16_t max_interval;
702 uint16_t min_interval;
541dc0d4 703} QEMU_PACKED park_mode_cp;
58a26b47
AZ		 704#define PARK_MODE_CP_SIZE 6
705
706#define OCF_EXIT_PARK_MODE 0x0006
707typedef struct {
708 uint16_t handle;
541dc0d4 709} QEMU_PACKED exit_park_mode_cp;
58a26b47
AZ		 710#define EXIT_PARK_MODE_CP_SIZE 2
711
712#define OCF_QOS_SETUP 0x0007
713typedef struct {
714 uint8_t service_type; /* 1 = best effort */
715 uint32_t token_rate; /* Byte per seconds */
716 uint32_t peak_bandwidth; /* Byte per seconds */
717 uint32_t latency; /* Microseconds */
718 uint32_t delay_variation; /* Microseconds */
541dc0d4 719} QEMU_PACKED hci_qos;
58a26b47
AZ		 720#define HCI_QOS_CP_SIZE 17
721typedef struct {
722 uint16_t handle;
723 uint8_t flags; /* Reserved */
724 hci_qos qos;
541dc0d4 725} QEMU_PACKED qos_setup_cp;
58a26b47
AZ		 726#define QOS_SETUP_CP_SIZE (3 + HCI_QOS_CP_SIZE)
727
728#define OCF_ROLE_DISCOVERY 0x0009
729typedef struct {
730 uint16_t handle;
541dc0d4 731} QEMU_PACKED role_discovery_cp;
58a26b47
AZ		 732#define ROLE_DISCOVERY_CP_SIZE 2
733typedef struct {
734 uint8_t status;
735 uint16_t handle;
736 uint8_t role;
541dc0d4 737} QEMU_PACKED role_discovery_rp;
58a26b47
AZ		 738#define ROLE_DISCOVERY_RP_SIZE 4
739
740#define OCF_SWITCH_ROLE 0x000B
741typedef struct {
c227f099 742 bdaddr_t bdaddr;
58a26b47 743 uint8_t role;
541dc0d4 744} QEMU_PACKED switch_role_cp;
58a26b47
AZ		 745#define SWITCH_ROLE_CP_SIZE 7
746
747#define OCF_READ_LINK_POLICY 0x000C
748typedef struct {
749 uint16_t handle;
541dc0d4 750} QEMU_PACKED read_link_policy_cp;
58a26b47
AZ		 751#define READ_LINK_POLICY_CP_SIZE 2
752typedef struct {
753 uint8_t status;
754 uint16_t handle;
755 uint16_t policy;
541dc0d4 756} QEMU_PACKED read_link_policy_rp;
58a26b47
AZ		 757#define READ_LINK_POLICY_RP_SIZE 5
758
759#define OCF_WRITE_LINK_POLICY 0x000D
760typedef struct {
761 uint16_t handle;
762 uint16_t policy;
541dc0d4 763} QEMU_PACKED write_link_policy_cp;
58a26b47
AZ		 764#define WRITE_LINK_POLICY_CP_SIZE 4
765typedef struct {
766 uint8_t status;
767 uint16_t handle;
541dc0d4 768} QEMU_PACKED write_link_policy_rp;
58a26b47
AZ		 769#define WRITE_LINK_POLICY_RP_SIZE 3
770
771#define OCF_READ_DEFAULT_LINK_POLICY 0x000E
772
773#define OCF_WRITE_DEFAULT_LINK_POLICY 0x000F
774
775#define OCF_FLOW_SPECIFICATION 0x0010
776
777#define OCF_SNIFF_SUBRATE 0x0011
778typedef struct {
779 uint16_t handle;
780 uint16_t max_remote_latency;
781 uint16_t max_local_latency;
782 uint16_t min_remote_timeout;
783 uint16_t min_local_timeout;
541dc0d4 784} QEMU_PACKED sniff_subrate_cp;
58a26b47
AZ		 785#define SNIFF_SUBRATE_CP_SIZE 10
786
787/* Host Controller and Baseband */
788#define OGF_HOST_CTL 0x03
789
790#define OCF_SET_EVENT_MASK 0x0001
791typedef struct {
792 uint8_t mask[8];
541dc0d4 793} QEMU_PACKED set_event_mask_cp;
58a26b47
AZ		 794#define SET_EVENT_MASK_CP_SIZE 8
795
796#define OCF_RESET 0x0003
797
798#define OCF_SET_EVENT_FLT 0x0005
799typedef struct {
800 uint8_t flt_type;
801 uint8_t cond_type;
802 uint8_t condition[0];
541dc0d4 803} QEMU_PACKED set_event_flt_cp;
58a26b47
AZ		 804#define SET_EVENT_FLT_CP_SIZE 2
805
806enum bt_filter_type {
807 FLT_CLEAR_ALL = 0x00,
808 FLT_INQ_RESULT = 0x01,
809 FLT_CONN_SETUP = 0x02,
810};
811enum inq_result_cond_type {
812 INQ_RESULT_RETURN_ALL = 0x00,
813 INQ_RESULT_RETURN_CLASS = 0x01,
814 INQ_RESULT_RETURN_BDADDR = 0x02,
815};
816enum conn_setup_cond_type {
817 CONN_SETUP_ALLOW_ALL = 0x00,
818 CONN_SETUP_ALLOW_CLASS = 0x01,
819 CONN_SETUP_ALLOW_BDADDR = 0x02,
820};
821enum conn_setup_cond {
822 CONN_SETUP_AUTO_OFF = 0x01,
823 CONN_SETUP_AUTO_ON = 0x02,
824};
825
826#define OCF_FLUSH 0x0008
827typedef struct {
828 uint16_t handle;
541dc0d4 829} QEMU_PACKED flush_cp;
58a26b47
AZ		 830#define FLUSH_CP_SIZE 2
831
832typedef struct {
833 uint8_t status;
834 uint16_t handle;
541dc0d4 835} QEMU_PACKED flush_rp;
58a26b47
AZ		 836#define FLUSH_RP_SIZE 3
837
838#define OCF_READ_PIN_TYPE 0x0009
839typedef struct {
840 uint8_t status;
841 uint8_t pin_type;
541dc0d4 842} QEMU_PACKED read_pin_type_rp;
58a26b47
AZ		 843#define READ_PIN_TYPE_RP_SIZE 2
844
845#define OCF_WRITE_PIN_TYPE 0x000A
846typedef struct {
847 uint8_t pin_type;
541dc0d4 848} QEMU_PACKED write_pin_type_cp;
58a26b47
AZ		 849#define WRITE_PIN_TYPE_CP_SIZE 1
850
851#define OCF_CREATE_NEW_UNIT_KEY 0x000B
852
853#define OCF_READ_STORED_LINK_KEY 0x000D
854typedef struct {
c227f099 855 bdaddr_t bdaddr;
58a26b47 856 uint8_t read_all;
541dc0d4 857} QEMU_PACKED read_stored_link_key_cp;
58a26b47
AZ		 858#define READ_STORED_LINK_KEY_CP_SIZE 7
859typedef struct {
860 uint8_t status;
861 uint16_t max_keys;
862 uint16_t num_keys;
541dc0d4 863} QEMU_PACKED read_stored_link_key_rp;
58a26b47
AZ		 864#define READ_STORED_LINK_KEY_RP_SIZE 5
865
866#define OCF_WRITE_STORED_LINK_KEY 0x0011
867typedef struct {
868 uint8_t num_keys;
869 /* variable length part */
541dc0d4 870} QEMU_PACKED write_stored_link_key_cp;
58a26b47
AZ		 871#define WRITE_STORED_LINK_KEY_CP_SIZE 1
872typedef struct {
873 uint8_t status;
874 uint8_t num_keys;
541dc0d4 875} QEMU_PACKED write_stored_link_key_rp;
58a26b47
AZ		 876#define READ_WRITE_LINK_KEY_RP_SIZE 2
877
878#define OCF_DELETE_STORED_LINK_KEY 0x0012
879typedef struct {
c227f099 880 bdaddr_t bdaddr;
58a26b47 881 uint8_t delete_all;
541dc0d4 882} QEMU_PACKED delete_stored_link_key_cp;
58a26b47
AZ		 883#define DELETE_STORED_LINK_KEY_CP_SIZE 7
884typedef struct {
885 uint8_t status;
886 uint16_t num_keys;
541dc0d4 887} QEMU_PACKED delete_stored_link_key_rp;
58a26b47
AZ		 888#define DELETE_STORED_LINK_KEY_RP_SIZE 3
889
890#define OCF_CHANGE_LOCAL_NAME 0x0013
891typedef struct {
892 char name[248];
541dc0d4 893} QEMU_PACKED change_local_name_cp;
58a26b47
AZ		 894#define CHANGE_LOCAL_NAME_CP_SIZE 248
895
896#define OCF_READ_LOCAL_NAME 0x0014
897typedef struct {
898 uint8_t status;
899 char name[248];
541dc0d4 900} QEMU_PACKED read_local_name_rp;
58a26b47
AZ		 901#define READ_LOCAL_NAME_RP_SIZE 249
902
903#define OCF_READ_CONN_ACCEPT_TIMEOUT 0x0015
904typedef struct {
905 uint8_t status;
906 uint16_t timeout;
541dc0d4 907} QEMU_PACKED read_conn_accept_timeout_rp;
58a26b47
AZ		 908#define READ_CONN_ACCEPT_TIMEOUT_RP_SIZE 3
909
910#define OCF_WRITE_CONN_ACCEPT_TIMEOUT 0x0016
911typedef struct {
912 uint16_t timeout;
541dc0d4 913} QEMU_PACKED write_conn_accept_timeout_cp;
58a26b47
AZ		 914#define WRITE_CONN_ACCEPT_TIMEOUT_CP_SIZE 2
915
916#define OCF_READ_PAGE_TIMEOUT 0x0017
917typedef struct {
918 uint8_t status;
919 uint16_t timeout;
541dc0d4 920} QEMU_PACKED read_page_timeout_rp;
58a26b47
AZ		 921#define READ_PAGE_TIMEOUT_RP_SIZE 3
922
923#define OCF_WRITE_PAGE_TIMEOUT 0x0018
924typedef struct {
925 uint16_t timeout;
541dc0d4 926} QEMU_PACKED write_page_timeout_cp;
58a26b47
AZ		 927#define WRITE_PAGE_TIMEOUT_CP_SIZE 2
928
929#define OCF_READ_SCAN_ENABLE 0x0019
930typedef struct {
931 uint8_t status;
932 uint8_t enable;
541dc0d4 933} QEMU_PACKED read_scan_enable_rp;
58a26b47
AZ		 934#define READ_SCAN_ENABLE_RP_SIZE 2
935
936#define OCF_WRITE_SCAN_ENABLE 0x001A
937typedef struct {
938 uint8_t scan_enable;
541dc0d4 939} QEMU_PACKED write_scan_enable_cp;
58a26b47
AZ		 940#define WRITE_SCAN_ENABLE_CP_SIZE 1
941
942enum scan_enable_bits {
943 SCAN_DISABLED = 0,
944 SCAN_INQUIRY = 1 << 0,
945 SCAN_PAGE = 1 << 1,
946};
947
948#define OCF_READ_PAGE_ACTIVITY 0x001B
949typedef struct {
950 uint8_t status;
951 uint16_t interval;
952 uint16_t window;
541dc0d4 953} QEMU_PACKED read_page_activity_rp;
58a26b47
AZ		 954#define READ_PAGE_ACTIVITY_RP_SIZE 5
955
956#define OCF_WRITE_PAGE_ACTIVITY 0x001C
957typedef struct {
958 uint16_t interval;
959 uint16_t window;
541dc0d4 960} QEMU_PACKED write_page_activity_cp;
58a26b47
AZ		 961#define WRITE_PAGE_ACTIVITY_CP_SIZE 4
962
963#define OCF_READ_INQ_ACTIVITY 0x001D
964typedef struct {
965 uint8_t status;
966 uint16_t interval;
967 uint16_t window;
541dc0d4 968} QEMU_PACKED read_inq_activity_rp;
58a26b47
AZ		 969#define READ_INQ_ACTIVITY_RP_SIZE 5
970
971#define OCF_WRITE_INQ_ACTIVITY 0x001E
972typedef struct {
973 uint16_t interval;
974 uint16_t window;
541dc0d4 975} QEMU_PACKED write_inq_activity_cp;
58a26b47
AZ		 976#define WRITE_INQ_ACTIVITY_CP_SIZE 4
977
978#define OCF_READ_AUTH_ENABLE 0x001F
979
980#define OCF_WRITE_AUTH_ENABLE 0x0020
981
982#define AUTH_DISABLED 0x00
983#define AUTH_ENABLED 0x01
984
985#define OCF_READ_ENCRYPT_MODE 0x0021
986
987#define OCF_WRITE_ENCRYPT_MODE 0x0022
988
989#define ENCRYPT_DISABLED 0x00
990#define ENCRYPT_P2P 0x01
991#define ENCRYPT_BOTH 0x02
992
993#define OCF_READ_CLASS_OF_DEV 0x0023
994typedef struct {
995 uint8_t status;
996 uint8_t dev_class[3];
541dc0d4 997} QEMU_PACKED read_class_of_dev_rp;
58a26b47
AZ		 998#define READ_CLASS_OF_DEV_RP_SIZE 4
999
1000#define OCF_WRITE_CLASS_OF_DEV 0x0024
1001typedef struct {
1002 uint8_t dev_class[3];
541dc0d4 1003} QEMU_PACKED write_class_of_dev_cp;
58a26b47
AZ		 1004#define WRITE_CLASS_OF_DEV_CP_SIZE 3
1005
1006#define OCF_READ_VOICE_SETTING 0x0025
1007typedef struct {
1008 uint8_t status;
1009 uint16_t voice_setting;
541dc0d4 1010} QEMU_PACKED read_voice_setting_rp;
58a26b47
AZ		 1011#define READ_VOICE_SETTING_RP_SIZE 3
1012
1013#define OCF_WRITE_VOICE_SETTING 0x0026
1014typedef struct {
1015 uint16_t voice_setting;
541dc0d4 1016} QEMU_PACKED write_voice_setting_cp;
58a26b47
AZ		 1017#define WRITE_VOICE_SETTING_CP_SIZE 2
1018
1019#define OCF_READ_AUTOMATIC_FLUSH_TIMEOUT 0x0027
1020
1021#define OCF_WRITE_AUTOMATIC_FLUSH_TIMEOUT 0x0028
1022
1023#define OCF_READ_NUM_BROADCAST_RETRANS 0x0029
1024
1025#define OCF_WRITE_NUM_BROADCAST_RETRANS 0x002A
1026
1027#define OCF_READ_HOLD_MODE_ACTIVITY 0x002B
1028
1029#define OCF_WRITE_HOLD_MODE_ACTIVITY 0x002C
1030
1031#define OCF_READ_TRANSMIT_POWER_LEVEL 0x002D
1032typedef struct {
1033 uint16_t handle;
1034 uint8_t type;
541dc0d4 1035} QEMU_PACKED read_transmit_power_level_cp;
58a26b47
AZ		 1036#define READ_TRANSMIT_POWER_LEVEL_CP_SIZE 3
1037typedef struct {
1038 uint8_t status;
1039 uint16_t handle;
1040 int8_t level;
541dc0d4 1041} QEMU_PACKED read_transmit_power_level_rp;
58a26b47
AZ		 1042#define READ_TRANSMIT_POWER_LEVEL_RP_SIZE 4
1043
1044#define OCF_HOST_BUFFER_SIZE 0x0033
1045typedef struct {
1046 uint16_t acl_mtu;
1047 uint8_t sco_mtu;
1048 uint16_t acl_max_pkt;
1049 uint16_t sco_max_pkt;
541dc0d4 1050} QEMU_PACKED host_buffer_size_cp;
58a26b47
AZ		 1051#define HOST_BUFFER_SIZE_CP_SIZE 7
1052
1053#define OCF_HOST_NUMBER_OF_COMPLETED_PACKETS 0x0035
1054
1055#define OCF_READ_LINK_SUPERVISION_TIMEOUT 0x0036
1056typedef struct {
1057 uint8_t status;
1058 uint16_t handle;
1059 uint16_t link_sup_to;
541dc0d4 1060} QEMU_PACKED read_link_supervision_timeout_rp;
58a26b47
AZ		 1061#define READ_LINK_SUPERVISION_TIMEOUT_RP_SIZE 5
1062
1063#define OCF_WRITE_LINK_SUPERVISION_TIMEOUT 0x0037
1064typedef struct {
1065 uint16_t handle;
1066 uint16_t link_sup_to;
541dc0d4 1067} QEMU_PACKED write_link_supervision_timeout_cp;
58a26b47
AZ		 1068#define WRITE_LINK_SUPERVISION_TIMEOUT_CP_SIZE 4
1069typedef struct {
1070 uint8_t status;
1071 uint16_t handle;
541dc0d4 1072} QEMU_PACKED write_link_supervision_timeout_rp;
58a26b47
AZ		 1073#define WRITE_LINK_SUPERVISION_TIMEOUT_RP_SIZE 3
1074
1075#define OCF_READ_NUM_SUPPORTED_IAC 0x0038
1076
1077#define MAX_IAC_LAP 0x40
1078#define OCF_READ_CURRENT_IAC_LAP 0x0039
1079typedef struct {
1080 uint8_t status;
1081 uint8_t num_current_iac;
1082 uint8_t lap[MAX_IAC_LAP][3];
541dc0d4 1083} QEMU_PACKED read_current_iac_lap_rp;
58a26b47
AZ		 1084#define READ_CURRENT_IAC_LAP_RP_SIZE 2+3*MAX_IAC_LAP
1085
1086#define OCF_WRITE_CURRENT_IAC_LAP 0x003A
1087typedef struct {
1088 uint8_t num_current_iac;
1089 uint8_t lap[MAX_IAC_LAP][3];
541dc0d4 1090} QEMU_PACKED write_current_iac_lap_cp;
58a26b47
AZ		 1091#define WRITE_CURRENT_IAC_LAP_CP_SIZE 1+3*MAX_IAC_LAP
1092
1093#define OCF_READ_PAGE_SCAN_PERIOD_MODE 0x003B
1094
1095#define OCF_WRITE_PAGE_SCAN_PERIOD_MODE 0x003C
1096
1097#define OCF_READ_PAGE_SCAN_MODE 0x003D
1098
1099#define OCF_WRITE_PAGE_SCAN_MODE 0x003E
1100
1101#define OCF_SET_AFH_CLASSIFICATION 0x003F
1102typedef struct {
1103 uint8_t map[10];
541dc0d4 1104} QEMU_PACKED set_afh_classification_cp;
58a26b47
AZ		 1105#define SET_AFH_CLASSIFICATION_CP_SIZE 10
1106typedef struct {
1107 uint8_t status;
541dc0d4 1108} QEMU_PACKED set_afh_classification_rp;
58a26b47
AZ		 1109#define SET_AFH_CLASSIFICATION_RP_SIZE 1
1110
1111#define OCF_READ_INQUIRY_SCAN_TYPE 0x0042
1112typedef struct {
1113 uint8_t status;
1114 uint8_t type;
541dc0d4 1115} QEMU_PACKED read_inquiry_scan_type_rp;
58a26b47
AZ		 1116#define READ_INQUIRY_SCAN_TYPE_RP_SIZE 2
1117
1118#define OCF_WRITE_INQUIRY_SCAN_TYPE 0x0043
1119typedef struct {
1120 uint8_t type;
541dc0d4 1121} QEMU_PACKED write_inquiry_scan_type_cp;
58a26b47
AZ		 1122#define WRITE_INQUIRY_SCAN_TYPE_CP_SIZE 1
1123typedef struct {
1124 uint8_t status;
541dc0d4 1125} QEMU_PACKED write_inquiry_scan_type_rp;
58a26b47
AZ		 1126#define WRITE_INQUIRY_SCAN_TYPE_RP_SIZE 1
1127
1128#define OCF_READ_INQUIRY_MODE 0x0044
1129typedef struct {
1130 uint8_t status;
1131 uint8_t mode;
541dc0d4 1132} QEMU_PACKED read_inquiry_mode_rp;
58a26b47
AZ		 1133#define READ_INQUIRY_MODE_RP_SIZE 2
1134
1135#define OCF_WRITE_INQUIRY_MODE 0x0045
1136typedef struct {
1137 uint8_t mode;
541dc0d4 1138} QEMU_PACKED write_inquiry_mode_cp;
58a26b47
AZ		 1139#define WRITE_INQUIRY_MODE_CP_SIZE 1
1140typedef struct {
1141 uint8_t status;
541dc0d4 1142} QEMU_PACKED write_inquiry_mode_rp;
58a26b47
AZ		 1143#define WRITE_INQUIRY_MODE_RP_SIZE 1
1144
1145#define OCF_READ_PAGE_SCAN_TYPE 0x0046
1146
1147#define OCF_WRITE_PAGE_SCAN_TYPE 0x0047
1148
1149#define OCF_READ_AFH_MODE 0x0048
1150typedef struct {
1151 uint8_t status;
1152 uint8_t mode;
541dc0d4 1153} QEMU_PACKED read_afh_mode_rp;
58a26b47
AZ		 1154#define READ_AFH_MODE_RP_SIZE 2
1155
1156#define OCF_WRITE_AFH_MODE 0x0049
1157typedef struct {
1158 uint8_t mode;
541dc0d4 1159} QEMU_PACKED write_afh_mode_cp;
58a26b47
AZ		 1160#define WRITE_AFH_MODE_CP_SIZE 1
1161typedef struct {
1162 uint8_t status;
541dc0d4 1163} QEMU_PACKED write_afh_mode_rp;
58a26b47
AZ		 1164#define WRITE_AFH_MODE_RP_SIZE 1
1165
1166#define OCF_READ_EXT_INQUIRY_RESPONSE 0x0051
1167typedef struct {
1168 uint8_t status;
1169 uint8_t fec;
1170 uint8_t data[240];
541dc0d4 1171} QEMU_PACKED read_ext_inquiry_response_rp;
58a26b47
AZ		 1172#define READ_EXT_INQUIRY_RESPONSE_RP_SIZE 242
1173
1174#define OCF_WRITE_EXT_INQUIRY_RESPONSE 0x0052
1175typedef struct {
1176 uint8_t fec;
1177 uint8_t data[240];
541dc0d4 1178} QEMU_PACKED write_ext_inquiry_response_cp;
58a26b47
AZ		 1179#define WRITE_EXT_INQUIRY_RESPONSE_CP_SIZE 241
1180typedef struct {
1181 uint8_t status;
541dc0d4 1182} QEMU_PACKED write_ext_inquiry_response_rp;
58a26b47
AZ		 1183#define WRITE_EXT_INQUIRY_RESPONSE_RP_SIZE 1
1184
1185/* Informational Parameters */
1186#define OGF_INFO_PARAM 0x04
1187
1188#define OCF_READ_LOCAL_VERSION 0x0001
1189typedef struct {
1190 uint8_t status;
1191 uint8_t hci_ver;
1192 uint16_t hci_rev;
1193 uint8_t lmp_ver;
1194 uint16_t manufacturer;
1195 uint16_t lmp_subver;
541dc0d4 1196} QEMU_PACKED read_local_version_rp;
58a26b47
AZ		 1197#define READ_LOCAL_VERSION_RP_SIZE 9
1198
1199#define OCF_READ_LOCAL_COMMANDS 0x0002
1200typedef struct {
1201 uint8_t status;
1202 uint8_t commands[64];
541dc0d4 1203} QEMU_PACKED read_local_commands_rp;
58a26b47
AZ		 1204#define READ_LOCAL_COMMANDS_RP_SIZE 65
1205
1206#define OCF_READ_LOCAL_FEATURES 0x0003
1207typedef struct {
1208 uint8_t status;
1209 uint8_t features[8];
541dc0d4 1210} QEMU_PACKED read_local_features_rp;
58a26b47
AZ		 1211#define READ_LOCAL_FEATURES_RP_SIZE 9
1212
1213#define OCF_READ_LOCAL_EXT_FEATURES 0x0004
1214typedef struct {
1215 uint8_t page_num;
541dc0d4 1216} QEMU_PACKED read_local_ext_features_cp;
58a26b47
AZ		 1217#define READ_LOCAL_EXT_FEATURES_CP_SIZE 1
1218typedef struct {
1219 uint8_t status;
1220 uint8_t page_num;
1221 uint8_t max_page_num;
1222 uint8_t features[8];
541dc0d4 1223} QEMU_PACKED read_local_ext_features_rp;
58a26b47
AZ		 1224#define READ_LOCAL_EXT_FEATURES_RP_SIZE 11
1225
1226#define OCF_READ_BUFFER_SIZE 0x0005
1227typedef struct {
1228 uint8_t status;
1229 uint16_t acl_mtu;
1230 uint8_t sco_mtu;
1231 uint16_t acl_max_pkt;
1232 uint16_t sco_max_pkt;
541dc0d4 1233} QEMU_PACKED read_buffer_size_rp;
58a26b47
AZ		 1234#define READ_BUFFER_SIZE_RP_SIZE 8
1235
1236#define OCF_READ_COUNTRY_CODE 0x0007
1237typedef struct {
1238 uint8_t status;
1239 uint8_t country_code;
541dc0d4 1240} QEMU_PACKED read_country_code_rp;
58a26b47
AZ		 1241#define READ_COUNTRY_CODE_RP_SIZE 2
1242
1243#define OCF_READ_BD_ADDR 0x0009
1244typedef struct {
1245 uint8_t status;
c227f099 1246 bdaddr_t bdaddr;
541dc0d4 1247} QEMU_PACKED read_bd_addr_rp;
58a26b47
AZ		 1248#define READ_BD_ADDR_RP_SIZE 7
1249
1250/* Status params */
1251#define OGF_STATUS_PARAM 0x05
1252
1253#define OCF_READ_FAILED_CONTACT_COUNTER 0x0001
1254typedef struct {
1255 uint8_t status;
1256 uint16_t handle;
1257 uint8_t counter;
541dc0d4 1258} QEMU_PACKED read_failed_contact_counter_rp;
58a26b47
AZ		 1259#define READ_FAILED_CONTACT_COUNTER_RP_SIZE 4
1260
1261#define OCF_RESET_FAILED_CONTACT_COUNTER 0x0002
1262typedef struct {
1263 uint8_t status;
1264 uint16_t handle;
541dc0d4 1265} QEMU_PACKED reset_failed_contact_counter_rp;
58a26b47
AZ		 1266#define RESET_FAILED_CONTACT_COUNTER_RP_SIZE 4
1267
1268#define OCF_READ_LINK_QUALITY 0x0003
1269typedef struct {
1270 uint16_t handle;
541dc0d4 1271} QEMU_PACKED read_link_quality_cp;
58a26b47
AZ		 1272#define READ_LINK_QUALITY_CP_SIZE 4
1273
1274typedef struct {
1275 uint8_t status;
1276 uint16_t handle;
1277 uint8_t link_quality;
541dc0d4 1278} QEMU_PACKED read_link_quality_rp;
58a26b47
AZ		 1279#define READ_LINK_QUALITY_RP_SIZE 4
1280
1281#define OCF_READ_RSSI 0x0005
1282typedef struct {
1283 uint8_t status;
1284 uint16_t handle;
1285 int8_t rssi;
541dc0d4 1286} QEMU_PACKED read_rssi_rp;
58a26b47
AZ		 1287#define READ_RSSI_RP_SIZE 4
1288
1289#define OCF_READ_AFH_MAP 0x0006
1290typedef struct {
1291 uint8_t status;
1292 uint16_t handle;
1293 uint8_t mode;
1294 uint8_t map[10];
541dc0d4 1295} QEMU_PACKED read_afh_map_rp;
58a26b47
AZ		 1296#define READ_AFH_MAP_RP_SIZE 14
1297
1298#define OCF_READ_CLOCK 0x0007
1299typedef struct {
1300 uint16_t handle;
1301 uint8_t which_clock;
541dc0d4 1302} QEMU_PACKED read_clock_cp;
58a26b47
AZ		 1303#define READ_CLOCK_CP_SIZE 3
1304typedef struct {
1305 uint8_t status;
1306 uint16_t handle;
1307 uint32_t clock;
1308 uint16_t accuracy;
541dc0d4 1309} QEMU_PACKED read_clock_rp;
58a26b47
AZ		 1310#define READ_CLOCK_RP_SIZE 9
1311
1312/* Testing commands */
1313#define OGF_TESTING_CMD 0x3e
1314
1315/* Vendor specific commands */
1316#define OGF_VENDOR_CMD 0x3f
1317
1318/* HCI Events */
1319
1320#define EVT_INQUIRY_COMPLETE 0x01
1321
1322#define EVT_INQUIRY_RESULT 0x02
1323typedef struct {
1324 uint8_t num_responses;
c227f099 1325 bdaddr_t bdaddr;
58a26b47
AZ		 1326 uint8_t pscan_rep_mode;
1327 uint8_t pscan_period_mode;
1328 uint8_t pscan_mode;
1329 uint8_t dev_class[3];
1330 uint16_t clock_offset;
541dc0d4 1331} QEMU_PACKED inquiry_info;
58a26b47
AZ		 1332#define INQUIRY_INFO_SIZE 14
1333
1334#define EVT_CONN_COMPLETE 0x03
1335typedef struct {
1336 uint8_t status;
1337 uint16_t handle;
c227f099 1338 bdaddr_t bdaddr;
58a26b47
AZ		 1339 uint8_t link_type;
1340 uint8_t encr_mode;
541dc0d4 1341} QEMU_PACKED evt_conn_complete;
58a26b47
AZ		 1342#define EVT_CONN_COMPLETE_SIZE 11
1343
1344#define EVT_CONN_REQUEST 0x04
1345typedef struct {
c227f099 1346 bdaddr_t bdaddr;
58a26b47
AZ		 1347 uint8_t dev_class[3];
1348 uint8_t link_type;
541dc0d4 1349} QEMU_PACKED evt_conn_request;
58a26b47
AZ		 1350#define EVT_CONN_REQUEST_SIZE 10
1351
1352#define EVT_DISCONN_COMPLETE 0x05
1353typedef struct {
1354 uint8_t status;
1355 uint16_t handle;
1356 uint8_t reason;
541dc0d4 1357} QEMU_PACKED evt_disconn_complete;
58a26b47
AZ		 1358#define EVT_DISCONN_COMPLETE_SIZE 4
1359
1360#define EVT_AUTH_COMPLETE 0x06
1361typedef struct {
1362 uint8_t status;
1363 uint16_t handle;
541dc0d4 1364} QEMU_PACKED evt_auth_complete;
58a26b47
AZ		 1365#define EVT_AUTH_COMPLETE_SIZE 3
1366
1367#define EVT_REMOTE_NAME_REQ_COMPLETE 0x07
1368typedef struct {
1369 uint8_t status;
c227f099 1370 bdaddr_t bdaddr;
58a26b47 1371 char name[248];
541dc0d4 1372} QEMU_PACKED evt_remote_name_req_complete;
58a26b47
AZ		 1373#define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255
1374
1375#define EVT_ENCRYPT_CHANGE 0x08
1376typedef struct {
1377 uint8_t status;
1378 uint16_t handle;
1379 uint8_t encrypt;
541dc0d4 1380} QEMU_PACKED evt_encrypt_change;
58a26b47
AZ		 1381#define EVT_ENCRYPT_CHANGE_SIZE 5
1382
1383#define EVT_CHANGE_CONN_LINK_KEY_COMPLETE 0x09
1384typedef struct {
1385 uint8_t status;
1386 uint16_t handle;
541dc0d4 1387} QEMU_PACKED evt_change_conn_link_key_complete;
58a26b47
AZ		 1388#define EVT_CHANGE_CONN_LINK_KEY_COMPLETE_SIZE 3
1389
1390#define EVT_MASTER_LINK_KEY_COMPLETE 0x0A
1391typedef struct {
1392 uint8_t status;
1393 uint16_t handle;
1394 uint8_t key_flag;
541dc0d4 1395} QEMU_PACKED evt_master_link_key_complete;
58a26b47
AZ		 1396#define EVT_MASTER_LINK_KEY_COMPLETE_SIZE 4
1397
1398#define EVT_READ_REMOTE_FEATURES_COMPLETE 0x0B
1399typedef struct {
1400 uint8_t status;
1401 uint16_t handle;
1402 uint8_t features[8];
541dc0d4 1403} QEMU_PACKED evt_read_remote_features_complete;
58a26b47
AZ		 1404#define EVT_READ_REMOTE_FEATURES_COMPLETE_SIZE 11
1405
1406#define EVT_READ_REMOTE_VERSION_COMPLETE 0x0C
1407typedef struct {
1408 uint8_t status;
1409 uint16_t handle;
1410 uint8_t lmp_ver;
1411 uint16_t manufacturer;
1412 uint16_t lmp_subver;
541dc0d4 1413} QEMU_PACKED evt_read_remote_version_complete;
58a26b47
AZ		 1414#define EVT_READ_REMOTE_VERSION_COMPLETE_SIZE 8
1415
1416#define EVT_QOS_SETUP_COMPLETE 0x0D
1417typedef struct {
1418 uint8_t status;
1419 uint16_t handle;
1420 uint8_t flags; /* Reserved */
1421 hci_qos qos;
541dc0d4 1422} QEMU_PACKED evt_qos_setup_complete;
58a26b47
AZ		 1423#define EVT_QOS_SETUP_COMPLETE_SIZE (4 + HCI_QOS_CP_SIZE)
1424
1425#define EVT_CMD_COMPLETE 0x0E
1426typedef struct {
1427 uint8_t ncmd;
1428 uint16_t opcode;
541dc0d4 1429} QEMU_PACKED evt_cmd_complete;
58a26b47
AZ		 1430#define EVT_CMD_COMPLETE_SIZE 3
1431
1432#define EVT_CMD_STATUS 0x0F
1433typedef struct {
1434 uint8_t status;
1435 uint8_t ncmd;
1436 uint16_t opcode;
541dc0d4 1437} QEMU_PACKED evt_cmd_status;
58a26b47
AZ		 1438#define EVT_CMD_STATUS_SIZE 4
1439
1440#define EVT_HARDWARE_ERROR 0x10
1441typedef struct {
1442 uint8_t code;
541dc0d4 1443} QEMU_PACKED evt_hardware_error;
58a26b47
AZ		 1444#define EVT_HARDWARE_ERROR_SIZE 1
1445
1446#define EVT_FLUSH_OCCURRED 0x11
1447typedef struct {
1448 uint16_t handle;
541dc0d4 1449} QEMU_PACKED evt_flush_occurred;
58a26b47
AZ		 1450#define EVT_FLUSH_OCCURRED_SIZE 2
1451
1452#define EVT_ROLE_CHANGE 0x12
1453typedef struct {
1454 uint8_t status;
c227f099 1455 bdaddr_t bdaddr;
58a26b47 1456 uint8_t role;
541dc0d4 1457} QEMU_PACKED evt_role_change;
58a26b47
AZ		 1458#define EVT_ROLE_CHANGE_SIZE 8
1459
1460#define EVT_NUM_COMP_PKTS 0x13
1461typedef struct {
1462 uint8_t num_hndl;
1463 struct {
1464 uint16_t handle;
1465 uint16_t num_packets;
1466 } connection[0];
541dc0d4 1467} QEMU_PACKED evt_num_comp_pkts;
58a26b47
AZ		 1468#define EVT_NUM_COMP_PKTS_SIZE(num_hndl) (1 + 4 * (num_hndl))
1469
1470#define EVT_MODE_CHANGE 0x14
1471typedef struct {
1472 uint8_t status;
1473 uint16_t handle;
1474 uint8_t mode;
1475 uint16_t interval;
541dc0d4 1476} QEMU_PACKED evt_mode_change;
58a26b47
AZ		 1477#define EVT_MODE_CHANGE_SIZE 6
1478
1479#define EVT_RETURN_LINK_KEYS 0x15
1480typedef struct {
1481 uint8_t num_keys;
1482 /* variable length part */
541dc0d4 1483} QEMU_PACKED evt_return_link_keys;
58a26b47
AZ		 1484#define EVT_RETURN_LINK_KEYS_SIZE 1
1485
1486#define EVT_PIN_CODE_REQ 0x16
1487typedef struct {
c227f099 1488 bdaddr_t bdaddr;
541dc0d4 1489} QEMU_PACKED evt_pin_code_req;
58a26b47
AZ		 1490#define EVT_PIN_CODE_REQ_SIZE 6
1491
1492#define EVT_LINK_KEY_REQ 0x17
1493typedef struct {
c227f099 1494 bdaddr_t bdaddr;
541dc0d4 1495} QEMU_PACKED evt_link_key_req;
58a26b47
AZ		 1496#define EVT_LINK_KEY_REQ_SIZE 6
1497
1498#define EVT_LINK_KEY_NOTIFY 0x18
1499typedef struct {
c227f099 1500 bdaddr_t bdaddr;
58a26b47
AZ		 1501 uint8_t link_key[16];
1502 uint8_t key_type;
541dc0d4 1503} QEMU_PACKED evt_link_key_notify;
58a26b47
AZ		 1504#define EVT_LINK_KEY_NOTIFY_SIZE 23
1505
1506#define EVT_LOOPBACK_COMMAND 0x19
1507
1508#define EVT_DATA_BUFFER_OVERFLOW 0x1A
1509typedef struct {
1510 uint8_t link_type;
541dc0d4 1511} QEMU_PACKED evt_data_buffer_overflow;
58a26b47
AZ		 1512#define EVT_DATA_BUFFER_OVERFLOW_SIZE 1
1513
1514#define EVT_MAX_SLOTS_CHANGE 0x1B
1515typedef struct {
1516 uint16_t handle;
1517 uint8_t max_slots;
541dc0d4 1518} QEMU_PACKED evt_max_slots_change;
58a26b47
AZ		 1519#define EVT_MAX_SLOTS_CHANGE_SIZE 3
1520
1521#define EVT_READ_CLOCK_OFFSET_COMPLETE 0x1C
1522typedef struct {
1523 uint8_t status;
1524 uint16_t handle;
1525 uint16_t clock_offset;
541dc0d4 1526} QEMU_PACKED evt_read_clock_offset_complete;
58a26b47
AZ		 1527#define EVT_READ_CLOCK_OFFSET_COMPLETE_SIZE 5
1528
1529#define EVT_CONN_PTYPE_CHANGED 0x1D
1530typedef struct {
1531 uint8_t status;
1532 uint16_t handle;
1533 uint16_t ptype;
541dc0d4 1534} QEMU_PACKED evt_conn_ptype_changed;
58a26b47
AZ		 1535#define EVT_CONN_PTYPE_CHANGED_SIZE 5
1536
1537#define EVT_QOS_VIOLATION 0x1E
1538typedef struct {
1539 uint16_t handle;
541dc0d4 1540} QEMU_PACKED evt_qos_violation;
58a26b47
AZ		 1541#define EVT_QOS_VIOLATION_SIZE 2
1542
1543#define EVT_PSCAN_REP_MODE_CHANGE 0x20
1544typedef struct {
c227f099 1545 bdaddr_t bdaddr;
58a26b47 1546 uint8_t pscan_rep_mode;
541dc0d4 1547} QEMU_PACKED evt_pscan_rep_mode_change;
58a26b47
AZ		 1548#define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7
1549
1550#define EVT_FLOW_SPEC_COMPLETE 0x21
1551typedef struct {
1552 uint8_t status;
1553 uint16_t handle;
1554 uint8_t flags;
1555 uint8_t direction;
1556 hci_qos qos;
541dc0d4 1557} QEMU_PACKED evt_flow_spec_complete;
58a26b47
AZ		 1558#define EVT_FLOW_SPEC_COMPLETE_SIZE (5 + HCI_QOS_CP_SIZE)
1559
1560#define EVT_INQUIRY_RESULT_WITH_RSSI 0x22
1561typedef struct {
1562 uint8_t num_responses;
c227f099 1563 bdaddr_t bdaddr;
58a26b47
AZ		 1564 uint8_t pscan_rep_mode;
1565 uint8_t pscan_period_mode;
1566 uint8_t dev_class[3];
1567 uint16_t clock_offset;
1568 int8_t rssi;
541dc0d4 1569} QEMU_PACKED inquiry_info_with_rssi;
58a26b47
AZ		 1570#define INQUIRY_INFO_WITH_RSSI_SIZE 15
1571typedef struct {
1572 uint8_t num_responses;
c227f099 1573 bdaddr_t bdaddr;
58a26b47
AZ		 1574 uint8_t pscan_rep_mode;
1575 uint8_t pscan_period_mode;
1576 uint8_t pscan_mode;
1577 uint8_t dev_class[3];
1578 uint16_t clock_offset;
1579 int8_t rssi;
541dc0d4 1580} QEMU_PACKED inquiry_info_with_rssi_and_pscan_mode;
58a26b47
AZ		 1581#define INQUIRY_INFO_WITH_RSSI_AND_PSCAN_MODE_SIZE 16
1582
1583#define EVT_READ_REMOTE_EXT_FEATURES_COMPLETE 0x23
1584typedef struct {
1585 uint8_t status;
1586 uint16_t handle;
1587 uint8_t page_num;
1588 uint8_t max_page_num;
1589 uint8_t features[8];
541dc0d4 1590} QEMU_PACKED evt_read_remote_ext_features_complete;
58a26b47
AZ		 1591#define EVT_READ_REMOTE_EXT_FEATURES_COMPLETE_SIZE 13
1592
1593#define EVT_SYNC_CONN_COMPLETE 0x2C
1594typedef struct {
1595 uint8_t status;
1596 uint16_t handle;
c227f099 1597 bdaddr_t bdaddr;
58a26b47
AZ		 1598 uint8_t link_type;
1599 uint8_t trans_interval;
1600 uint8_t retrans_window;
1601 uint16_t rx_pkt_len;
1602 uint16_t tx_pkt_len;
1603 uint8_t air_mode;
541dc0d4 1604} QEMU_PACKED evt_sync_conn_complete;
58a26b47
AZ		 1605#define EVT_SYNC_CONN_COMPLETE_SIZE 17
1606
1607#define EVT_SYNC_CONN_CHANGED 0x2D
1608typedef struct {
1609 uint8_t status;
1610 uint16_t handle;
1611 uint8_t trans_interval;
1612 uint8_t retrans_window;
1613 uint16_t rx_pkt_len;
1614 uint16_t tx_pkt_len;
541dc0d4 1615} QEMU_PACKED evt_sync_conn_changed;
58a26b47
AZ		 1616#define EVT_SYNC_CONN_CHANGED_SIZE 9
1617
1618#define EVT_SNIFF_SUBRATE 0x2E
1619typedef struct {
1620 uint8_t status;
1621 uint16_t handle;
1622 uint16_t max_remote_latency;
1623 uint16_t max_local_latency;
1624 uint16_t min_remote_timeout;
1625 uint16_t min_local_timeout;
541dc0d4 1626} QEMU_PACKED evt_sniff_subrate;
58a26b47
AZ		 1627#define EVT_SNIFF_SUBRATE_SIZE 11
1628
1629#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
1630typedef struct {
c227f099 1631 bdaddr_t bdaddr;
58a26b47
AZ		 1632 uint8_t pscan_rep_mode;
1633 uint8_t pscan_period_mode;
1634 uint8_t dev_class[3];
1635 uint16_t clock_offset;
1636 int8_t rssi;
1637 uint8_t data[240];
541dc0d4 1638} QEMU_PACKED extended_inquiry_info;
58a26b47
AZ		 1639#define EXTENDED_INQUIRY_INFO_SIZE 254
1640
1641#define EVT_TESTING 0xFE
1642
1643#define EVT_VENDOR 0xFF
1644
1645/* Command opcode pack/unpack */
1646#define cmd_opcode_pack(ogf, ocf) (uint16_t)((ocf & 0x03ff)|(ogf << 10))
1647#define cmd_opcode_ogf(op) (op >> 10)
1648#define cmd_opcode_ocf(op) (op & 0x03ff)
1649
1650/* ACL handle and flags pack/unpack */
1651#define acl_handle_pack(h, f) (uint16_t)(((h) & 0x0fff)|((f) << 12))
1652#define acl_handle(h) ((h) & 0x0fff)
1653#define acl_flags(h) ((h) >> 12)
1654
1655/* HCI Packet structures */
1656#define HCI_COMMAND_HDR_SIZE 3
1657#define HCI_EVENT_HDR_SIZE 2
1658#define HCI_ACL_HDR_SIZE 4
1659#define HCI_SCO_HDR_SIZE 3
1660
1661struct hci_command_hdr {
1662 uint16_t opcode; /* OCF & OGF */
1663 uint8_t plen;
541dc0d4 1664} QEMU_PACKED;
58a26b47
AZ		 1665
1666struct hci_event_hdr {
1667 uint8_t evt;
1668 uint8_t plen;
541dc0d4 1669} QEMU_PACKED;
58a26b47
AZ		 1670
1671struct hci_acl_hdr {
1672 uint16_t handle; /* Handle & Flags(PB, BC) */
1673 uint16_t dlen;
541dc0d4 1674} QEMU_PACKED;
58a26b47
AZ		 1675
1676struct hci_sco_hdr {
1677 uint16_t handle;
1678 uint8_t dlen;
541dc0d4 1679} QEMU_PACKED;
4d2d181c
AZ		 1680
1681/* L2CAP layer defines */
1682
1683enum bt_l2cap_lm_bits {
1684 L2CAP_LM_MASTER = 1 << 0,
1685 L2CAP_LM_AUTH = 1 << 1,
1686 L2CAP_LM_ENCRYPT = 1 << 2,
1687 L2CAP_LM_TRUSTED = 1 << 3,
1688 L2CAP_LM_RELIABLE = 1 << 4,
1689 L2CAP_LM_SECURE = 1 << 5,
1690};
1691
1692enum bt_l2cap_cid_predef {
1693 L2CAP_CID_INVALID = 0x0000,
1694 L2CAP_CID_SIGNALLING= 0x0001,
1695 L2CAP_CID_GROUP = 0x0002,
1696 L2CAP_CID_ALLOC = 0x0040,
1697};
1698
1699/* L2CAP command codes */
1700enum bt_l2cap_cmd {
1701 L2CAP_COMMAND_REJ = 1,
1702 L2CAP_CONN_REQ,
1703 L2CAP_CONN_RSP,
1704 L2CAP_CONF_REQ,
1705 L2CAP_CONF_RSP,
1706 L2CAP_DISCONN_REQ,
1707 L2CAP_DISCONN_RSP,
1708 L2CAP_ECHO_REQ,
1709 L2CAP_ECHO_RSP,
1710 L2CAP_INFO_REQ,
1711 L2CAP_INFO_RSP,
1712};
1713
1714enum bt_l2cap_sar_bits {
1715 L2CAP_SAR_NO_SEG = 0,
1716 L2CAP_SAR_START,
1717 L2CAP_SAR_END,
1718 L2CAP_SAR_CONT,
1719};
1720
1721/* L2CAP structures */
1722typedef struct {
1723 uint16_t len;
1724 uint16_t cid;
1725 uint8_t data[0];
541dc0d4 1726} QEMU_PACKED l2cap_hdr;
4d2d181c
AZ		 1727#define L2CAP_HDR_SIZE 4
1728
1729typedef struct {
1730 uint8_t code;
1731 uint8_t ident;
1732 uint16_t len;
541dc0d4 1733} QEMU_PACKED l2cap_cmd_hdr;
4d2d181c
AZ		 1734#define L2CAP_CMD_HDR_SIZE 4
1735
1736typedef struct {
1737 uint16_t reason;
541dc0d4 1738} QEMU_PACKED l2cap_cmd_rej;
4d2d181c
AZ		 1739#define L2CAP_CMD_REJ_SIZE 2
1740
1741typedef struct {
1742 uint16_t dcid;
1743 uint16_t scid;
541dc0d4 1744} QEMU_PACKED l2cap_cmd_rej_cid;
4d2d181c
AZ		 1745#define L2CAP_CMD_REJ_CID_SIZE 4
1746
1747/* reject reason */
1748enum bt_l2cap_rej_reason {
1749 L2CAP_REJ_CMD_NOT_UNDERSTOOD = 0,
1750 L2CAP_REJ_SIG_TOOBIG,
1751 L2CAP_REJ_CID_INVAL,
1752};
1753
1754typedef struct {
1755 uint16_t psm;
1756 uint16_t scid;
541dc0d4 1757} QEMU_PACKED l2cap_conn_req;
4d2d181c
AZ		 1758#define L2CAP_CONN_REQ_SIZE 4
1759
1760typedef struct {
1761 uint16_t dcid;
1762 uint16_t scid;
1763 uint16_t result;
1764 uint16_t status;
541dc0d4 1765} QEMU_PACKED l2cap_conn_rsp;
4d2d181c
AZ		 1766#define L2CAP_CONN_RSP_SIZE 8
1767
1768/* connect result */
1769enum bt_l2cap_conn_res {
1770 L2CAP_CR_SUCCESS = 0,
1771 L2CAP_CR_PEND,
1772 L2CAP_CR_BAD_PSM,
1773 L2CAP_CR_SEC_BLOCK,
1774 L2CAP_CR_NO_MEM,
1775};
1776
1777/* connect status */
1778enum bt_l2cap_conn_stat {
1779 L2CAP_CS_NO_INFO = 0,
1780 L2CAP_CS_AUTHEN_PEND,
1781 L2CAP_CS_AUTHOR_PEND,
1782};
1783
1784typedef struct {
1785 uint16_t dcid;
1786 uint16_t flags;
1787 uint8_t data[0];
541dc0d4 1788} QEMU_PACKED l2cap_conf_req;
4d2d181c
AZ		 1789#define L2CAP_CONF_REQ_SIZE(datalen) (4 + (datalen))
1790
1791typedef struct {
1792 uint16_t scid;
1793 uint16_t flags;
1794 uint16_t result;
1795 uint8_t data[0];
541dc0d4 1796} QEMU_PACKED l2cap_conf_rsp;
4d2d181c
AZ		 1797#define L2CAP_CONF_RSP_SIZE(datalen) (6 + datalen)
1798
1799enum bt_l2cap_conf_res {
1800 L2CAP_CONF_SUCCESS = 0,
1801 L2CAP_CONF_UNACCEPT,
1802 L2CAP_CONF_REJECT,
1803 L2CAP_CONF_UNKNOWN,
1804};
1805
1806typedef struct {
1807 uint8_t type;
1808 uint8_t len;
1809 uint8_t val[0];
541dc0d4 1810} QEMU_PACKED l2cap_conf_opt;
4d2d181c
AZ		 1811#define L2CAP_CONF_OPT_SIZE 2
1812
1813enum bt_l2cap_conf_val {
1814 L2CAP_CONF_MTU = 1,
1815 L2CAP_CONF_FLUSH_TO,
1816 L2CAP_CONF_QOS,
1817 L2CAP_CONF_RFC,
1818 L2CAP_CONF_RFC_MODE = L2CAP_CONF_RFC,
1819};
1820
1821typedef struct {
1822 uint8_t flags;
1823 uint8_t service_type;
1824 uint32_t token_rate;
1825 uint32_t token_bucket_size;
1826 uint32_t peak_bandwidth;
1827 uint32_t latency;
1828 uint32_t delay_variation;
541dc0d4 1829} QEMU_PACKED l2cap_conf_opt_qos;
4d2d181c
AZ		 1830#define L2CAP_CONF_OPT_QOS_SIZE 22
1831
1832enum bt_l2cap_conf_opt_qos_st {
1833 L2CAP_CONF_QOS_NO_TRAFFIC = 0x00,
1834 L2CAP_CONF_QOS_BEST_EFFORT,
1835 L2CAP_CONF_QOS_GUARANTEED,
1836};
1837
1838#define L2CAP_CONF_QOS_WILDCARD 0xffffffff
1839
1840enum bt_l2cap_mode {
1841 L2CAP_MODE_BASIC = 0,
1842 L2CAP_MODE_RETRANS = 1,
1843 L2CAP_MODE_FLOWCTL = 2,
1844};
1845
1846typedef struct {
1847 uint16_t dcid;
1848 uint16_t scid;
541dc0d4 1849} QEMU_PACKED l2cap_disconn_req;
4d2d181c
AZ		 1850#define L2CAP_DISCONN_REQ_SIZE 4
1851
1852typedef struct {
1853 uint16_t dcid;
1854 uint16_t scid;
541dc0d4 1855} QEMU_PACKED l2cap_disconn_rsp;
4d2d181c
AZ		 1856#define L2CAP_DISCONN_RSP_SIZE 4
1857
1858typedef struct {
1859 uint16_t type;
541dc0d4 1860} QEMU_PACKED l2cap_info_req;
4d2d181c
AZ		 1861#define L2CAP_INFO_REQ_SIZE 2
1862
1863typedef struct {
1864 uint16_t type;
1865 uint16_t result;
1866 uint8_t data[0];
541dc0d4 1867} QEMU_PACKED l2cap_info_rsp;
4d2d181c
AZ		 1868#define L2CAP_INFO_RSP_SIZE 4
1869
1870/* info type */
1871enum bt_l2cap_info_type {
1872 L2CAP_IT_CL_MTU = 1,
1873 L2CAP_IT_FEAT_MASK,
1874};
1875
1876/* info result */
1877enum bt_l2cap_info_result {
1878 L2CAP_IR_SUCCESS = 0,
1879 L2CAP_IR_NOTSUPP,
1880};
1881
1882/* Service Discovery Protocol defines */
1883/* Note that all multibyte values in lower layer protocols (above in this file)
1884 * are little-endian while SDP is big-endian. */
1885
1886/* Protocol UUIDs */
1887enum sdp_proto_uuid {
1888 SDP_UUID = 0x0001,
1889 UDP_UUID = 0x0002,
1890 RFCOMM_UUID = 0x0003,
1891 TCP_UUID = 0x0004,
1892 TCS_BIN_UUID = 0x0005,
1893 TCS_AT_UUID = 0x0006,
1894 OBEX_UUID = 0x0008,
1895 IP_UUID = 0x0009,
1896 FTP_UUID = 0x000a,
1897 HTTP_UUID = 0x000c,
1898 WSP_UUID = 0x000e,
1899 BNEP_UUID = 0x000f,
1900 UPNP_UUID = 0x0010,
1901 HIDP_UUID = 0x0011,
1902 HCRP_CTRL_UUID = 0x0012,
1903 HCRP_DATA_UUID = 0x0014,
1904 HCRP_NOTE_UUID = 0x0016,
1905 AVCTP_UUID = 0x0017,
1906 AVDTP_UUID = 0x0019,
1907 CMTP_UUID = 0x001b,
1908 UDI_UUID = 0x001d,
1909 MCAP_CTRL_UUID = 0x001e,
1910 MCAP_DATA_UUID = 0x001f,
1911 L2CAP_UUID = 0x0100,
1912};
1913
1914/*
1915 * Service class identifiers of standard services and service groups
1916 */
1917enum service_class_id {
1918 SDP_SERVER_SVCLASS_ID = 0x1000,
1919 BROWSE_GRP_DESC_SVCLASS_ID = 0x1001,
1920 PUBLIC_BROWSE_GROUP = 0x1002,
1921 SERIAL_PORT_SVCLASS_ID = 0x1101,
1922 LAN_ACCESS_SVCLASS_ID = 0x1102,
1923 DIALUP_NET_SVCLASS_ID = 0x1103,
1924 IRMC_SYNC_SVCLASS_ID = 0x1104,
1925 OBEX_OBJPUSH_SVCLASS_ID = 0x1105,
1926 OBEX_FILETRANS_SVCLASS_ID = 0x1106,
1927 IRMC_SYNC_CMD_SVCLASS_ID = 0x1107,
1928 HEADSET_SVCLASS_ID = 0x1108,
1929 CORDLESS_TELEPHONY_SVCLASS_ID = 0x1109,
1930 AUDIO_SOURCE_SVCLASS_ID = 0x110a,
1931 AUDIO_SINK_SVCLASS_ID = 0x110b,
1932 AV_REMOTE_TARGET_SVCLASS_ID = 0x110c,
1933 ADVANCED_AUDIO_SVCLASS_ID = 0x110d,
1934 AV_REMOTE_SVCLASS_ID = 0x110e,
1935 VIDEO_CONF_SVCLASS_ID = 0x110f,
1936 INTERCOM_SVCLASS_ID = 0x1110,
1937 FAX_SVCLASS_ID = 0x1111,
1938 HEADSET_AGW_SVCLASS_ID = 0x1112,
1939 WAP_SVCLASS_ID = 0x1113,
1940 WAP_CLIENT_SVCLASS_ID = 0x1114,
1941 PANU_SVCLASS_ID = 0x1115,
1942 NAP_SVCLASS_ID = 0x1116,
1943 GN_SVCLASS_ID = 0x1117,
1944 DIRECT_PRINTING_SVCLASS_ID = 0x1118,
1945 REFERENCE_PRINTING_SVCLASS_ID = 0x1119,
1946 IMAGING_SVCLASS_ID = 0x111a,
1947 IMAGING_RESPONDER_SVCLASS_ID = 0x111b,
1948 IMAGING_ARCHIVE_SVCLASS_ID = 0x111c,
1949 IMAGING_REFOBJS_SVCLASS_ID = 0x111d,
1950 HANDSFREE_SVCLASS_ID = 0x111e,
1951 HANDSFREE_AGW_SVCLASS_ID = 0x111f,
1952 DIRECT_PRT_REFOBJS_SVCLASS_ID = 0x1120,
1953 REFLECTED_UI_SVCLASS_ID = 0x1121,
1954 BASIC_PRINTING_SVCLASS_ID = 0x1122,
1955 PRINTING_STATUS_SVCLASS_ID = 0x1123,
1956 HID_SVCLASS_ID = 0x1124,
1957 HCR_SVCLASS_ID = 0x1125,
1958 HCR_PRINT_SVCLASS_ID = 0x1126,
1959 HCR_SCAN_SVCLASS_ID = 0x1127,
1960 CIP_SVCLASS_ID = 0x1128,
1961 VIDEO_CONF_GW_SVCLASS_ID = 0x1129,
1962 UDI_MT_SVCLASS_ID = 0x112a,
1963 UDI_TA_SVCLASS_ID = 0x112b,
1964 AV_SVCLASS_ID = 0x112c,
1965 SAP_SVCLASS_ID = 0x112d,
1966 PBAP_PCE_SVCLASS_ID = 0x112e,
1967 PBAP_PSE_SVCLASS_ID = 0x112f,
1968 PBAP_SVCLASS_ID = 0x1130,
1969 PNP_INFO_SVCLASS_ID = 0x1200,
1970 GENERIC_NETWORKING_SVCLASS_ID = 0x1201,
1971 GENERIC_FILETRANS_SVCLASS_ID = 0x1202,
1972 GENERIC_AUDIO_SVCLASS_ID = 0x1203,
1973 GENERIC_TELEPHONY_SVCLASS_ID = 0x1204,
1974 UPNP_SVCLASS_ID = 0x1205,
1975 UPNP_IP_SVCLASS_ID = 0x1206,
1976 UPNP_PAN_SVCLASS_ID = 0x1300,
1977 UPNP_LAP_SVCLASS_ID = 0x1301,
1978 UPNP_L2CAP_SVCLASS_ID = 0x1302,
1979 VIDEO_SOURCE_SVCLASS_ID = 0x1303,
1980 VIDEO_SINK_SVCLASS_ID = 0x1304,
1981 VIDEO_DISTRIBUTION_SVCLASS_ID = 0x1305,
1982 MDP_SVCLASS_ID = 0x1400,
1983 MDP_SOURCE_SVCLASS_ID = 0x1401,
1984 MDP_SINK_SVCLASS_ID = 0x1402,
1985 APPLE_AGENT_SVCLASS_ID = 0x2112,
1986};
1987
1988/*
1989 * Standard profile descriptor identifiers; note these
1990 * may be identical to some of the service classes defined above
1991 */
1992#define SDP_SERVER_PROFILE_ID SDP_SERVER_SVCLASS_ID
1993#define BROWSE_GRP_DESC_PROFILE_ID BROWSE_GRP_DESC_SVCLASS_ID
1994#define SERIAL_PORT_PROFILE_ID SERIAL_PORT_SVCLASS_ID
1995#define LAN_ACCESS_PROFILE_ID LAN_ACCESS_SVCLASS_ID
1996#define DIALUP_NET_PROFILE_ID DIALUP_NET_SVCLASS_ID
1997#define IRMC_SYNC_PROFILE_ID IRMC_SYNC_SVCLASS_ID
1998#define OBEX_OBJPUSH_PROFILE_ID OBEX_OBJPUSH_SVCLASS_ID
1999#define OBEX_FILETRANS_PROFILE_ID OBEX_FILETRANS_SVCLASS_ID
2000#define IRMC_SYNC_CMD_PROFILE_ID IRMC_SYNC_CMD_SVCLASS_ID
2001#define HEADSET_PROFILE_ID HEADSET_SVCLASS_ID
2002#define CORDLESS_TELEPHONY_PROFILE_ID CORDLESS_TELEPHONY_SVCLASS_ID
2003#define AUDIO_SOURCE_PROFILE_ID AUDIO_SOURCE_SVCLASS_ID
2004#define AUDIO_SINK_PROFILE_ID AUDIO_SINK_SVCLASS_ID
2005#define AV_REMOTE_TARGET_PROFILE_ID AV_REMOTE_TARGET_SVCLASS_ID
2006#define ADVANCED_AUDIO_PROFILE_ID ADVANCED_AUDIO_SVCLASS_ID
2007#define AV_REMOTE_PROFILE_ID AV_REMOTE_SVCLASS_ID
2008#define VIDEO_CONF_PROFILE_ID VIDEO_CONF_SVCLASS_ID
2009#define INTERCOM_PROFILE_ID INTERCOM_SVCLASS_ID
2010#define FAX_PROFILE_ID FAX_SVCLASS_ID
2011#define HEADSET_AGW_PROFILE_ID HEADSET_AGW_SVCLASS_ID
2012#define WAP_PROFILE_ID WAP_SVCLASS_ID
2013#define WAP_CLIENT_PROFILE_ID WAP_CLIENT_SVCLASS_ID
2014#define PANU_PROFILE_ID PANU_SVCLASS_ID
2015#define NAP_PROFILE_ID NAP_SVCLASS_ID
2016#define GN_PROFILE_ID GN_SVCLASS_ID
2017#define DIRECT_PRINTING_PROFILE_ID DIRECT_PRINTING_SVCLASS_ID
2018#define REFERENCE_PRINTING_PROFILE_ID REFERENCE_PRINTING_SVCLASS_ID
2019#define IMAGING_PROFILE_ID IMAGING_SVCLASS_ID
2020#define IMAGING_RESPONDER_PROFILE_ID IMAGING_RESPONDER_SVCLASS_ID
2021#define IMAGING_ARCHIVE_PROFILE_ID IMAGING_ARCHIVE_SVCLASS_ID
2022#define IMAGING_REFOBJS_PROFILE_ID IMAGING_REFOBJS_SVCLASS_ID
2023#define HANDSFREE_PROFILE_ID HANDSFREE_SVCLASS_ID
2024#define HANDSFREE_AGW_PROFILE_ID HANDSFREE_AGW_SVCLASS_ID
2025#define DIRECT_PRT_REFOBJS_PROFILE_ID DIRECT_PRT_REFOBJS_SVCLASS_ID
2026#define REFLECTED_UI_PROFILE_ID REFLECTED_UI_SVCLASS_ID
2027#define BASIC_PRINTING_PROFILE_ID BASIC_PRINTING_SVCLASS_ID
2028#define PRINTING_STATUS_PROFILE_ID PRINTING_STATUS_SVCLASS_ID
2029#define HID_PROFILE_ID HID_SVCLASS_ID
2030#define HCR_PROFILE_ID HCR_SCAN_SVCLASS_ID
2031#define HCR_PRINT_PROFILE_ID HCR_PRINT_SVCLASS_ID
2032#define HCR_SCAN_PROFILE_ID HCR_SCAN_SVCLASS_ID
2033#define CIP_PROFILE_ID CIP_SVCLASS_ID
2034#define VIDEO_CONF_GW_PROFILE_ID VIDEO_CONF_GW_SVCLASS_ID
2035#define UDI_MT_PROFILE_ID UDI_MT_SVCLASS_ID
2036#define UDI_TA_PROFILE_ID UDI_TA_SVCLASS_ID
2037#define AV_PROFILE_ID AV_SVCLASS_ID
2038#define SAP_PROFILE_ID SAP_SVCLASS_ID
2039#define PBAP_PCE_PROFILE_ID PBAP_PCE_SVCLASS_ID
2040#define PBAP_PSE_PROFILE_ID PBAP_PSE_SVCLASS_ID
2041#define PBAP_PROFILE_ID PBAP_SVCLASS_ID
2042#define PNP_INFO_PROFILE_ID PNP_INFO_SVCLASS_ID
2043#define GENERIC_NETWORKING_PROFILE_ID GENERIC_NETWORKING_SVCLASS_ID
2044#define GENERIC_FILETRANS_PROFILE_ID GENERIC_FILETRANS_SVCLASS_ID
2045#define GENERIC_AUDIO_PROFILE_ID GENERIC_AUDIO_SVCLASS_ID
2046#define GENERIC_TELEPHONY_PROFILE_ID GENERIC_TELEPHONY_SVCLASS_ID
2047#define UPNP_PROFILE_ID UPNP_SVCLASS_ID
2048#define UPNP_IP_PROFILE_ID UPNP_IP_SVCLASS_ID
2049#define UPNP_PAN_PROFILE_ID UPNP_PAN_SVCLASS_ID
2050#define UPNP_LAP_PROFILE_ID UPNP_LAP_SVCLASS_ID
2051#define UPNP_L2CAP_PROFILE_ID UPNP_L2CAP_SVCLASS_ID
2052#define VIDEO_SOURCE_PROFILE_ID VIDEO_SOURCE_SVCLASS_ID
2053#define VIDEO_SINK_PROFILE_ID VIDEO_SINK_SVCLASS_ID
2054#define VIDEO_DISTRIBUTION_PROFILE_ID VIDEO_DISTRIBUTION_SVCLASS_ID
2055#define MDP_PROFILE_ID MDP_SVCLASS_ID
2056#define MDP_SOURCE_PROFILE_ID MDP_SROUCE_SVCLASS_ID
2057#define MDP_SINK_PROFILE_ID MDP_SINK_SVCLASS_ID
2058#define APPLE_AGENT_PROFILE_ID APPLE_AGENT_SVCLASS_ID
2059
2060/* Data Representation */
2061enum bt_sdp_data_type {
2062 SDP_DTYPE_NIL = 0 << 3,
2063 SDP_DTYPE_UINT = 1 << 3,
2064 SDP_DTYPE_SINT = 2 << 3,
2065 SDP_DTYPE_UUID = 3 << 3,
2066 SDP_DTYPE_STRING = 4 << 3,
2067 SDP_DTYPE_BOOL = 5 << 3,
2068 SDP_DTYPE_SEQ = 6 << 3,
2069 SDP_DTYPE_ALT = 7 << 3,
2070 SDP_DTYPE_URL = 8 << 3,
2071};
2072
2073enum bt_sdp_data_size {
2074 SDP_DSIZE_1 = 0,
2075 SDP_DSIZE_2,
2076 SDP_DSIZE_4,
2077 SDP_DSIZE_8,
2078 SDP_DSIZE_16,
2079 SDP_DSIZE_NEXT1,
2080 SDP_DSIZE_NEXT2,
2081 SDP_DSIZE_NEXT4,
2082 SDP_DSIZE_MASK = SDP_DSIZE_NEXT4,
2083};
2084
2085enum bt_sdp_cmd {
2086 SDP_ERROR_RSP = 0x01,
2087 SDP_SVC_SEARCH_REQ = 0x02,
2088 SDP_SVC_SEARCH_RSP = 0x03,
2089 SDP_SVC_ATTR_REQ = 0x04,
2090 SDP_SVC_ATTR_RSP = 0x05,
2091 SDP_SVC_SEARCH_ATTR_REQ = 0x06,
2092 SDP_SVC_SEARCH_ATTR_RSP = 0x07,
2093};
2094
2095enum bt_sdp_errorcode {
2096 SDP_INVALID_VERSION = 0x0001,
2097 SDP_INVALID_RECORD_HANDLE = 0x0002,
2098 SDP_INVALID_SYNTAX = 0x0003,
2099 SDP_INVALID_PDU_SIZE = 0x0004,
2100 SDP_INVALID_CSTATE = 0x0005,
2101};
2102
2103/*
2104 * String identifiers are based on the SDP spec stating that
2105 * "base attribute id of the primary (universal) language must be 0x0100"
2106 *
2107 * Other languages should have their own offset; e.g.:
2108 * #define XXXLangBase yyyy
2109 * #define AttrServiceName_XXX 0x0000+XXXLangBase
2110 */
2111#define SDP_PRIMARY_LANG_BASE 0x0100
2112
2113enum bt_sdp_attribute_id {
2114 SDP_ATTR_RECORD_HANDLE = 0x0000,
2115 SDP_ATTR_SVCLASS_ID_LIST = 0x0001,
2116 SDP_ATTR_RECORD_STATE = 0x0002,
2117 SDP_ATTR_SERVICE_ID = 0x0003,
2118 SDP_ATTR_PROTO_DESC_LIST = 0x0004,
2119 SDP_ATTR_BROWSE_GRP_LIST = 0x0005,
2120 SDP_ATTR_LANG_BASE_ATTR_ID_LIST = 0x0006,
2121 SDP_ATTR_SVCINFO_TTL = 0x0007,
2122 SDP_ATTR_SERVICE_AVAILABILITY = 0x0008,
2123 SDP_ATTR_PFILE_DESC_LIST = 0x0009,
2124 SDP_ATTR_DOC_URL = 0x000a,
2125 SDP_ATTR_CLNT_EXEC_URL = 0x000b,
2126 SDP_ATTR_ICON_URL = 0x000c,
2127 SDP_ATTR_ADD_PROTO_DESC_LIST = 0x000d,
2128
2129 SDP_ATTR_SVCNAME_PRIMARY = SDP_PRIMARY_LANG_BASE + 0,
2130 SDP_ATTR_SVCDESC_PRIMARY = SDP_PRIMARY_LANG_BASE + 1,
2131 SDP_ATTR_SVCPROV_PRIMARY = SDP_PRIMARY_LANG_BASE + 2,
2132
2133 SDP_ATTR_GROUP_ID = 0x0200,
2134 SDP_ATTR_IP_SUBNET = 0x0200,
2135
2136 /* SDP */
2137 SDP_ATTR_VERSION_NUM_LIST = 0x0200,
2138 SDP_ATTR_SVCDB_STATE = 0x0201,
2139
2140 SDP_ATTR_SERVICE_VERSION = 0x0300,
2141 SDP_ATTR_EXTERNAL_NETWORK = 0x0301,
2142 SDP_ATTR_SUPPORTED_DATA_STORES_LIST = 0x0301,
2143 SDP_ATTR_FAX_CLASS1_SUPPORT = 0x0302,
2144 SDP_ATTR_REMOTE_AUDIO_VOLUME_CONTROL = 0x0302,
2145 SDP_ATTR_FAX_CLASS20_SUPPORT = 0x0303,
2146 SDP_ATTR_SUPPORTED_FORMATS_LIST = 0x0303,
2147 SDP_ATTR_FAX_CLASS2_SUPPORT = 0x0304,
2148 SDP_ATTR_AUDIO_FEEDBACK_SUPPORT = 0x0305,
2149 SDP_ATTR_NETWORK_ADDRESS = 0x0306,
2150 SDP_ATTR_WAP_GATEWAY = 0x0307,
2151 SDP_ATTR_HOMEPAGE_URL = 0x0308,
2152 SDP_ATTR_WAP_STACK_TYPE = 0x0309,
2153 SDP_ATTR_SECURITY_DESC = 0x030a,
2154 SDP_ATTR_NET_ACCESS_TYPE = 0x030b,
2155 SDP_ATTR_MAX_NET_ACCESSRATE = 0x030c,
2156 SDP_ATTR_IP4_SUBNET = 0x030d,
2157 SDP_ATTR_IP6_SUBNET = 0x030e,
2158 SDP_ATTR_SUPPORTED_CAPABILITIES = 0x0310,
2159 SDP_ATTR_SUPPORTED_FEATURES = 0x0311,
2160 SDP_ATTR_SUPPORTED_FUNCTIONS = 0x0312,
2161 SDP_ATTR_TOTAL_IMAGING_DATA_CAPACITY = 0x0313,
2162 SDP_ATTR_SUPPORTED_REPOSITORIES = 0x0314,
2163
2164 /* PnP Information */
2165 SDP_ATTR_SPECIFICATION_ID = 0x0200,
2166 SDP_ATTR_VENDOR_ID = 0x0201,
2167 SDP_ATTR_PRODUCT_ID = 0x0202,
2168 SDP_ATTR_VERSION = 0x0203,
2169 SDP_ATTR_PRIMARY_RECORD = 0x0204,
2170 SDP_ATTR_VENDOR_ID_SOURCE = 0x0205,
2171
2172 /* BT HID */
2173 SDP_ATTR_DEVICE_RELEASE_NUMBER = 0x0200,
2174 SDP_ATTR_PARSER_VERSION = 0x0201,
2175 SDP_ATTR_DEVICE_SUBCLASS = 0x0202,
2176 SDP_ATTR_COUNTRY_CODE = 0x0203,
2177 SDP_ATTR_VIRTUAL_CABLE = 0x0204,
2178 SDP_ATTR_RECONNECT_INITIATE = 0x0205,
2179 SDP_ATTR_DESCRIPTOR_LIST = 0x0206,
2180 SDP_ATTR_LANG_ID_BASE_LIST = 0x0207,
2181 SDP_ATTR_SDP_DISABLE = 0x0208,
2182 SDP_ATTR_BATTERY_POWER = 0x0209,
2183 SDP_ATTR_REMOTE_WAKEUP = 0x020a,
2184 SDP_ATTR_PROFILE_VERSION = 0x020b,
2185 SDP_ATTR_SUPERVISION_TIMEOUT = 0x020c,
2186 SDP_ATTR_NORMALLY_CONNECTABLE = 0x020d,
2187 SDP_ATTR_BOOT_DEVICE = 0x020e,
2188};
cb9c377f
PB		 2189
2190#endif
Empty description
This page took 0.777485 seconds and 4 git commands to generate.