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b5ea9327 AL |
1 | #ifndef QEMU_SMBUS_H |
2 | #define QEMU_SMBUS_H | |
3 | ||
3fffc223 TS |
4 | /* |
5 | * QEMU SMBus API | |
5fafdf24 | 6 | * |
3fffc223 | 7 | * Copyright (c) 2007 Arastra, Inc. |
5fafdf24 | 8 | * |
3fffc223 TS |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | */ | |
27 | ||
83c9f4ca | 28 | #include "hw/i2c.h" |
3fffc223 | 29 | |
b5ea9327 AL |
30 | #define TYPE_SMBUS_DEVICE "smbus-device" |
31 | #define SMBUS_DEVICE(obj) \ | |
32 | OBJECT_CHECK(SMBusDevice, (obj), TYPE_SMBUS_DEVICE) | |
33 | #define SMBUS_DEVICE_CLASS(klass) \ | |
34 | OBJECT_CLASS_CHECK(SMBusDeviceClass, (klass), TYPE_SMBUS_DEVICE) | |
35 | #define SMBUS_DEVICE_GET_CLASS(obj) \ | |
36 | OBJECT_GET_CLASS(SMBusDeviceClass, (obj), TYPE_SMBUS_DEVICE) | |
1ea96673 | 37 | |
b5ea9327 AL |
38 | typedef struct SMBusDeviceClass |
39 | { | |
40 | I2CSlaveClass parent_class; | |
81a322d4 | 41 | int (*init)(SMBusDevice *dev); |
3fffc223 TS |
42 | void (*quick_cmd)(SMBusDevice *dev, uint8_t read); |
43 | void (*send_byte)(SMBusDevice *dev, uint8_t val); | |
44 | uint8_t (*receive_byte)(SMBusDevice *dev); | |
0ff596d0 PB |
45 | /* We can't distinguish between a word write and a block write with |
46 | length 1, so pass the whole data block including the length byte | |
47 | (if present). The device is responsible figuring out what type of | |
48 | command this is. */ | |
49 | void (*write_data)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf, int len); | |
3f582262 | 50 | /* Likewise we can't distinguish between different reads, or even know |
0ff596d0 PB |
51 | the length of the read until the read is complete, so read data a |
52 | byte at a time. The device is responsible for adding the length | |
53 | byte on block reads. */ | |
54 | uint8_t (*read_data)(SMBusDevice *dev, uint8_t cmd, int n); | |
b5ea9327 | 55 | } SMBusDeviceClass; |
0ff596d0 | 56 | |
b5ea9327 AL |
57 | struct SMBusDevice { |
58 | /* The SMBus protocol is implemented on top of I2C. */ | |
59 | I2CSlave i2c; | |
60 | ||
61 | /* Remaining fields for internal use only. */ | |
62 | int mode; | |
63 | int data_len; | |
64 | uint8_t data_buf[34]; /* command + len + 32 bytes of data. */ | |
65 | uint8_t command; | |
66 | }; | |
67 | ||
0ff596d0 | 68 | /* Master device commands. */ |
5b7f5327 JQ |
69 | void smbus_quick_command(i2c_bus *bus, uint8_t addr, int read); |
70 | uint8_t smbus_receive_byte(i2c_bus *bus, uint8_t addr); | |
71 | void smbus_send_byte(i2c_bus *bus, uint8_t addr, uint8_t data); | |
72 | uint8_t smbus_read_byte(i2c_bus *bus, uint8_t addr, uint8_t command); | |
73 | void smbus_write_byte(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t data); | |
74 | uint16_t smbus_read_word(i2c_bus *bus, uint8_t addr, uint8_t command); | |
75 | void smbus_write_word(i2c_bus *bus, uint8_t addr, uint8_t command, uint16_t data); | |
76 | int smbus_read_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data); | |
77 | void smbus_write_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data, | |
0ff596d0 | 78 | int len); |
a88df0b9 IY |
79 | |
80 | void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom, | |
81 | const uint8_t *eeprom_spd, int size); | |
b5ea9327 AL |
82 | |
83 | #endif |