[qemu.git] / hw / ich9.h

#ifndef HW_ICH9_H
#define HW_ICH9_H

#include "hw/hw.h"
#include "qemu/range.h"
#include "hw/isa.h"
#include "hw/sysbus.h"
#include "hw/pc.h"
#include "hw/apm.h"
#include "hw/ioapic.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi.h"
#include "hw/acpi_ich9.h"
#include "hw/pam.h"
#include "hw/pci/pci_bus.h"

void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);

#define ICH9_CC_SIZE                            (16 * 1024)     /* 16KB */

#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
#define ICH9_LPC_DEVICE(obj) \
     OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)

typedef struct ICH9LPCState {
    /* ICH9 LPC PCI to ISA bridge */
    PCIDevice d;

    /* (pci device, intx) -> pirq
     * In real chipset case, the unused slots are never used
     * as ICH9 supports only D25-D32 irq routing.
     * On the other hand in qemu case, any slot/function can be populated
     * via command line option.
     * So fallback interrupt routing for any devices in any slots is necessary.
    */
    uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];

    APMState apm;
    ICH9LPCPMRegs pm;
    uint32_t sci_level; /* track sci level */

    /* 10.1 Chipset Configuration registers(Memory Space)
     which is pointed by RCBA */
    uint8_t chip_config[ICH9_CC_SIZE];

    /*
     * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
     *
     * register contents and IO memory region
     */
    uint8_t rst_cnt;
    MemoryRegion rst_cnt_mem;

    /* isa bus */
    ISABus *isa_bus;
    MemoryRegion rbca_mem;
    Notifier machine_ready;

    qemu_irq *pic;
    qemu_irq *ioapic;
} ICH9LPCState;

#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))

/* ICH9: Chipset Configuration Registers */
#define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)

#define ICH9_CC
#define ICH9_CC_D28IP                           0x310C
#define ICH9_CC_D28IP_SHIFT                     4
#define ICH9_CC_D28IP_MASK                      0xf
#define ICH9_CC_D28IP_DEFAULT                   0x00214321
#define ICH9_CC_D31IR                           0x3140
#define ICH9_CC_D30IR                           0x3142
#define ICH9_CC_D29IR                           0x3144
#define ICH9_CC_D28IR                           0x3146
#define ICH9_CC_D27IR                           0x3148
#define ICH9_CC_D26IR                           0x314C
#define ICH9_CC_D25IR                           0x3150
#define ICH9_CC_DIR_DEFAULT                     0x3210
#define ICH9_CC_D30IR_DEFAULT                   0x0
#define ICH9_CC_DIR_SHIFT                       4
#define ICH9_CC_DIR_MASK                        0x7
#define ICH9_CC_OIC                             0x31FF
#define ICH9_CC_OIC_AEN                         0x1

/* D28:F[0-5] */
#define ICH9_PCIE_DEV                           28
#define ICH9_PCIE_FUNC_MAX                      6


/* D29:F0 USB UHCI Controller #1 */
#define ICH9_USB_UHCI1_DEV                      29
#define ICH9_USB_UHCI1_FUNC                     0

/* D30:F0 DMI-to-PCI brdige */
#define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0

#define ICH9_D2P_BRIDGE_DEV                     30
#define ICH9_D2P_BRIDGE_FUNC                    0

#define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)

#define ICH9_D2P_A2_REVISION                    0x92

/* D31:F0 LPC Processor Interface */
#define ICH9_RST_CNT_IOPORT                     0xCF9

/* D31:F1 LPC controller */
#define ICH9_A2_LPC                             "ICH9 A2 LPC"
#define ICH9_A2_LPC_SAVEVM_VERSION              0

#define ICH9_LPC_DEV                            31
#define ICH9_LPC_FUNC                           0

#define ICH9_A2_LPC_REVISION                    0x2
#define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */

#define ICH9_LPC_PMBASE                         0x40
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE                     0x1
#define ICH9_LPC_PMBASE_DEFAULT                 0x1
#define ICH9_LPC_ACPI_CTRL                      0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_9                    0x0
#define ICH9_LPC_ACPI_CTRL_10                   0x1
#define ICH9_LPC_ACPI_CTRL_11                   0x2
#define ICH9_LPC_ACPI_CTRL_20                   0x4
#define ICH9_LPC_ACPI_CTRL_21                   0x5
#define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0

#define ICH9_LPC_PIRQA_ROUT                     0x60
#define ICH9_LPC_PIRQB_ROUT                     0x61
#define ICH9_LPC_PIRQC_ROUT                     0x62
#define ICH9_LPC_PIRQD_ROUT                     0x63

#define ICH9_LPC_PIRQE_ROUT                     0x68
#define ICH9_LPC_PIRQF_ROUT                     0x69
#define ICH9_LPC_PIRQG_ROUT                     0x6a
#define ICH9_LPC_PIRQH_ROUT                     0x6b

#define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
#define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80

#define ICH9_LPC_RCBA                           0xf0
#define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN                        0x1
#define ICH9_LPC_RCBA_DEFAULT                   0x0

#define ICH9_LPC_PIC_NUM_PINS                   16
#define ICH9_LPC_IOAPIC_NUM_PINS                24

/* D31:F2 SATA Controller #1 */
#define ICH9_SATA1_DEV                          31
#define ICH9_SATA1_FUNC                         2

/* D30:F1 power management I/O registers
   offset from the address ICH9_LPC_PMBASE */

/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
#define ICH9_PMIO_SIZE                          128
#define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)

#define ICH9_PMIO_PM1_STS                       0x00
#define ICH9_PMIO_PM1_EN                        0x02
#define ICH9_PMIO_PM1_CNT                       0x04
#define ICH9_PMIO_PM1_TMR                       0x08
#define ICH9_PMIO_GPE0_STS                      0x20
#define ICH9_PMIO_GPE0_EN                       0x28
#define ICH9_PMIO_GPE0_LEN                      16
#define ICH9_PMIO_SMI_EN                        0x30
#define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
#define ICH9_PMIO_SMI_STS                       0x34

/* FADT ACPI_ENABLE/ACPI_DISABLE */
#define ICH9_APM_ACPI_ENABLE                    0x2
#define ICH9_APM_ACPI_DISABLE                   0x3


/* D31:F3 SMBus controller */
#define ICH9_A2_SMB_REVISION                    0x02
#define ICH9_SMB_PI                             0x00

#define ICH9_SMB_SMBMBAR0                       0x10
#define ICH9_SMB_SMBMBAR1                       0x14
#define ICH9_SMB_SMBM_BAR                       0
#define ICH9_SMB_SMBM_SIZE                      (1 << 8)
#define ICH9_SMB_SMB_BASE                       0x20
#define ICH9_SMB_SMB_BASE_BAR                   4
#define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
#define ICH9_SMB_HOSTC                          0x40
#define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
#define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
#define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
#define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))

/* D31:F3 SMBus I/O and memory mapped I/O registers */
#define ICH9_SMB_DEV                            31
#define ICH9_SMB_FUNC                           3

#define ICH9_SMB_HST_STS                        0x00
#define ICH9_SMB_HST_CNT                        0x02
#define ICH9_SMB_HST_CMD                        0x03
#define ICH9_SMB_XMIT_SLVA                      0x04
#define ICH9_SMB_HST_D0                         0x05
#define ICH9_SMB_HST_D1                         0x06
#define ICH9_SMB_HOST_BLOCK_DB                  0x07

#endif /* HW_ICH9_H */
Commit	Line	Data
e516572f JB	1	#ifndef HW_ICH9_H
	2	#define HW_ICH9_H
	3
83c9f4ca	4	#include "hw/hw.h"
1de7afc9	5	#include "qemu/range.h"
83c9f4ca PB	6	#include "hw/isa.h"
	7	#include "hw/sysbus.h"
	8	#include "hw/pc.h"
	9	#include "hw/apm.h"
	10	#include "hw/ioapic.h"
	11	#include "hw/pci/pci.h"
	12	#include "hw/pci/pcie_host.h"
	13	#include "hw/pci/pci_bridge.h"
	14	#include "hw/acpi.h"
	15	#include "hw/acpi_ich9.h"
	16	#include "hw/pam.h"
	17	#include "hw/pci/pci_bus.h"
e516572f JB	18
	19	void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
	20	int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
91c3f2f0	21	PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
e516572f JB	22	void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
	23	PCIBus ich9_d2pbr_init(PCIBus bus, int devfn, int sec_bus);
	24	i2c_bus ich9_smb_init(PCIBus bus, int devfn, uint32_t smb_io_base);
	25
	26	#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
	27
	28	#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
	29	#define ICH9_LPC_DEVICE(obj) \
	30	OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
	31
	32	typedef struct ICH9LPCState {
	33	/* ICH9 LPC PCI to ISA bridge */
	34	PCIDevice d;
	35
	36	/* (pci device, intx) -> pirq
	37	* In real chipset case, the unused slots are never used
	38	* as ICH9 supports only D25-D32 irq routing.
	39	* On the other hand in qemu case, any slot/function can be populated
	40	* via command line option.
	41	* So fallback interrupt routing for any devices in any slots is necessary.
	42	*/
	43	uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
	44
	45	APMState apm;
	46	ICH9LPCPMRegs pm;
	47	uint32_t sci_level; /* track sci level */
	48
	49	/* 10.1 Chipset Configuration registers(Memory Space)
	50	which is pointed by RCBA */
	51	uint8_t chip_config[ICH9_CC_SIZE];
0e98b436 LE	52
	53	/*
	54	* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
	55	*
	56	* register contents and IO memory region
	57	*/
	58	uint8_t rst_cnt;
	59	MemoryRegion rst_cnt_mem;
	60
e516572f JB	61	/* isa bus */
	62	ISABus *isa_bus;
	63	MemoryRegion rbca_mem;
3f5bc9e8	64	Notifier machine_ready;
e516572f JB	65
	66	qemu_irq *pic;
	67	qemu_irq *ioapic;
	68	} ICH9LPCState;
	69
	70	#define Q35_MASK(bit, ms_bit, ls_bit) \
	71	((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
	72
	73	/* ICH9: Chipset Configuration Registers */
	74	#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
	75
	76	#define ICH9_CC
	77	#define ICH9_CC_D28IP 0x310C
	78	#define ICH9_CC_D28IP_SHIFT 4
	79	#define ICH9_CC_D28IP_MASK 0xf
	80	#define ICH9_CC_D28IP_DEFAULT 0x00214321
	81	#define ICH9_CC_D31IR 0x3140
	82	#define ICH9_CC_D30IR 0x3142
	83	#define ICH9_CC_D29IR 0x3144
	84	#define ICH9_CC_D28IR 0x3146
	85	#define ICH9_CC_D27IR 0x3148
	86	#define ICH9_CC_D26IR 0x314C
	87	#define ICH9_CC_D25IR 0x3150
	88	#define ICH9_CC_DIR_DEFAULT 0x3210
	89	#define ICH9_CC_D30IR_DEFAULT 0x0
	90	#define ICH9_CC_DIR_SHIFT 4
	91	#define ICH9_CC_DIR_MASK 0x7
	92	#define ICH9_CC_OIC 0x31FF
	93	#define ICH9_CC_OIC_AEN 0x1
	94
	95	/* D28:F[0-5] */
	96	#define ICH9_PCIE_DEV 28
	97	#define ICH9_PCIE_FUNC_MAX 6
	98
	99
	100	/* D29:F0 USB UHCI Controller #1 */
	101	#define ICH9_USB_UHCI1_DEV 29
	102	#define ICH9_USB_UHCI1_FUNC 0
	103
	104	/* D30:F0 DMI-to-PCI brdige */
	105	#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
	106	#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
	107
	108	#define ICH9_D2P_BRIDGE_DEV 30
	109	#define ICH9_D2P_BRIDGE_FUNC 0
	110
	111	#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
	112
	113	#define ICH9_D2P_A2_REVISION 0x92
	114
0e98b436 LE	115	/* D31:F0 LPC Processor Interface */
0e98b436 LE	116	#define ICH9_RST_CNT_IOPORT 0xCF9
e516572f JB	117
	118	/* D31:F1 LPC controller */
	119	#define ICH9_A2_LPC "ICH9 A2 LPC"
	120	#define ICH9_A2_LPC_SAVEVM_VERSION 0
	121
	122	#define ICH9_LPC_DEV 31
	123	#define ICH9_LPC_FUNC 0
	124
	125	#define ICH9_A2_LPC_REVISION 0x2
	126	#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
	127
	128	#define ICH9_LPC_PMBASE 0x40
	129	#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
	130	#define ICH9_LPC_PMBASE_RTE 0x1
	131	#define ICH9_LPC_PMBASE_DEFAULT 0x1
	132	#define ICH9_LPC_ACPI_CTRL 0x44
	133	#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
	134	#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
	135	#define ICH9_LPC_ACPI_CTRL_9 0x0
	136	#define ICH9_LPC_ACPI_CTRL_10 0x1
	137	#define ICH9_LPC_ACPI_CTRL_11 0x2
	138	#define ICH9_LPC_ACPI_CTRL_20 0x4
	139	#define ICH9_LPC_ACPI_CTRL_21 0x5
	140	#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
	141
	142	#define ICH9_LPC_PIRQA_ROUT 0x60
	143	#define ICH9_LPC_PIRQB_ROUT 0x61
	144	#define ICH9_LPC_PIRQC_ROUT 0x62
	145	#define ICH9_LPC_PIRQD_ROUT 0x63
	146
	147	#define ICH9_LPC_PIRQE_ROUT 0x68
	148	#define ICH9_LPC_PIRQF_ROUT 0x69
	149	#define ICH9_LPC_PIRQG_ROUT 0x6a
	150	#define ICH9_LPC_PIRQH_ROUT 0x6b
	151
	152	#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
	153	#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
	154	#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
	155
	156	#define ICH9_LPC_RCBA 0xf0
	157	#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
	158	#define ICH9_LPC_RCBA_EN 0x1
	159	#define ICH9_LPC_RCBA_DEFAULT 0x0
	160
	161	#define ICH9_LPC_PIC_NUM_PINS 16
	162	#define ICH9_LPC_IOAPIC_NUM_PINS 24
	163
	164	/* D31:F2 SATA Controller #1 */
	165	#define ICH9_SATA1_DEV 31
	166	#define ICH9_SATA1_FUNC 2
	167
	168	/* D30:F1 power management I/O registers
	169	offset from the address ICH9_LPC_PMBASE */
	170
	171	/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
	172	#define ICH9_PMIO_SIZE 128
	173	#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
	174
	175	#define ICH9_PMIO_PM1_STS 0x00
	176	#define ICH9_PMIO_PM1_EN 0x02
	177	#define ICH9_PMIO_PM1_CNT 0x04
	178	#define ICH9_PMIO_PM1_TMR 0x08
	179	#define ICH9_PMIO_GPE0_STS 0x20
	180	#define ICH9_PMIO_GPE0_EN 0x28
181	#define ICH9_PMIO_GPE0_LEN 16
182	#define ICH9_PMIO_SMI_EN 0x30
183	#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
184	#define ICH9_PMIO_SMI_STS 0x34
185
186	/* FADT ACPI_ENABLE/ACPI_DISABLE */
187	#define ICH9_APM_ACPI_ENABLE 0x2
188	#define ICH9_APM_ACPI_DISABLE 0x3
189
190
191	/* D31:F3 SMBus controller */
192	#define ICH9_A2_SMB_REVISION 0x02
193	#define ICH9_SMB_PI 0x00
194
195	#define ICH9_SMB_SMBMBAR0 0x10
196	#define ICH9_SMB_SMBMBAR1 0x14
197	#define ICH9_SMB_SMBM_BAR 0
198	#define ICH9_SMB_SMBM_SIZE (1 << 8)
199	#define ICH9_SMB_SMB_BASE 0x20
200	#define ICH9_SMB_SMB_BASE_BAR 4
201	#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
202	#define ICH9_SMB_HOSTC 0x40
203	#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
204	#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
205	#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
206	#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
207
208	/* D31:F3 SMBus I/O and memory mapped I/O registers */
209	#define ICH9_SMB_DEV 31
210	#define ICH9_SMB_FUNC 3
211
212	#define ICH9_SMB_HST_STS 0x00
213	#define ICH9_SMB_HST_CNT 0x02
214	#define ICH9_SMB_HST_CMD 0x03
215	#define ICH9_SMB_XMIT_SLVA 0x04
216	#define ICH9_SMB_HST_D0 0x05
217	#define ICH9_SMB_HST_D1 0x06
218	#define ICH9_SMB_HOST_BLOCK_DB 0x07
219
220	#endif /* HW_ICH9_H */