[qemu.git] / hw / ppce500_pci.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <[email protected]>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_ALL_SIZE      0x1000
#define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

struct PPCE500PCIState {
    PCIHostState pci_state;
    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    qemu_irq irq[4];
    /* mmio maps */
    int reg;
};

typedef struct PPCE500PCIState PPCE500PCIState;

static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        switch (addr & 0xC) {
        case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
        case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
        case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
        case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
        default: break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        switch (addr & 0xC) {
        case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
        case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
        case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
        case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
        default: break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
    &pci_reg_read4,
    &pci_reg_read4,
    &pci_reg_read4,
};

static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
                               uint32_t value)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        switch (addr & 0xC) {
        case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
        case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
        case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
        case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
        default: break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        switch (addr & 0xC) {
        case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
        case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
        case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
        case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
        default: break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
    &pci_reg_write4,
    &pci_reg_write4,
    &pci_reg_write4,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devno = pci_dev->devfn >> 3, ret = 0;

    switch (devno) {
        /* Two PCI slot */
        case 0x11:
        case 0x12:
            ret = (irq_num + devno - 0x10) % 4;
            break;
        default:
            printf("Error:%s:unknown dev number\n", __func__);
    }

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, irq_num, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);

    qemu_set_irq(pic[irq_num], level);
}

static const VMStateDescription vmstate_pci_outbound = {
    .name = "pci_outbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(potar, struct pci_outbound),
        VMSTATE_UINT32(potear, struct pci_outbound),
        VMSTATE_UINT32(powbar, struct pci_outbound),
        VMSTATE_UINT32(powar, struct pci_outbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_inbound = {
    .name = "pci_inbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(pitar, struct pci_inbound),
        VMSTATE_UINT32(piwbar, struct pci_inbound),
        VMSTATE_UINT32(piwbear, struct pci_inbound),
        VMSTATE_UINT32(piwar, struct pci_inbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppce500_pci = {
    .name = "ppce500_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
                             vmstate_pci_outbound, struct pci_outbound),
        VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
                             vmstate_pci_outbound, struct pci_inbound),
        VMSTATE_UINT32(gasket_time, PPCE500PCIState),
        VMSTATE_END_OF_LIST()
    }
};

static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
{
    PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
    PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);

    sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
    sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
    cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
                                 s->reg);
}

static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
{
    PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));

    sysbus_del_memory(dev, &h->conf_mem);
    sysbus_del_memory(dev, &h->data_mem);
    cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
                                 IO_MEM_UNASSIGNED);
}

#include "exec-memory.h"

static int e500_pcihost_initfn(SysBusDevice *dev)
{
    PCIHostState *h;
    PPCE500PCIState *s;
    PCIBus *b;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *address_space_io = get_system_io();

    h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
    s = DO_UPCAST(PPCE500PCIState, pci_state, h);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
                         mpc85xx_pci_map_irq, s->irq, address_space_mem,
                         address_space_io, PCI_DEVFN(0x11, 0), 4);
    s->pci_state.bus = b;

    pci_create_simple(b, 0, "e500-host-bridge");

    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
                                    DEVICE_BIG_ENDIAN);
    sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);

    return 0;
}

static PCIDeviceInfo e500_host_bridge_info = {
    .qdev.name    = "e500-host-bridge",
    .qdev.desc    = "Host bridge",
    .qdev.size    = sizeof(PCIDevice),
    .vendor_id    = PCI_VENDOR_ID_FREESCALE,
    .device_id    = PCI_DEVICE_ID_MPC8533E,
    .class_id     = PCI_CLASS_PROCESSOR_POWERPC,
};

static SysBusDeviceInfo e500_pcihost_info = {
    .init         = e500_pcihost_initfn,
    .qdev.name    = "e500-pcihost",
    .qdev.size    = sizeof(PPCE500PCIState),
    .qdev.vmsd    = &vmstate_ppce500_pci,
};

static void e500_pci_register(void)
{
    sysbus_register_withprop(&e500_pcihost_info);
    pci_qdev_register(&e500_host_bridge_info);
}
device_init(e500_pci_register);
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <[email protected]>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "hw.h"
74c62ba8 AJ	18	#include "pci.h"
	19	#include "pci_host.h"
	20	#include "bswap.h"
74c62ba8 AJ	21
74c62ba8 AJ	22	#ifdef DEBUG_PCI
001faf32	23	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	24	#else
001faf32	25	#define pci_debug(fmt, ...)
74c62ba8 AJ	26	#endif
	27
	28	#define PCIE500_CFGADDR 0x0
	29	#define PCIE500_CFGDATA 0x4
	30	#define PCIE500_REG_BASE 0xC00
be13cc7a AG	31	#define PCIE500_ALL_SIZE 0x1000
be13cc7a AG	32	#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
74c62ba8 AJ	33
	34	#define PPCE500_PCI_CONFIG_ADDR 0x0
	35	#define PPCE500_PCI_CONFIG_DATA 0x4
	36	#define PPCE500_PCI_INTACK 0x8
	37
	38	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	39	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	40	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	41	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	42	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	45
	46	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	47
	48	#define PCI_POTAR 0x0
	49	#define PCI_POTEAR 0x4
	50	#define PCI_POWBAR 0x8
	51	#define PCI_POWAR 0x10
	52
	53	#define PCI_PITAR 0x0
	54	#define PCI_PIWBAR 0x8
	55	#define PCI_PIWBEAR 0xC
	56	#define PCI_PIWAR 0x10
	57
	58	#define PPCE500_PCI_NR_POBS 5
	59	#define PPCE500_PCI_NR_PIBS 3
	60
	61	struct pci_outbound {
	62	uint32_t potar;
	63	uint32_t potear;
	64	uint32_t powbar;
	65	uint32_t powar;
	66	};
	67
	68	struct pci_inbound {
	69	uint32_t pitar;
	70	uint32_t piwbar;
	71	uint32_t piwbear;
	72	uint32_t piwar;
	73	};
	74
	75	struct PPCE500PCIState {
be13cc7a	76	PCIHostState pci_state;
74c62ba8 AJ	77	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	78	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	79	uint32_t gasket_time;
be13cc7a AG	80	qemu_irq irq[4];
be13cc7a AG	81	/* mmio maps */
be13cc7a	82	int reg;
74c62ba8 AJ	83	};
	84
	85	typedef struct PPCE500PCIState PPCE500PCIState;
	86
c227f099	87	static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
74c62ba8 AJ	88	{
	89	PPCE500PCIState *pci = opaque;
	90	unsigned long win;
	91	uint32_t value = 0;
	92
	93	win = addr & 0xfe0;
	94
	95	switch (win) {
	96	case PPCE500_PCI_OW1:
	97	case PPCE500_PCI_OW2:
	98	case PPCE500_PCI_OW3:
	99	case PPCE500_PCI_OW4:
	100	switch (addr & 0xC) {
	101	case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
	102	case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
	103	case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
	104	case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
	105	default: break;
	106	}
	107	break;
	108
	109	case PPCE500_PCI_IW3:
	110	case PPCE500_PCI_IW2:
	111	case PPCE500_PCI_IW1:
	112	switch (addr & 0xC) {
	113	case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
	114	case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
	115	case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
	116	case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
	117	default: break;
	118	};
	119	break;
	120
	121	case PPCE500_PCI_GASKET_TIMR:
	122	value = pci->gasket_time;
	123	break;
	124
	125	default:
	126	break;
	127	}
	128
c0a2a096 BS	129	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	130	win, addr, value);
74c62ba8 AJ	131	return value;
	132	}
	133
d60efc6b	134	static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
74c62ba8 AJ	135	&pci_reg_read4,
	136	&pci_reg_read4,
	137	&pci_reg_read4,
	138	};
	139
c227f099	140	static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
74c62ba8 AJ	141	uint32_t value)
	142	{
	143	PPCE500PCIState *pci = opaque;
	144	unsigned long win;
	145
	146	win = addr & 0xfe0;
	147
c0a2a096 BS	148	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
c0a2a096 BS	149	__func__, value, win, addr);
74c62ba8 AJ	150
	151	switch (win) {
	152	case PPCE500_PCI_OW1:
	153	case PPCE500_PCI_OW2:
	154	case PPCE500_PCI_OW3:
	155	case PPCE500_PCI_OW4:
	156	switch (addr & 0xC) {
	157	case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
	158	case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
	159	case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
	160	case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
	161	default: break;
	162	};
	163	break;
	164
	165	case PPCE500_PCI_IW3:
	166	case PPCE500_PCI_IW2:
	167	case PPCE500_PCI_IW1:
	168	switch (addr & 0xC) {
	169	case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
	170	case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
	171	case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
	172	case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
	173	default: break;
	174	};
	175	break;
	176
	177	case PPCE500_PCI_GASKET_TIMR:
	178	pci->gasket_time = value;
	179	break;
	180
	181	default:
	182	break;
	183	};
	184	}
	185
d60efc6b	186	static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
74c62ba8 AJ	187	&pci_reg_write4,
	188	&pci_reg_write4,
	189	&pci_reg_write4,
	190	};
	191
	192	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	193	{
	194	int devno = pci_dev->devfn >> 3, ret = 0;
	195
	196	switch (devno) {
	197	/* Two PCI slot */
	198	case 0x11:
	199	case 0x12:
	200	ret = (irq_num + devno - 0x10) % 4;
	201	break;
	202	default:
72b310e9	203	printf("Error:%s:unknown dev number\n", __func__);
74c62ba8 AJ	204	}
	205
	206	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
	207	pci_dev->devfn, irq_num, ret, devno);
	208
	209	return ret;
	210	}
	211
5d4e84c8	212	static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8	213	{
5d4e84c8 JQ	214	qemu_irq *pic = opaque;
5d4e84c8 JQ	215
74c62ba8 AJ	216	pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
	217
	218	qemu_set_irq(pic[irq_num], level);
	219	}
	220
e0433ecc JQ	221	static const VMStateDescription vmstate_pci_outbound = {
	222	.name = "pci_outbound",
	223	.version_id = 0,
	224	.minimum_version_id = 0,
	225	.minimum_version_id_old = 0,
	226	.fields = (VMStateField[]) {
	227	VMSTATE_UINT32(potar, struct pci_outbound),
	228	VMSTATE_UINT32(potear, struct pci_outbound),
	229	VMSTATE_UINT32(powbar, struct pci_outbound),
	230	VMSTATE_UINT32(powar, struct pci_outbound),
	231	VMSTATE_END_OF_LIST()
74c62ba8	232	}
e0433ecc	233	};
74c62ba8	234
e0433ecc JQ	235	static const VMStateDescription vmstate_pci_inbound = {
	236	.name = "pci_inbound",
	237	.version_id = 0,
	238	.minimum_version_id = 0,
	239	.minimum_version_id_old = 0,
	240	.fields = (VMStateField[]) {
	241	VMSTATE_UINT32(pitar, struct pci_inbound),
	242	VMSTATE_UINT32(piwbar, struct pci_inbound),
	243	VMSTATE_UINT32(piwbear, struct pci_inbound),
	244	VMSTATE_UINT32(piwar, struct pci_inbound),
	245	VMSTATE_END_OF_LIST()
74c62ba8	246	}
e0433ecc	247	};
74c62ba8	248
e0433ecc JQ	249	static const VMStateDescription vmstate_ppce500_pci = {
	250	.name = "ppce500_pci",
	251	.version_id = 1,
	252	.minimum_version_id = 1,
	253	.minimum_version_id_old = 1,
	254	.fields = (VMStateField[]) {
e0433ecc JQ	255	VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
	256	vmstate_pci_outbound, struct pci_outbound),
	257	VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
	258	vmstate_pci_outbound, struct pci_inbound),
	259	VMSTATE_UINT32(gasket_time, PPCE500PCIState),
	260	VMSTATE_END_OF_LIST()
74c62ba8	261	}
e0433ecc	262	};
74c62ba8	263
be13cc7a AG	264	static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
	265	{
	266	PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
	267	PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
	268
d0ed8076 AK	269	sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
d0ed8076 AK	270	sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
be13cc7a AG	271	cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
	272	s->reg);
	273	}
	274
cd0fa1e6 AK	275	static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
cd0fa1e6 AK	276	{
d0ed8076 AK	277	PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
	278
	279	sysbus_del_memory(dev, &h->conf_mem);
	280	sysbus_del_memory(dev, &h->data_mem);
cd0fa1e6 AK	281	cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
	282	IO_MEM_UNASSIGNED);
	283	}
	284
1e39101c AK	285	#include "exec-memory.h"
1e39101c AK	286
be13cc7a AG	287	static int e500_pcihost_initfn(SysBusDevice *dev)
	288	{
	289	PCIHostState *h;
	290	PPCE500PCIState *s;
	291	PCIBus *b;
	292	int i;
aee97b84 AK	293	MemoryRegion *address_space_mem = get_system_memory();
aee97b84 AK	294	MemoryRegion *address_space_io = get_system_io();
be13cc7a AG	295
	296	h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
	297	s = DO_UPCAST(PPCE500PCIState, pci_state, h);
	298
	299	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	300	sysbus_init_irq(dev, &s->irq[i]);
	301	}
	302
	303	b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
aee97b84 AK	304	mpc85xx_pci_map_irq, s->irq, address_space_mem,
aee97b84 AK	305	address_space_io, PCI_DEVFN(0x11, 0), 4);
be13cc7a AG	306	s->pci_state.bus = b;
	307
	308	pci_create_simple(b, 0, "e500-host-bridge");
	309
d0ed8076 AK	310	memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
	311	"pci-conf-idx", 4);
	312	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
	313	"pci-conf-data", 4);
be13cc7a AG	314	s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
be13cc7a AG	315	DEVICE_BIG_ENDIAN);
cd0fa1e6	316	sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
be13cc7a AG	317
	318	return 0;
	319	}
	320
be13cc7a AG	321	static PCIDeviceInfo e500_host_bridge_info = {
	322	.qdev.name = "e500-host-bridge",
	323	.qdev.desc = "Host bridge",
	324	.qdev.size = sizeof(PCIDevice),
cdfdec7f MT	325	.vendor_id = PCI_VENDOR_ID_FREESCALE,
	326	.device_id = PCI_DEVICE_ID_MPC8533E,
	327	.class_id = PCI_CLASS_PROCESSOR_POWERPC,
be13cc7a AG	328	};
	329
	330	static SysBusDeviceInfo e500_pcihost_info = {
	331	.init = e500_pcihost_initfn,
	332	.qdev.name = "e500-pcihost",
	333	.qdev.size = sizeof(PPCE500PCIState),
	334	.qdev.vmsd = &vmstate_ppce500_pci,
	335	};
	336
	337	static void e500_pci_register(void)
74c62ba8	338	{
be13cc7a AG	339	sysbus_register_withprop(&e500_pcihost_info);
be13cc7a AG	340	pci_qdev_register(&e500_host_bridge_info);
74c62ba8	341	}
be13cc7a	342	device_init(e500_pci_register);