[qemu.git] / hw / a9mpcore.c

/*
 * Cortex-A9MPCore internal peripheral emulation.
 *
 * Copyright (c) 2009 CodeSourcery.
 * Copyright (c) 2011 Linaro Limited.
 * Written by Paul Brook, Peter Maydell.
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"

#include "arm_gic.c"

/* A9MP private memory region.  */

typedef struct a9mp_priv_state {
    gic_state gic;
    uint32_t scu_control;
    uint32_t scu_status;
    uint32_t old_timer_status[8];
    uint32_t num_cpu;
    qemu_irq *timer_irq;
    MemoryRegion scu_iomem;
    MemoryRegion ptimer_iomem;
    MemoryRegion container;
    DeviceState *mptimer;
    uint32_t num_irq;
} a9mp_priv_state;

static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
                            unsigned size)
{
    a9mp_priv_state *s = (a9mp_priv_state *)opaque;
    switch (offset) {
    case 0x00: /* Control */
        return s->scu_control;
    case 0x04: /* Configuration */
        return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
    case 0x08: /* CPU Power Status */
        return s->scu_status;
    case 0x09: /* CPU status.  */
        return s->scu_status >> 8;
    case 0x0a: /* CPU status.  */
        return s->scu_status >> 16;
    case 0x0b: /* CPU status.  */
        return s->scu_status >> 24;
    case 0x0c: /* Invalidate All Registers In Secure State */
        return 0;
    case 0x40: /* Filtering Start Address Register */
    case 0x44: /* Filtering End Address Register */
        /* RAZ/WI, like an implementation with only one AXI master */
        return 0;
    case 0x50: /* SCU Access Control Register */
    case 0x54: /* SCU Non-secure Access Control Register */
        /* unimplemented, fall through */
    default:
        return 0;
    }
}

static void a9_scu_write(void *opaque, target_phys_addr_t offset,
                         uint64_t value, unsigned size)
{
    a9mp_priv_state *s = (a9mp_priv_state *)opaque;
    uint32_t mask;
    uint32_t shift;
    switch (size) {
    case 1:
        mask = 0xff;
        break;
    case 2:
        mask = 0xffff;
        break;
    case 4:
        mask = 0xffffffff;
        break;
    default:
        fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
                size, offset);
        return;
    }

    switch (offset) {
    case 0x00: /* Control */
        s->scu_control = value & 1;
        break;
    case 0x4: /* Configuration: RO */
        break;
    case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
        shift = (offset - 0x8) * 8;
        s->scu_status &= ~(mask << shift);
        s->scu_status |= ((value & mask) << shift);
        break;
    case 0x0c: /* Invalidate All Registers In Secure State */
        /* no-op as we do not implement caches */
        break;
    case 0x40: /* Filtering Start Address Register */
    case 0x44: /* Filtering End Address Register */
        /* RAZ/WI, like an implementation with only one AXI master */
        break;
    case 0x50: /* SCU Access Control Register */
    case 0x54: /* SCU Non-secure Access Control Register */
        /* unimplemented, fall through */
    default:
        break;
    }
}

static const MemoryRegionOps a9_scu_ops = {
    .read = a9_scu_read,
    .write = a9_scu_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void a9mpcore_timer_irq_handler(void *opaque, int irq, int level)
{
    a9mp_priv_state *s = (a9mp_priv_state *)opaque;
    if (level && !s->old_timer_status[irq]) {
        gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
    }
    s->old_timer_status[irq] = level;
}

static void a9mp_priv_reset(DeviceState *dev)
{
    a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, sysbus_from_qdev(dev));
    int i;
    s->scu_control = 0;
    for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) {
        s->old_timer_status[i] = 0;
    }
}

static int a9mp_priv_init(SysBusDevice *dev)
{
    a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, dev);
    SysBusDevice *busdev;
    int i;

    gic_init(&s->gic, s->num_cpu, s->num_irq);

    s->mptimer = qdev_create(NULL, "arm_mptimer");
    qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
    qdev_init_nofail(s->mptimer);
    busdev = sysbus_from_qdev(s->mptimer);

    /* Memory map (addresses are offsets from PERIPHBASE):
     *  0x0000-0x00ff -- Snoop Control Unit
     *  0x0100-0x01ff -- GIC CPU interface
     *  0x0200-0x02ff -- Global Timer
     *  0x0300-0x05ff -- nothing
     *  0x0600-0x06ff -- private timers and watchdogs
     *  0x0700-0x0fff -- nothing
     *  0x1000-0x1fff -- GIC Distributor
     *
     * We should implement the global timer but don't currently do so.
     */
    memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
    memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100);
    memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
    /* GIC CPU interface */
    memory_region_add_subregion(&s->container, 0x100, &s->gic.cpuiomem[0]);
    /* Note that the A9 exposes only the "timer/watchdog for this core"
     * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
     */
    memory_region_add_subregion(&s->container, 0x600,
                                sysbus_mmio_get_region(busdev, 0));
    memory_region_add_subregion(&s->container, 0x620,
                                sysbus_mmio_get_region(busdev, 1));
    memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);

    sysbus_init_mmio(dev, &s->container);

    /* Wire up the interrupt from each watchdog and timer. */
    s->timer_irq = qemu_allocate_irqs(a9mpcore_timer_irq_handler,
                                      s, (s->num_cpu + 1) * 2);
    for (i = 0; i < s->num_cpu * 2; i++) {
        sysbus_connect_irq(busdev, i, s->timer_irq[i]);
    }
    return 0;
}

static const VMStateDescription vmstate_a9mp_priv = {
    .name = "a9mpcore_priv",
    .version_id = 2,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(scu_control, a9mp_priv_state),
        VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
        VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
        VMSTATE_END_OF_LIST()
    }
};

static Property a9mp_priv_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
    /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
     * IRQ lines (with another 32 internal). We default to 64+32, which
     * is the number provided by the Cortex-A9MP test chip in the
     * Realview PBX-A9 and Versatile Express A9 development boards.
     * Other boards may differ and should set this property appropriately.
     */
    DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
    DEFINE_PROP_END_OF_LIST(),
};

static void a9mp_priv_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = a9mp_priv_init;
    dc->props = a9mp_priv_properties;
    dc->vmsd = &vmstate_a9mp_priv;
    dc->reset = a9mp_priv_reset;
}

static TypeInfo a9mp_priv_info = {
    .name          = "a9mpcore_priv",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(a9mp_priv_state),
    .class_init    = a9mp_priv_class_init,
};

static void a9mp_register_types(void)
{
    type_register_static(&a9mp_priv_info);
}

type_init(a9mp_register_types)
Commit	Line	Data
f7c70325 PB	1	/*
	2	* Cortex-A9MPCore internal peripheral emulation.
	3	*
	4	* Copyright (c) 2009 CodeSourcery.
b12080cd PM	5	* Copyright (c) 2011 Linaro Limited.
b12080cd PM	6	* Written by Paul Brook, Peter Maydell.
f7c70325	7	*
8e31bf38	8	* This code is licensed under the GPL.
f7c70325 PB	9	*/
f7c70325 PB	10
b12080cd PM	11	#include "sysbus.h"
b12080cd PM	12
b12080cd PM	13	#include "arm_gic.c"
	14
	15	/* A9MP private memory region. */
	16
	17	typedef struct a9mp_priv_state {
	18	gic_state gic;
	19	uint32_t scu_control;
78aca8a7	20	uint32_t scu_status;
b12080cd PM	21	uint32_t old_timer_status[8];
	22	uint32_t num_cpu;
	23	qemu_irq *timer_irq;
	24	MemoryRegion scu_iomem;
	25	MemoryRegion ptimer_iomem;
	26	MemoryRegion container;
	27	DeviceState *mptimer;
a32134aa	28	uint32_t num_irq;
b12080cd PM	29	} a9mp_priv_state;
	30
	31	static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
	32	unsigned size)
	33	{
	34	a9mp_priv_state s = (a9mp_priv_state )opaque;
	35	switch (offset) {
	36	case 0x00: /* Control */
	37	return s->scu_control;
	38	case 0x04: /* Configuration */
	39	return (((1 << s->num_cpu) - 1) << 4) \| (s->num_cpu - 1);
	40	case 0x08: /* CPU Power Status */
78aca8a7 RH	41	return s->scu_status;
	42	case 0x09: /* CPU status. */
	43	return s->scu_status >> 8;
	44	case 0x0a: /* CPU status. */
	45	return s->scu_status >> 16;
	46	case 0x0b: /* CPU status. */
	47	return s->scu_status >> 24;
b12080cd PM	48	case 0x0c: /* Invalidate All Registers In Secure State */
	49	return 0;
	50	case 0x40: /* Filtering Start Address Register */
	51	case 0x44: /* Filtering End Address Register */
	52	/* RAZ/WI, like an implementation with only one AXI master */
	53	return 0;
	54	case 0x50: /* SCU Access Control Register */
	55	case 0x54: /* SCU Non-secure Access Control Register */
	56	/* unimplemented, fall through */
	57	default:
	58	return 0;
	59	}
	60	}
	61
	62	static void a9_scu_write(void *opaque, target_phys_addr_t offset,
	63	uint64_t value, unsigned size)
	64	{
	65	a9mp_priv_state s = (a9mp_priv_state )opaque;
78aca8a7 RH	66	uint32_t mask;
	67	uint32_t shift;
	68	switch (size) {
	69	case 1:
	70	mask = 0xff;
	71	break;
	72	case 2:
	73	mask = 0xffff;
	74	break;
	75	case 4:
	76	mask = 0xffffffff;
	77	break;
	78	default:
	79	fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
	80	size, offset);
	81	return;
	82	}
	83
b12080cd PM	84	switch (offset) {
	85	case 0x00: /* Control */
	86	s->scu_control = value & 1;
	87	break;
	88	case 0x4: /* Configuration: RO */
	89	break;
78aca8a7 RH	90	case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
	91	shift = (offset - 0x8) * 8;
	92	s->scu_status &= ~(mask << shift);
	93	s->scu_status \|= ((value & mask) << shift);
	94	break;
b12080cd PM	95	case 0x0c: /* Invalidate All Registers In Secure State */
	96	/* no-op as we do not implement caches */
	97	break;
	98	case 0x40: /* Filtering Start Address Register */
	99	case 0x44: /* Filtering End Address Register */
	100	/* RAZ/WI, like an implementation with only one AXI master */
	101	break;
b12080cd PM	102	case 0x50: /* SCU Access Control Register */
	103	case 0x54: /* SCU Non-secure Access Control Register */
	104	/* unimplemented, fall through */
	105	default:
	106	break;
	107	}
	108	}
	109
	110	static const MemoryRegionOps a9_scu_ops = {
	111	.read = a9_scu_read,
	112	.write = a9_scu_write,
	113	.endianness = DEVICE_NATIVE_ENDIAN,
	114	};
	115
	116	static void a9mpcore_timer_irq_handler(void *opaque, int irq, int level)
	117	{
	118	a9mp_priv_state s = (a9mp_priv_state )opaque;
	119	if (level && !s->old_timer_status[irq]) {
	120	gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
	121	}
	122	s->old_timer_status[irq] = level;
	123	}
	124
	125	static void a9mp_priv_reset(DeviceState *dev)
	126	{
	127	a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, sysbus_from_qdev(dev));
	128	int i;
	129	s->scu_control = 0;
	130	for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) {
	131	s->old_timer_status[i] = 0;
	132	}
	133	}
	134
	135	static int a9mp_priv_init(SysBusDevice *dev)
	136	{
	137	a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, dev);
	138	SysBusDevice *busdev;
	139	int i;
	140
a32134aa	141	gic_init(&s->gic, s->num_cpu, s->num_irq);
b12080cd PM	142
	143	s->mptimer = qdev_create(NULL, "arm_mptimer");
	144	qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
	145	qdev_init_nofail(s->mptimer);
	146	busdev = sysbus_from_qdev(s->mptimer);
	147
	148	/* Memory map (addresses are offsets from PERIPHBASE):
	149	* 0x0000-0x00ff -- Snoop Control Unit
	150	* 0x0100-0x01ff -- GIC CPU interface
	151	* 0x0200-0x02ff -- Global Timer
	152	* 0x0300-0x05ff -- nothing
	153	* 0x0600-0x06ff -- private timers and watchdogs
	154	* 0x0700-0x0fff -- nothing
	155	* 0x1000-0x1fff -- GIC Distributor
	156	*
	157	* We should implement the global timer but don't currently do so.
	158	*/
	159	memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
	160	memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100);
	161	memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
	162	/* GIC CPU interface */
	163	memory_region_add_subregion(&s->container, 0x100, &s->gic.cpuiomem[0]);
	164	/* Note that the A9 exposes only the "timer/watchdog for this core"
	165	* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
	166	*/
	167	memory_region_add_subregion(&s->container, 0x600,
	168	sysbus_mmio_get_region(busdev, 0));
	169	memory_region_add_subregion(&s->container, 0x620,
	170	sysbus_mmio_get_region(busdev, 1));
	171	memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
	172
	173	sysbus_init_mmio(dev, &s->container);
	174
	175	/* Wire up the interrupt from each watchdog and timer. */
	176	s->timer_irq = qemu_allocate_irqs(a9mpcore_timer_irq_handler,
	177	s, (s->num_cpu + 1) * 2);
	178	for (i = 0; i < s->num_cpu * 2; i++) {
	179	sysbus_connect_irq(busdev, i, s->timer_irq[i]);
	180	}
	181	return 0;
	182	}
	183
	184	static const VMStateDescription vmstate_a9mp_priv = {
	185	.name = "a9mpcore_priv",
78aca8a7	186	.version_id = 2,
b12080cd PM	187	.minimum_version_id = 1,
	188	.fields = (VMStateField[]) {
	189	VMSTATE_UINT32(scu_control, a9mp_priv_state),
	190	VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
78aca8a7	191	VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
b12080cd PM	192	VMSTATE_END_OF_LIST()
	193	}
	194	};
f7c70325	195
39bffca2 AL	196	static Property a9mp_priv_properties[] = {
	197	DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
	198	/* The Cortex-A9MP may have anything from 0 to 224 external interrupt
	199	* IRQ lines (with another 32 internal). We default to 64+32, which
	200	* is the number provided by the Cortex-A9MP test chip in the
	201	* Realview PBX-A9 and Versatile Express A9 development boards.
	202	* Other boards may differ and should set this property appropriately.
	203	*/
	204	DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
	205	DEFINE_PROP_END_OF_LIST(),
	206	};
	207
999e12bb AL	208	static void a9mp_priv_class_init(ObjectClass klass, void data)
999e12bb AL	209	{
39bffca2	210	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	211	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	212
	213	k->init = a9mp_priv_init;
39bffca2 AL	214	dc->props = a9mp_priv_properties;
	215	dc->vmsd = &vmstate_a9mp_priv;
	216	dc->reset = a9mp_priv_reset;
999e12bb AL	217	}
999e12bb AL	218
39bffca2 AL	219	static TypeInfo a9mp_priv_info = {
	220	.name = "a9mpcore_priv",
	221	.parent = TYPE_SYS_BUS_DEVICE,
	222	.instance_size = sizeof(a9mp_priv_state),
	223	.class_init = a9mp_priv_class_init,
f7c70325 PB	224	};
f7c70325 PB	225
83f7d43a	226	static void a9mp_register_types(void)
f7c70325	227	{
39bffca2	228	type_register_static(&a9mp_priv_info);
f7c70325 PB	229	}
f7c70325 PB	230
83f7d43a	231	type_init(a9mp_register_types)