[qemu.git] / hw / input / pckbd.c

/*
 * QEMU PC keyboard emulation
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "hw/input/ps2.h"
#include "hw/irq.h"
#include "hw/input/i8042.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"

#include "trace.h"

/*	Keyboard Controller Commands */
#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
#define KBD_CCMD_READ_INPORT    0xC0    /* read input port */
#define KBD_CCMD_READ_OUTPORT	0xD0    /* read output port */
#define KBD_CCMD_WRITE_OUTPORT	0xD1    /* write output port */
#define KBD_CCMD_WRITE_OBUF	0xD2
#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
                                           initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
#define KBD_CCMD_DISABLE_A20    0xDD    /* HP vectra only ? */
#define KBD_CCMD_ENABLE_A20     0xDF    /* HP vectra only ? */
#define KBD_CCMD_PULSE_BITS_3_0 0xF0    /* Pulse bits 3-0 of the output port P2. */
#define KBD_CCMD_RESET          0xFE    /* Pulse bit 0 of the output port P2 = CPU reset. */
#define KBD_CCMD_NO_OP          0xFF    /* Pulse no bits of the output port P2. */

/* Keyboard Commands */
#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
#define KBD_CMD_ECHO     	0xEE
#define KBD_CMD_GET_ID 	        0xF2	/* get keyboard ID */
#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
#define KBD_CMD_RESET_DISABLE	0xF5	/* reset and disable scanning */
#define KBD_CMD_RESET_ENABLE   	0xF6    /* reset and enable scanning */
#define KBD_CMD_RESET		0xFF	/* Reset */

/* Keyboard Replies */
#define KBD_REPLY_POR		0xAA	/* Power on reset */
#define KBD_REPLY_ACK		0xFA	/* Command ACK */
#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */

/* Status Register Bits */
#define KBD_STAT_OBF 		0x01	/* Keyboard output buffer full */
#define KBD_STAT_IBF 		0x02	/* Keyboard input buffer full */
#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
#define KBD_STAT_GTO 		0x40	/* General receive/xmit timeout */
#define KBD_STAT_PERR 		0x80	/* Parity error */

/* Controller Mode Register Bits */
#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 		0x04	/* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
#define KBD_MODE_KCC 		0x40	/* Scan code conversion to PC format */
#define KBD_MODE_RFU		0x80

/* Output Port Bits */
#define KBD_OUT_RESET           0x01    /* 1=normal mode, 0=reset */
#define KBD_OUT_A20             0x02    /* x86 only */
#define KBD_OUT_OBF             0x10    /* Keyboard output buffer full */
#define KBD_OUT_MOUSE_OBF       0x20    /* Mouse output buffer full */

/* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
 * We make the default value of the outport include these four bits,
 * so that the subsection is rarely necessary.
 */
#define KBD_OUT_ONES            0xcc

/* Mouse Commands */
#define AUX_SET_SCALE11		0xE6	/* Set 1:1 scaling */
#define AUX_SET_SCALE21		0xE7	/* Set 2:1 scaling */
#define AUX_SET_RES		0xE8	/* Set resolution */
#define AUX_GET_SCALE		0xE9	/* Get scaling factor */
#define AUX_SET_STREAM		0xEA	/* Set stream mode */
#define AUX_POLL		0xEB	/* Poll */
#define AUX_RESET_WRAP		0xEC	/* Reset wrap mode */
#define AUX_SET_WRAP		0xEE	/* Set wrap mode */
#define AUX_SET_REMOTE		0xF0	/* Set remote mode */
#define AUX_GET_TYPE		0xF2	/* Get type */
#define AUX_SET_SAMPLE		0xF3	/* Set sample rate */
#define AUX_ENABLE_DEV		0xF4	/* Enable aux device */
#define AUX_DISABLE_DEV		0xF5	/* Disable aux device */
#define AUX_SET_DEFAULT		0xF6
#define AUX_RESET		0xFF	/* Reset aux device */
#define AUX_ACK			0xFA	/* Command byte ACK. */

#define MOUSE_STATUS_REMOTE     0x40
#define MOUSE_STATUS_ENABLED    0x20
#define MOUSE_STATUS_SCALE21    0x10

#define KBD_PENDING_KBD         1
#define KBD_PENDING_AUX         2

typedef struct KBDState {
    uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
    uint8_t status;
    uint8_t mode;
    uint8_t outport;
    bool outport_present;
    /* Bitmask of devices with data available.  */
    uint8_t pending;
    void *kbd;
    void *mouse;

    qemu_irq irq_kbd;
    qemu_irq irq_mouse;
    qemu_irq a20_out;
    hwaddr mask;
} KBDState;

/* update irq and KBD_STAT_[MOUSE_]OBF */
/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
   incorrect, but it avoids having to simulate exact delays */
static void kbd_update_irq(KBDState *s)
{
    int irq_kbd_level, irq_mouse_level;

    irq_kbd_level = 0;
    irq_mouse_level = 0;
    s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
    s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
    if (s->pending) {
        s->status |= KBD_STAT_OBF;
        s->outport |= KBD_OUT_OBF;
        /* kbd data takes priority over aux data.  */
        if (s->pending == KBD_PENDING_AUX) {
            s->status |= KBD_STAT_MOUSE_OBF;
            s->outport |= KBD_OUT_MOUSE_OBF;
            if (s->mode & KBD_MODE_MOUSE_INT)
                irq_mouse_level = 1;
        } else {
            if ((s->mode & KBD_MODE_KBD_INT) &&
                !(s->mode & KBD_MODE_DISABLE_KBD))
                irq_kbd_level = 1;
        }
    }
    qemu_set_irq(s->irq_kbd, irq_kbd_level);
    qemu_set_irq(s->irq_mouse, irq_mouse_level);
}

static void kbd_update_kbd_irq(void *opaque, int level)
{
    KBDState *s = (KBDState *)opaque;

    if (level)
        s->pending |= KBD_PENDING_KBD;
    else
        s->pending &= ~KBD_PENDING_KBD;
    kbd_update_irq(s);
}

static void kbd_update_aux_irq(void *opaque, int level)
{
    KBDState *s = (KBDState *)opaque;

    if (level)
        s->pending |= KBD_PENDING_AUX;
    else
        s->pending &= ~KBD_PENDING_AUX;
    kbd_update_irq(s);
}

static uint64_t kbd_read_status(void *opaque, hwaddr addr,
                                unsigned size)
{
    KBDState *s = opaque;
    int val;
    val = s->status;
    trace_pckbd_kbd_read_status(val);
    return val;
}

static void kbd_queue(KBDState *s, int b, int aux)
{
    if (aux)
        ps2_queue(s->mouse, b);
    else
        ps2_queue(s->kbd, b);
}

static void outport_write(KBDState *s, uint32_t val)
{
    trace_pckbd_outport_write(val);
    s->outport = val;
    qemu_set_irq(s->a20_out, (val >> 1) & 1);
    if (!(val & 1)) {
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
    }
}

static void kbd_write_command(void *opaque, hwaddr addr,
                              uint64_t val, unsigned size)
{
    KBDState *s = opaque;

    trace_pckbd_kbd_write_command(val);

    /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
     * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
     * command specify the output port bits to be pulsed.
     * 0: Bit should be pulsed. 1: Bit should not be modified.
     * The only useful version of this command is pulsing bit 0,
     * which does a CPU reset.
     */
    if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
        if(!(val & 1))
            val = KBD_CCMD_RESET;
        else
            val = KBD_CCMD_NO_OP;
    }

    switch(val) {
    case KBD_CCMD_READ_MODE:
        kbd_queue(s, s->mode, 0);
        break;
    case KBD_CCMD_WRITE_MODE:
    case KBD_CCMD_WRITE_OBUF:
    case KBD_CCMD_WRITE_AUX_OBUF:
    case KBD_CCMD_WRITE_MOUSE:
    case KBD_CCMD_WRITE_OUTPORT:
        s->write_cmd = val;
        break;
    case KBD_CCMD_MOUSE_DISABLE:
        s->mode |= KBD_MODE_DISABLE_MOUSE;
        break;
    case KBD_CCMD_MOUSE_ENABLE:
        s->mode &= ~KBD_MODE_DISABLE_MOUSE;
        break;
    case KBD_CCMD_TEST_MOUSE:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_SELF_TEST:
        s->status |= KBD_STAT_SELFTEST;
        kbd_queue(s, 0x55, 0);
        break;
    case KBD_CCMD_KBD_TEST:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_KBD_DISABLE:
        s->mode |= KBD_MODE_DISABLE_KBD;
        kbd_update_irq(s);
        break;
    case KBD_CCMD_KBD_ENABLE:
        s->mode &= ~KBD_MODE_DISABLE_KBD;
        kbd_update_irq(s);
        break;
    case KBD_CCMD_READ_INPORT:
        kbd_queue(s, 0x80, 0);
        break;
    case KBD_CCMD_READ_OUTPORT:
        kbd_queue(s, s->outport, 0);
        break;
    case KBD_CCMD_ENABLE_A20:
        qemu_irq_raise(s->a20_out);
        s->outport |= KBD_OUT_A20;
        break;
    case KBD_CCMD_DISABLE_A20:
        qemu_irq_lower(s->a20_out);
        s->outport &= ~KBD_OUT_A20;
        break;
    case KBD_CCMD_RESET:
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        break;
    case KBD_CCMD_NO_OP:
        /* ignore that */
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
        break;
    }
}

static uint64_t kbd_read_data(void *opaque, hwaddr addr,
                              unsigned size)
{
    KBDState *s = opaque;
    uint32_t val;

    if (s->pending == KBD_PENDING_AUX)
        val = ps2_read_data(s->mouse);
    else
        val = ps2_read_data(s->kbd);

    trace_pckbd_kbd_read_data(val);
    return val;
}

static void kbd_write_data(void *opaque, hwaddr addr,
                           uint64_t val, unsigned size)
{
    KBDState *s = opaque;

    trace_pckbd_kbd_write_data(val);

    switch(s->write_cmd) {
    case 0:
        ps2_write_keyboard(s->kbd, val);
        break;
    case KBD_CCMD_WRITE_MODE:
        s->mode = val;
        ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
        /* ??? */
        kbd_update_irq(s);
        break;
    case KBD_CCMD_WRITE_OBUF:
        kbd_queue(s, val, 0);
        break;
    case KBD_CCMD_WRITE_AUX_OBUF:
        kbd_queue(s, val, 1);
        break;
    case KBD_CCMD_WRITE_OUTPORT:
        outport_write(s, val);
        break;
    case KBD_CCMD_WRITE_MOUSE:
        ps2_write_mouse(s->mouse, val);
        break;
    default:
        break;
    }
    s->write_cmd = 0;
}

static void kbd_reset(void *opaque)
{
    KBDState *s = opaque;

    s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
    s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
    s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES;
    s->outport_present = false;
}

static uint8_t kbd_outport_default(KBDState *s)
{
    return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES
           | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
           | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
}

static int kbd_outport_post_load(void *opaque, int version_id)
{
    KBDState *s = opaque;
    s->outport_present = true;
    return 0;
}

static bool kbd_outport_needed(void *opaque)
{
    KBDState *s = opaque;
    return s->outport != kbd_outport_default(s);
}

static const VMStateDescription vmstate_kbd_outport = {
    .name = "pckbd_outport",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = kbd_outport_post_load,
    .needed = kbd_outport_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(outport, KBDState),
        VMSTATE_END_OF_LIST()
    }
};

static int kbd_post_load(void *opaque, int version_id)
{
    KBDState *s = opaque;
    if (!s->outport_present) {
        s->outport = kbd_outport_default(s);
    }
    s->outport_present = false;
    return 0;
}

static const VMStateDescription vmstate_kbd = {
    .name = "pckbd",
    .version_id = 3,
    .minimum_version_id = 3,
    .post_load = kbd_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(write_cmd, KBDState),
        VMSTATE_UINT8(status, KBDState),
        VMSTATE_UINT8(mode, KBDState),
        VMSTATE_UINT8(pending, KBDState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_kbd_outport,
        NULL
    }
};

/* Memory mapped interface */
static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
{
    KBDState *s = opaque;

    if (addr & s->mask)
        return kbd_read_status(s, 0, 1) & 0xff;
    else
        return kbd_read_data(s, 0, 1) & 0xff;
}

static void kbd_mm_writefn(void *opaque, hwaddr addr,
                           uint64_t value, unsigned size)
{
    KBDState *s = opaque;

    if (addr & s->mask)
        kbd_write_command(s, 0, value & 0xff, 1);
    else
        kbd_write_data(s, 0, value & 0xff, 1);
}


static const MemoryRegionOps i8042_mmio_ops = {
    .read = kbd_mm_readfn,
    .write = kbd_mm_writefn,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask)
{
    KBDState *s = g_malloc0(sizeof(KBDState));

    s->irq_kbd = kbd_irq;
    s->irq_mouse = mouse_irq;
    s->mask = mask;

    vmstate_register(NULL, 0, &vmstate_kbd, s);

    memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}

#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)

struct ISAKBDState {
    ISADevice parent_obj;

    KBDState kbd;
    MemoryRegion io[2];
};

void i8042_isa_mouse_fake_event(ISAKBDState *isa)
{
    KBDState *s = &isa->kbd;

    ps2_mouse_fake_event(s->mouse);
}

void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
{
    qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
}

static const VMStateDescription vmstate_kbd_isa = {
    .name = "pckbd",
    .version_id = 3,
    .minimum_version_id = 3,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
        VMSTATE_END_OF_LIST()
    }
};

static const MemoryRegionOps i8042_data_ops = {
    .read = kbd_read_data,
    .write = kbd_write_data,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static const MemoryRegionOps i8042_cmd_ops = {
    .read = kbd_read_status,
    .write = kbd_write_command,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void i8042_initfn(Object *obj)
{
    ISAKBDState *isa_s = I8042(obj);
    KBDState *s = &isa_s->kbd;

    memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
                          "i8042-data", 1);
    memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
                          "i8042-cmd", 1);

    qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
}

static void i8042_realizefn(DeviceState *dev, Error **errp)
{
    ISADevice *isadev = ISA_DEVICE(dev);
    ISAKBDState *isa_s = I8042(dev);
    KBDState *s = &isa_s->kbd;

    isa_init_irq(isadev, &s->irq_kbd, 1);
    isa_init_irq(isadev, &s->irq_mouse, 12);

    isa_register_ioport(isadev, isa_s->io + 0, 0x60);
    isa_register_ioport(isadev, isa_s->io + 1, 0x64);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}

static void i8042_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = i8042_realizefn;
    dc->vmsd = &vmstate_kbd_isa;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo i8042_info = {
    .name          = TYPE_I8042,
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(ISAKBDState),
    .instance_init = i8042_initfn,
    .class_init    = i8042_class_initfn,
};

static void i8042_register_types(void)
{
    type_register_static(&i8042_info);
}

type_init(i8042_register_types)
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU PC keyboard emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
71e8a915	24
0430891c	25	#include "qemu/osdep.h"
c2e846bb	26	#include "qemu/log.h"
0d09e41a	27	#include "hw/isa/isa.h"
d6454270	28	#include "migration/vmstate.h"
0d09e41a	29	#include "hw/input/ps2.h"
64552b6b	30	#include "hw/irq.h"
47973a2d	31	#include "hw/input/i8042.h"
71e8a915	32	#include "sysemu/reset.h"
54d31236	33	#include "sysemu/runstate.h"
80cabfad	34
65b182c3	35	#include "trace.h"
80cabfad	36
80cabfad FB	37	/* Keyboard Controller Commands */
	38	#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
	39	#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
	40	#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
	41	#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
	42	#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
	43	#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
	44	#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
	45	#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
	46	#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
	47	#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
	48	#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
	49	#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
	50	#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
	51	#define KBD_CCMD_WRITE_OBUF 0xD2
	52	#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
7d37435b	53	initiated by the auxiliary device */
80cabfad FB	54	#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
	55	#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
	56	#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
5ccaa4ce BK	57	#define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
	58	#define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
	59	#define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
80cabfad FB	60
	61	/* Keyboard Commands */
	62	#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
	63	#define KBD_CMD_ECHO 0xEE
	64	#define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
	65	#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
	66	#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
	67	#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
	68	#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
	69	#define KBD_CMD_RESET 0xFF /* Reset */
	70
	71	/* Keyboard Replies */
	72	#define KBD_REPLY_POR 0xAA /* Power on reset */
	73	#define KBD_REPLY_ACK 0xFA /* Command ACK */
	74	#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
	75
	76	/* Status Register Bits */
	77	#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
	78	#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
	79	#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
	80	#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
	81	#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
	82	#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
	83	#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
	84	#define KBD_STAT_PERR 0x80 /* Parity error */
	85
	86	/* Controller Mode Register Bits */
	87	#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
	88	#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
	89	#define KBD_MODE_SYS 0x04 /* The system flag (?) */
	90	#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
	91	#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
	92	#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
	93	#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
	94	#define KBD_MODE_RFU 0x80
	95
956a3e6b BS	96	/* Output Port Bits */
	97	#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
	98	#define KBD_OUT_A20 0x02 /* x86 only */
	99	#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
	100	#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
	101
d13c0404 PB	102	/* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
	103	* We make the default value of the outport include these four bits,
	104	* so that the subsection is rarely necessary.
	105	*/
	106	#define KBD_OUT_ONES 0xcc
	107
80cabfad FB	108	/* Mouse Commands */
	109	#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
	110	#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
	111	#define AUX_SET_RES 0xE8 /* Set resolution */
	112	#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
	113	#define AUX_SET_STREAM 0xEA /* Set stream mode */
	114	#define AUX_POLL 0xEB /* Poll */
	115	#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
	116	#define AUX_SET_WRAP 0xEE /* Set wrap mode */
	117	#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
	118	#define AUX_GET_TYPE 0xF2 /* Get type */
	119	#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
	120	#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
	121	#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
	122	#define AUX_SET_DEFAULT 0xF6
	123	#define AUX_RESET 0xFF /* Reset aux device */
	124	#define AUX_ACK 0xFA /* Command byte ACK. */
	125
	126	#define MOUSE_STATUS_REMOTE 0x40
	127	#define MOUSE_STATUS_ENABLED 0x20
	128	#define MOUSE_STATUS_SCALE21 0x10
	129
daa57963 FB	130	#define KBD_PENDING_KBD 1
daa57963 FB	131	#define KBD_PENDING_AUX 2
80cabfad FB	132
80cabfad FB	133	typedef struct KBDState {
80cabfad FB	134	uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
	135	uint8_t status;
	136	uint8_t mode;
956a3e6b	137	uint8_t outport;
a28fe7e3	138	bool outport_present;
daa57963	139	/* Bitmask of devices with data available. */
7783e9f0	140	uint8_t pending;
daa57963 FB	141	void *kbd;
daa57963 FB	142	void *mouse;
b7678d96	143
d537cf6c PB	144	qemu_irq irq_kbd;
d537cf6c PB	145	qemu_irq irq_mouse;
3115b9e2	146	qemu_irq a20_out;
a8170e5e	147	hwaddr mask;
80cabfad FB	148	} KBDState;
80cabfad FB	149
80cabfad FB	150	/* update irq and KBD_STAT_[MOUSE_]OBF */
	151	/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
	152	incorrect, but it avoids having to simulate exact delays */
	153	static void kbd_update_irq(KBDState *s)
	154	{
b7678d96	155	int irq_kbd_level, irq_mouse_level;
80cabfad	156
b7678d96 TS	157	irq_kbd_level = 0;
b7678d96 TS	158	irq_mouse_level = 0;
80cabfad	159	s->status &= ~(KBD_STAT_OBF \| KBD_STAT_MOUSE_OBF);
956a3e6b	160	s->outport &= ~(KBD_OUT_OBF \| KBD_OUT_MOUSE_OBF);
daa57963	161	if (s->pending) {
80cabfad	162	s->status \|= KBD_STAT_OBF;
956a3e6b	163	s->outport \|= KBD_OUT_OBF;
b92bb99b	164	/* kbd data takes priority over aux data. */
daa57963	165	if (s->pending == KBD_PENDING_AUX) {
80cabfad	166	s->status \|= KBD_STAT_MOUSE_OBF;
956a3e6b	167	s->outport \|= KBD_OUT_MOUSE_OBF;
80cabfad	168	if (s->mode & KBD_MODE_MOUSE_INT)
b7678d96	169	irq_mouse_level = 1;
80cabfad	170	} else {
5fafdf24	171	if ((s->mode & KBD_MODE_KBD_INT) &&
80cabfad	172	!(s->mode & KBD_MODE_DISABLE_KBD))
b7678d96	173	irq_kbd_level = 1;
80cabfad FB	174	}
80cabfad FB	175	}
d537cf6c PB	176	qemu_set_irq(s->irq_kbd, irq_kbd_level);
d537cf6c PB	177	qemu_set_irq(s->irq_mouse, irq_mouse_level);
80cabfad FB	178	}
80cabfad FB	179
daa57963	180	static void kbd_update_kbd_irq(void *opaque, int level)
80cabfad	181	{
daa57963	182	KBDState s = (KBDState )opaque;
80cabfad	183
daa57963 FB	184	if (level)
daa57963 FB	185	s->pending \|= KBD_PENDING_KBD;
80cabfad	186	else
daa57963	187	s->pending &= ~KBD_PENDING_KBD;
80cabfad FB	188	kbd_update_irq(s);
	189	}
	190
daa57963	191	static void kbd_update_aux_irq(void *opaque, int level)
80cabfad	192	{
daa57963 FB	193	KBDState s = (KBDState )opaque;
	194
	195	if (level)
	196	s->pending \|= KBD_PENDING_AUX;
	197	else
	198	s->pending &= ~KBD_PENDING_AUX;
	199	kbd_update_irq(s);
80cabfad FB	200	}
80cabfad FB	201
d540bfe0 AG	202	static uint64_t kbd_read_status(void *opaque, hwaddr addr,
d540bfe0 AG	203	unsigned size)
80cabfad	204	{
b41a2cd1	205	KBDState *s = opaque;
80cabfad FB	206	int val;
80cabfad FB	207	val = s->status;
65b182c3	208	trace_pckbd_kbd_read_status(val);
80cabfad FB	209	return val;
	210	}
	211
daa57963 FB	212	static void kbd_queue(KBDState *s, int b, int aux)
	213	{
	214	if (aux)
	215	ps2_queue(s->mouse, b);
	216	else
	217	ps2_queue(s->kbd, b);
	218	}
	219
4b78a802	220	static void outport_write(KBDState *s, uint32_t val)
956a3e6b	221	{
65b182c3	222	trace_pckbd_outport_write(val);
956a3e6b	223	s->outport = val;
3115b9e2	224	qemu_set_irq(s->a20_out, (val >> 1) & 1);
956a3e6b	225	if (!(val & 1)) {
cf83f140	226	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
956a3e6b BS	227	}
	228	}
	229
d540bfe0 AG	230	static void kbd_write_command(void *opaque, hwaddr addr,
d540bfe0 AG	231	uint64_t val, unsigned size)
80cabfad	232	{
b41a2cd1	233	KBDState *s = opaque;
80cabfad	234
65b182c3	235	trace_pckbd_kbd_write_command(val);
5ccaa4ce BK	236
	237	/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
	238	* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
	239	* command specify the output port bits to be pulsed.
	240	* 0: Bit should be pulsed. 1: Bit should not be modified.
	241	* The only useful version of this command is pulsing bit 0,
	242	* which does a CPU reset.
	243	*/
	244	if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
	245	if(!(val & 1))
	246	val = KBD_CCMD_RESET;
	247	else
	248	val = KBD_CCMD_NO_OP;
	249	}
	250
80cabfad FB	251	switch(val) {
80cabfad FB	252	case KBD_CCMD_READ_MODE:
889bec69	253	kbd_queue(s, s->mode, 0);
80cabfad FB	254	break;
	255	case KBD_CCMD_WRITE_MODE:
	256	case KBD_CCMD_WRITE_OBUF:
	257	case KBD_CCMD_WRITE_AUX_OBUF:
	258	case KBD_CCMD_WRITE_MOUSE:
	259	case KBD_CCMD_WRITE_OUTPORT:
	260	s->write_cmd = val;
	261	break;
	262	case KBD_CCMD_MOUSE_DISABLE:
	263	s->mode \|= KBD_MODE_DISABLE_MOUSE;
	264	break;
	265	case KBD_CCMD_MOUSE_ENABLE:
	266	s->mode &= ~KBD_MODE_DISABLE_MOUSE;
	267	break;
	268	case KBD_CCMD_TEST_MOUSE:
	269	kbd_queue(s, 0x00, 0);
	270	break;
	271	case KBD_CCMD_SELF_TEST:
	272	s->status \|= KBD_STAT_SELFTEST;
	273	kbd_queue(s, 0x55, 0);
	274	break;
	275	case KBD_CCMD_KBD_TEST:
	276	kbd_queue(s, 0x00, 0);
	277	break;
	278	case KBD_CCMD_KBD_DISABLE:
	279	s->mode \|= KBD_MODE_DISABLE_KBD;
	280	kbd_update_irq(s);
	281	break;
	282	case KBD_CCMD_KBD_ENABLE:
	283	s->mode &= ~KBD_MODE_DISABLE_KBD;
	284	kbd_update_irq(s);
	285	break;
	286	case KBD_CCMD_READ_INPORT:
f1b7e0e4	287	kbd_queue(s, 0x80, 0);
80cabfad FB	288	break;
80cabfad FB	289	case KBD_CCMD_READ_OUTPORT:
956a3e6b	290	kbd_queue(s, s->outport, 0);
80cabfad	291	break;
80cabfad	292	case KBD_CCMD_ENABLE_A20:
3115b9e2	293	qemu_irq_raise(s->a20_out);
956a3e6b	294	s->outport \|= KBD_OUT_A20;
80cabfad FB	295	break;
80cabfad FB	296	case KBD_CCMD_DISABLE_A20:
3115b9e2	297	qemu_irq_lower(s->a20_out);
956a3e6b	298	s->outport &= ~KBD_OUT_A20;
80cabfad	299	break;
80cabfad	300	case KBD_CCMD_RESET:
cf83f140	301	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
80cabfad	302	break;
5ccaa4ce BK	303	case KBD_CCMD_NO_OP:
5ccaa4ce BK	304	/* ignore that */
80cabfad FB	305	break;
80cabfad FB	306	default:
c2e846bb PMD	307	qemu_log_mask(LOG_GUEST_ERROR,
c2e846bb PMD	308	"unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
80cabfad FB	309	break;
	310	}
	311	}
	312
d540bfe0 AG	313	static uint64_t kbd_read_data(void *opaque, hwaddr addr,
d540bfe0 AG	314	unsigned size)
80cabfad	315	{
63066f4f	316	KBDState *s = opaque;
e41c0f26	317	uint32_t val;
80cabfad	318
daa57963	319	if (s->pending == KBD_PENDING_AUX)
e41c0f26 AZ	320	val = ps2_read_data(s->mouse);
	321	else
	322	val = ps2_read_data(s->kbd);
80cabfad	323
65b182c3	324	trace_pckbd_kbd_read_data(val);
e41c0f26	325	return val;
80cabfad FB	326	}
80cabfad FB	327
d540bfe0 AG	328	static void kbd_write_data(void *opaque, hwaddr addr,
d540bfe0 AG	329	uint64_t val, unsigned size)
80cabfad	330	{
b41a2cd1	331	KBDState *s = opaque;
80cabfad	332
65b182c3	333	trace_pckbd_kbd_write_data(val);
80cabfad FB	334
	335	switch(s->write_cmd) {
	336	case 0:
daa57963	337	ps2_write_keyboard(s->kbd, val);
80cabfad FB	338	break;
	339	case KBD_CCMD_WRITE_MODE:
	340	s->mode = val;
f94f5d71	341	ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
daa57963	342	/* ??? */
80cabfad FB	343	kbd_update_irq(s);
	344	break;
	345	case KBD_CCMD_WRITE_OBUF:
	346	kbd_queue(s, val, 0);
	347	break;
	348	case KBD_CCMD_WRITE_AUX_OBUF:
	349	kbd_queue(s, val, 1);
	350	break;
	351	case KBD_CCMD_WRITE_OUTPORT:
4b78a802	352	outport_write(s, val);
80cabfad FB	353	break;
80cabfad FB	354	case KBD_CCMD_WRITE_MOUSE:
daa57963	355	ps2_write_mouse(s->mouse, val);
80cabfad FB	356	break;
	357	default:
	358	break;
	359	}
	360	s->write_cmd = 0;
	361	}
	362
d7d02e3c	363	static void kbd_reset(void *opaque)
80cabfad	364	{
d7d02e3c	365	KBDState *s = opaque;
80cabfad	366
80cabfad FB	367	s->mode = KBD_MODE_KBD_INT \| KBD_MODE_MOUSE_INT;
80cabfad FB	368	s->status = KBD_STAT_CMD \| KBD_STAT_UNLOCKED;
d13c0404	369	s->outport = KBD_OUT_RESET \| KBD_OUT_A20 \| KBD_OUT_ONES;
a28fe7e3 PD	370	s->outport_present = false;
	371	}
	372
	373	static uint8_t kbd_outport_default(KBDState *s)
	374	{
d13c0404	375	return KBD_OUT_RESET \| KBD_OUT_A20 \| KBD_OUT_ONES
a28fe7e3 PD	376	\| (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
	377	\| (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
	378	}
	379
	380	static int kbd_outport_post_load(void *opaque, int version_id)
	381	{
	382	KBDState *s = opaque;
	383	s->outport_present = true;
	384	return 0;
	385	}
	386
5cd8cada JQ	387	static bool kbd_outport_needed(void *opaque)
	388	{
	389	KBDState *s = opaque;
	390	return s->outport != kbd_outport_default(s);
	391	}
	392
a28fe7e3 PD	393	static const VMStateDescription vmstate_kbd_outport = {
	394	.name = "pckbd_outport",
	395	.version_id = 1,
	396	.minimum_version_id = 1,
	397	.post_load = kbd_outport_post_load,
5cd8cada	398	.needed = kbd_outport_needed,
a28fe7e3 PD	399	.fields = (VMStateField[]) {
	400	VMSTATE_UINT8(outport, KBDState),
	401	VMSTATE_END_OF_LIST()
	402	}
	403	};
	404
a28fe7e3 PD	405	static int kbd_post_load(void *opaque, int version_id)
	406	{
	407	KBDState *s = opaque;
	408	if (!s->outport_present) {
	409	s->outport = kbd_outport_default(s);
	410	}
	411	s->outport_present = false;
	412	return 0;
80cabfad FB	413	}
80cabfad FB	414
3c619b59 JQ	415	static const VMStateDescription vmstate_kbd = {
	416	.name = "pckbd",
	417	.version_id = 3,
	418	.minimum_version_id = 3,
a28fe7e3	419	.post_load = kbd_post_load,
d49805ae	420	.fields = (VMStateField[]) {
3c619b59 JQ	421	VMSTATE_UINT8(write_cmd, KBDState),
	422	VMSTATE_UINT8(status, KBDState),
	423	VMSTATE_UINT8(mode, KBDState),
	424	VMSTATE_UINT8(pending, KBDState),
	425	VMSTATE_END_OF_LIST()
a28fe7e3	426	},
5cd8cada JQ	427	.subsections = (const VMStateDescription*[]) {
	428	&vmstate_kbd_outport,
	429	NULL
3c619b59 JQ	430	}
3c619b59 JQ	431	};
675376f2	432
b92bb99b	433	/* Memory mapped interface */
5876503c	434	static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
b92bb99b TS	435	{
	436	KBDState *s = opaque;
	437
4efbe58f	438	if (addr & s->mask)
d540bfe0	439	return kbd_read_status(s, 0, 1) & 0xff;
4efbe58f	440	else
d540bfe0	441	return kbd_read_data(s, 0, 1) & 0xff;
b92bb99b TS	442	}
b92bb99b TS	443
5876503c PM	444	static void kbd_mm_writefn(void *opaque, hwaddr addr,
5876503c PM	445	uint64_t value, unsigned size)
b92bb99b TS	446	{
	447	KBDState *s = opaque;
	448
4efbe58f	449	if (addr & s->mask)
d540bfe0	450	kbd_write_command(s, 0, value & 0xff, 1);
4efbe58f	451	else
d540bfe0	452	kbd_write_data(s, 0, value & 0xff, 1);
b92bb99b TS	453	}
b92bb99b TS	454
5876503c	455
dbff76ac	456	static const MemoryRegionOps i8042_mmio_ops = {
5876503c PM	457	.read = kbd_mm_readfn,
	458	.write = kbd_mm_writefn,
	459	.valid.min_access_size = 1,
	460	.valid.max_access_size = 4,
dbff76ac	461	.endianness = DEVICE_NATIVE_ENDIAN,
b92bb99b TS	462	};
b92bb99b TS	463
71db710f	464	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dbff76ac	465	MemoryRegion *region, ram_addr_t size,
a8170e5e	466	hwaddr mask)
b92bb99b	467	{
7267c094	468	KBDState *s = g_malloc0(sizeof(KBDState));
b92bb99b TS	469
	470	s->irq_kbd = kbd_irq;
	471	s->irq_mouse = mouse_irq;
4efbe58f	472	s->mask = mask;
b92bb99b	473
0be71e32	474	vmstate_register(NULL, 0, &vmstate_kbd, s);
dbff76ac	475
2c9b15ca	476	memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
b92bb99b TS	477
	478	s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
	479	s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
a08d4367	480	qemu_register_reset(kbd_reset, s);
b92bb99b	481	}
da85ccfb	482
a2e0b863 AF	483	#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
a2e0b863 AF	484
0fe4bb32	485	struct ISAKBDState {
a2e0b863 AF	486	ISADevice parent_obj;
a2e0b863 AF	487
dbff76ac RH	488	KBDState kbd;
dbff76ac RH	489	MemoryRegion io[2];
0fe4bb32	490	};
da85ccfb	491
0fe4bb32	492	void i8042_isa_mouse_fake_event(ISAKBDState *isa)
956a3e6b	493	{
a2e0b863	494	KBDState *s = &isa->kbd;
956a3e6b BS	495
	496	ps2_mouse_fake_event(s->mouse);
	497	}
	498
d80fe99d	499	void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
956a3e6b	500	{
d80fe99d	501	qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
956a3e6b BS	502	}
956a3e6b BS	503
d05ac8fa	504	static const VMStateDescription vmstate_kbd_isa = {
be73cfe2 JQ	505	.name = "pckbd",
	506	.version_id = 3,
	507	.minimum_version_id = 3,
d49805ae	508	.fields = (VMStateField[]) {
be73cfe2 JQ	509	VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
	510	VMSTATE_END_OF_LIST()
	511	}
	512	};
	513
dbff76ac	514	static const MemoryRegionOps i8042_data_ops = {
d540bfe0 AG	515	.read = kbd_read_data,
	516	.write = kbd_write_data,
	517	.impl = {
	518	.min_access_size = 1,
	519	.max_access_size = 1,
	520	},
	521	.endianness = DEVICE_LITTLE_ENDIAN,
dbff76ac RH	522	};
	523
	524	static const MemoryRegionOps i8042_cmd_ops = {
d540bfe0 AG	525	.read = kbd_read_status,
	526	.write = kbd_write_command,
	527	.impl = {
	528	.min_access_size = 1,
	529	.max_access_size = 1,
	530	},
	531	.endianness = DEVICE_LITTLE_ENDIAN,
dbff76ac RH	532	};
dbff76ac RH	533
db895a1e	534	static void i8042_initfn(Object *obj)
da85ccfb	535	{
db895a1e	536	ISAKBDState *isa_s = I8042(obj);
dbff76ac	537	KBDState *s = &isa_s->kbd;
da85ccfb	538
1437c94b PB	539	memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
	540	"i8042-data", 1);
	541	memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
	542	"i8042-cmd", 1);
3115b9e2 EV	543
3115b9e2 EV	544	qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
db895a1e AF	545	}
	546
	547	static void i8042_realizefn(DeviceState dev, Error *errp)
	548	{
	549	ISADevice *isadev = ISA_DEVICE(dev);
	550	ISAKBDState *isa_s = I8042(dev);
	551	KBDState *s = &isa_s->kbd;
	552
	553	isa_init_irq(isadev, &s->irq_kbd, 1);
	554	isa_init_irq(isadev, &s->irq_mouse, 12);
	555
	556	isa_register_ioport(isadev, isa_s->io + 0, 0x60);
	557	isa_register_ioport(isadev, isa_s->io + 1, 0x64);
da85ccfb GH	558
	559	s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
	560	s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
da85ccfb GH	561	qemu_register_reset(kbd_reset, s);
	562	}
	563
8f04ee08 AL	564	static void i8042_class_initfn(ObjectClass klass, void data)
8f04ee08 AL	565	{
39bffca2	566	DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e AF	567
db895a1e AF	568	dc->realize = i8042_realizefn;
39bffca2	569	dc->vmsd = &vmstate_kbd_isa;
cbe9ed73	570	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
8f04ee08 AL	571	}
8f04ee08 AL	572
8c43a6f0	573	static const TypeInfo i8042_info = {
a2e0b863	574	.name = TYPE_I8042,
39bffca2 AL	575	.parent = TYPE_ISA_DEVICE,
39bffca2 AL	576	.instance_size = sizeof(ISAKBDState),
db895a1e	577	.instance_init = i8042_initfn,
39bffca2	578	.class_init = i8042_class_initfn,
da85ccfb GH	579	};
da85ccfb GH	580
83f7d43a	581	static void i8042_register_types(void)
da85ccfb	582	{
39bffca2	583	type_register_static(&i8042_info);
da85ccfb	584	}
83f7d43a AF	585
83f7d43a AF	586	type_init(i8042_register_types)