[qemu.git] / hw / i8254.c

/*
 * QEMU 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pc.h"
#include "isa.h"
#include "qemu-timer.h"

//#define DEBUG_PIT

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

typedef struct PITChannelState {
    int count; /* can be 65536 */
    uint16_t latched_count;
    uint8_t count_latched;
    uint8_t status_latched;
    uint8_t status;
    uint8_t read_state;
    uint8_t write_state;
    uint8_t write_latch;
    uint8_t rw_mode;
    uint8_t mode;
    uint8_t bcd; /* not supported */
    uint8_t gate; /* timer start */
    int64_t count_load_time;
    /* irq handling */
    int64_t next_transition_time;
    QEMUTimer *irq_timer;
    qemu_irq irq;
} PITChannelState;

typedef struct PITState {
    ISADevice dev;
    uint32_t irq;
    uint32_t iobase;
    PITChannelState channels[3];
} PITState;

static PITState pit_state;

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);

static int pit_get_count(PITChannelState *s)
{
    uint64_t d;
    int counter;

    d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
                 get_ticks_per_sec());
    switch(s->mode) {
    case 0:
    case 1:
    case 4:
    case 5:
        counter = (s->count - d) & 0xffff;
        break;
    case 3:
        /* XXX: may be incorrect for odd counts */
        counter = s->count - ((2 * d) % s->count);
        break;
    default:
        counter = s->count - (d % s->count);
        break;
    }
    return counter;
}

/* get pit output bit */
static int pit_get_out1(PITChannelState *s, int64_t current_time)
{
    uint64_t d;
    int out;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
                 get_ticks_per_sec());
    switch(s->mode) {
    default:
    case 0:
        out = (d >= s->count);
        break;
    case 1:
        out = (d < s->count);
        break;
    case 2:
        if ((d % s->count) == 0 && d != 0)
            out = 1;
        else
            out = 0;
        break;
    case 3:
        out = (d % s->count) < ((s->count + 1) >> 1);
        break;
    case 4:
    case 5:
        out = (d == s->count);
        break;
    }
    return out;
}

int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
{
    PITState *pit = DO_UPCAST(PITState, dev, dev);
    PITChannelState *s = &pit->channels[channel];
    return pit_get_out1(s, current_time);
}

/* return -1 if no transition will occur.  */
static int64_t pit_get_next_transition_time(PITChannelState *s,
                                            int64_t current_time)
{
    uint64_t d, next_time, base;
    int period2;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
                 get_ticks_per_sec());
    switch(s->mode) {
    default:
    case 0:
    case 1:
        if (d < s->count)
            next_time = s->count;
        else
            return -1;
        break;
    case 2:
        base = (d / s->count) * s->count;
        if ((d - base) == 0 && d != 0)
            next_time = base + s->count;
        else
            next_time = base + s->count + 1;
        break;
    case 3:
        base = (d / s->count) * s->count;
        period2 = ((s->count + 1) >> 1);
        if ((d - base) < period2)
            next_time = base + period2;
        else
            next_time = base + s->count;
        break;
    case 4:
    case 5:
        if (d < s->count)
            next_time = s->count;
        else if (d == s->count)
            next_time = s->count + 1;
        else
            return -1;
        break;
    }
    /* convert to timer units */
    next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
                                              PIT_FREQ);
    /* fix potential rounding problems */
    /* XXX: better solution: use a clock at PIT_FREQ Hz */
    if (next_time <= current_time)
        next_time = current_time + 1;
    return next_time;
}

/* val must be 0 or 1 */
void pit_set_gate(ISADevice *dev, int channel, int val)
{
    PITState *pit = DO_UPCAST(PITState, dev, dev);
    PITChannelState *s = &pit->channels[channel];

    switch(s->mode) {
    default:
    case 0:
    case 4:
        /* XXX: just disable/enable counting */
        break;
    case 1:
    case 5:
        if (s->gate < val) {
            /* restart counting on rising edge */
            s->count_load_time = qemu_get_clock_ns(vm_clock);
            pit_irq_timer_update(s, s->count_load_time);
        }
        break;
    case 2:
    case 3:
        if (s->gate < val) {
            /* restart counting on rising edge */
            s->count_load_time = qemu_get_clock_ns(vm_clock);
            pit_irq_timer_update(s, s->count_load_time);
        }
        /* XXX: disable/enable counting */
        break;
    }
    s->gate = val;
}

int pit_get_gate(ISADevice *dev, int channel)
{
    PITState *pit = DO_UPCAST(PITState, dev, dev);
    PITChannelState *s = &pit->channels[channel];
    return s->gate;
}

int pit_get_initial_count(ISADevice *dev, int channel)
{
    PITState *pit = DO_UPCAST(PITState, dev, dev);
    PITChannelState *s = &pit->channels[channel];
    return s->count;
}

int pit_get_mode(ISADevice *dev, int channel)
{
    PITState *pit = DO_UPCAST(PITState, dev, dev);
    PITChannelState *s = &pit->channels[channel];
    return s->mode;
}

static inline void pit_load_count(PITChannelState *s, int val)
{
    if (val == 0)
        val = 0x10000;
    s->count_load_time = qemu_get_clock_ns(vm_clock);
    s->count = val;
    pit_irq_timer_update(s, s->count_load_time);
}

/* if already latched, do not latch again */
static void pit_latch_count(PITChannelState *s)
{
    if (!s->count_latched) {
        s->latched_count = pit_get_count(s);
        s->count_latched = s->rw_mode;
    }
}

static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PITState *pit = opaque;
    int channel, access;
    PITChannelState *s;

    addr &= 3;
    if (addr == 3) {
        channel = val >> 6;
        if (channel == 3) {
            /* read back command */
            for(channel = 0; channel < 3; channel++) {
                s = &pit->channels[channel];
                if (val & (2 << channel)) {
                    if (!(val & 0x20)) {
                        pit_latch_count(s);
                    }
                    if (!(val & 0x10) && !s->status_latched) {
                        /* status latch */
                        /* XXX: add BCD and null count */
                        s->status =  (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) |
                            (s->rw_mode << 4) |
                            (s->mode << 1) |
                            s->bcd;
                        s->status_latched = 1;
                    }
                }
            }
        } else {
            s = &pit->channels[channel];
            access = (val >> 4) & 3;
            if (access == 0) {
                pit_latch_count(s);
            } else {
                s->rw_mode = access;
                s->read_state = access;
                s->write_state = access;

                s->mode = (val >> 1) & 7;
                s->bcd = val & 1;
                /* XXX: update irq timer ? */
            }
        }
    } else {
        s = &pit->channels[addr];
        switch(s->write_state) {
        default:
        case RW_STATE_LSB:
            pit_load_count(s, val);
            break;
        case RW_STATE_MSB:
            pit_load_count(s, val << 8);
            break;
        case RW_STATE_WORD0:
            s->write_latch = val;
            s->write_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            pit_load_count(s, s->write_latch | (val << 8));
            s->write_state = RW_STATE_WORD0;
            break;
        }
    }
}

static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
{
    PITState *pit = opaque;
    int ret, count;
    PITChannelState *s;

    addr &= 3;
    s = &pit->channels[addr];
    if (s->status_latched) {
        s->status_latched = 0;
        ret = s->status;
    } else if (s->count_latched) {
        switch(s->count_latched) {
        default:
        case RW_STATE_LSB:
            ret = s->latched_count & 0xff;
            s->count_latched = 0;
            break;
        case RW_STATE_MSB:
            ret = s->latched_count >> 8;
            s->count_latched = 0;
            break;
        case RW_STATE_WORD0:
            ret = s->latched_count & 0xff;
            s->count_latched = RW_STATE_MSB;
            break;
        }
    } else {
        switch(s->read_state) {
        default:
        case RW_STATE_LSB:
            count = pit_get_count(s);
            ret = count & 0xff;
            break;
        case RW_STATE_MSB:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            break;
        case RW_STATE_WORD0:
            count = pit_get_count(s);
            ret = count & 0xff;
            s->read_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            s->read_state = RW_STATE_WORD0;
            break;
        }
    }
    return ret;
}

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
{
    int64_t expire_time;
    int irq_level;

    if (!s->irq_timer)
        return;
    expire_time = pit_get_next_transition_time(s, current_time);
    irq_level = pit_get_out1(s, current_time);
    qemu_set_irq(s->irq, irq_level);
#ifdef DEBUG_PIT
    printf("irq_level=%d next_delay=%f\n",
           irq_level,
           (double)(expire_time - current_time) / get_ticks_per_sec());
#endif
    s->next_transition_time = expire_time;
    if (expire_time != -1)
        qemu_mod_timer(s->irq_timer, expire_time);
    else
        qemu_del_timer(s->irq_timer);
}

static void pit_irq_timer(void *opaque)
{
    PITChannelState *s = opaque;

    pit_irq_timer_update(s, s->next_transition_time);
}

static const VMStateDescription vmstate_pit_channel = {
    .name = "pit channel",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_INT32(count, PITChannelState),
        VMSTATE_UINT16(latched_count, PITChannelState),
        VMSTATE_UINT8(count_latched, PITChannelState),
        VMSTATE_UINT8(status_latched, PITChannelState),
        VMSTATE_UINT8(status, PITChannelState),
        VMSTATE_UINT8(read_state, PITChannelState),
        VMSTATE_UINT8(write_state, PITChannelState),
        VMSTATE_UINT8(write_latch, PITChannelState),
        VMSTATE_UINT8(rw_mode, PITChannelState),
        VMSTATE_UINT8(mode, PITChannelState),
        VMSTATE_UINT8(bcd, PITChannelState),
        VMSTATE_UINT8(gate, PITChannelState),
        VMSTATE_INT64(count_load_time, PITChannelState),
        VMSTATE_INT64(next_transition_time, PITChannelState),
        VMSTATE_END_OF_LIST()
    }
};

static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for(i = 0; i < 3; i++) {
        s = &pit->channels[i];
        s->count=qemu_get_be32(f);
        qemu_get_be16s(f, &s->latched_count);
        qemu_get_8s(f, &s->count_latched);
        qemu_get_8s(f, &s->status_latched);
        qemu_get_8s(f, &s->status);
        qemu_get_8s(f, &s->read_state);
        qemu_get_8s(f, &s->write_state);
        qemu_get_8s(f, &s->write_latch);
        qemu_get_8s(f, &s->rw_mode);
        qemu_get_8s(f, &s->mode);
        qemu_get_8s(f, &s->bcd);
        qemu_get_8s(f, &s->gate);
        s->count_load_time=qemu_get_be64(f);
        if (s->irq_timer) {
            s->next_transition_time=qemu_get_be64(f);
            qemu_get_timer(f, s->irq_timer);
        }
    }
    return 0;
}

static const VMStateDescription vmstate_pit = {
    .name = "i8254",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 1,
    .load_state_old = pit_load_old,
    .fields      = (VMStateField []) {
        VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState),
        VMSTATE_TIMER(channels[0].irq_timer, PITState),
        VMSTATE_END_OF_LIST()
    }
};

static void pit_reset(DeviceState *dev)
{
    PITState *pit = container_of(dev, PITState, dev.qdev);
    PITChannelState *s;
    int i;

    for(i = 0;i < 3; i++) {
        s = &pit->channels[i];
        s->mode = 3;
        s->gate = (i != 2);
        pit_load_count(s, 0);
    }
}

/* When HPET is operating in legacy mode, i8254 timer0 is disabled */
void hpet_pit_disable(void) {
    PITChannelState *s;
    s = &pit_state.channels[0];
    if (s->irq_timer)
        qemu_del_timer(s->irq_timer);
}

/* When HPET is reset or leaving legacy mode, it must reenable i8254
 * timer 0
 */

void hpet_pit_enable(void)
{
    PITState *pit = &pit_state;
    PITChannelState *s;
    s = &pit->channels[0];
    s->mode = 3;
    s->gate = 1;
    pit_load_count(s, 0);
}

static int pit_initfn(ISADevice *dev)
{
    PITState *pit = DO_UPCAST(PITState, dev, dev);
    PITChannelState *s;

    s = &pit->channels[0];
    /* the timer 0 is connected to an IRQ */
    s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
    s->irq = isa_get_irq(pit->irq);

    register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
    register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
    isa_init_ioport(dev, pit->iobase);

    qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);

    return 0;
}

static ISADeviceInfo pit_info = {
    .qdev.name     = "isa-pit",
    .qdev.size     = sizeof(PITState),
    .qdev.vmsd     = &vmstate_pit,
    .qdev.reset    = pit_reset,
    .qdev.no_user  = 1,
    .init          = pit_initfn,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("irq", PITState, irq,  -1),
        DEFINE_PROP_HEX32("iobase", PITState, iobase,  -1),
        DEFINE_PROP_END_OF_LIST(),
    },
};

static void pit_register(void)
{
    isa_qdev_register(&pit_info);
}
device_init(pit_register)
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 8253/8254 interval timer emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "pc.h"
	26	#include "isa.h"
	27	#include "qemu-timer.h"
80cabfad	28
b0a21b53 FB	29	//#define DEBUG_PIT
b0a21b53 FB	30
ec844b96 FB	31	#define RW_STATE_LSB 1
	32	#define RW_STATE_MSB 2
	33	#define RW_STATE_WORD0 3
	34	#define RW_STATE_WORD1 4
80cabfad	35
ec844b96 FB	36	typedef struct PITChannelState {
	37	int count; /* can be 65536 */
	38	uint16_t latched_count;
	39	uint8_t count_latched;
	40	uint8_t status_latched;
	41	uint8_t status;
	42	uint8_t read_state;
	43	uint8_t write_state;
	44	uint8_t write_latch;
	45	uint8_t rw_mode;
	46	uint8_t mode;
	47	uint8_t bcd; /* not supported */
	48	uint8_t gate; /* timer start */
	49	int64_t count_load_time;
	50	/* irq handling */
	51	int64_t next_transition_time;
	52	QEMUTimer *irq_timer;
d537cf6c	53	qemu_irq irq;
ec844b96 FB	54	} PITChannelState;
ec844b96 FB	55
64d7e9a4 BS	56	typedef struct PITState {
	57	ISADevice dev;
	58	uint32_t irq;
	59	uint32_t iobase;
ec844b96	60	PITChannelState channels[3];
64d7e9a4	61	} PITState;
ec844b96 FB	62
ec844b96 FB	63	static PITState pit_state;
80cabfad	64
b0a21b53 FB	65	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
b0a21b53 FB	66
80cabfad FB	67	static int pit_get_count(PITChannelState *s)
	68	{
	69	uint64_t d;
	70	int counter;
	71
74475455	72	d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
6ee093c9	73	get_ticks_per_sec());
80cabfad FB	74	switch(s->mode) {
	75	case 0:
	76	case 1:
	77	case 4:
	78	case 5:
	79	counter = (s->count - d) & 0xffff;
	80	break;
	81	case 3:
	82	/* XXX: may be incorrect for odd counts */
	83	counter = s->count - ((2 * d) % s->count);
	84	break;
	85	default:
	86	counter = s->count - (d % s->count);
	87	break;
	88	}
	89	return counter;
	90	}
	91
	92	/* get pit output bit */
ec844b96	93	static int pit_get_out1(PITChannelState *s, int64_t current_time)
80cabfad FB	94	{
	95	uint64_t d;
	96	int out;
	97
6ee093c9 JQ	98	d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
6ee093c9 JQ	99	get_ticks_per_sec());
80cabfad FB	100	switch(s->mode) {
	101	default:
	102	case 0:
	103	out = (d >= s->count);
	104	break;
	105	case 1:
	106	out = (d < s->count);
	107	break;
	108	case 2:
	109	if ((d % s->count) == 0 && d != 0)
	110	out = 1;
	111	else
	112	out = 0;
	113	break;
	114	case 3:
	115	out = (d % s->count) < ((s->count + 1) >> 1);
	116	break;
	117	case 4:
	118	case 5:
	119	out = (d == s->count);
	120	break;
	121	}
	122	return out;
	123	}
	124
64d7e9a4	125	int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
ec844b96	126	{
64d7e9a4	127	PITState *pit = DO_UPCAST(PITState, dev, dev);
ec844b96 FB	128	PITChannelState *s = &pit->channels[channel];
	129	return pit_get_out1(s, current_time);
	130	}
	131
b0a21b53	132	/* return -1 if no transition will occur. */
5fafdf24	133	static int64_t pit_get_next_transition_time(PITChannelState *s,
b0a21b53	134	int64_t current_time)
80cabfad	135	{
b0a21b53 FB	136	uint64_t d, next_time, base;
b0a21b53 FB	137	int period2;
80cabfad	138
6ee093c9 JQ	139	d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
6ee093c9 JQ	140	get_ticks_per_sec());
80cabfad FB	141	switch(s->mode) {
	142	default:
	143	case 0:
80cabfad	144	case 1:
b0a21b53 FB	145	if (d < s->count)
	146	next_time = s->count;
	147	else
	148	return -1;
80cabfad FB	149	break;
80cabfad FB	150	case 2:
b0a21b53 FB	151	base = (d / s->count) * s->count;
	152	if ((d - base) == 0 && d != 0)
	153	next_time = base + s->count;
	154	else
	155	next_time = base + s->count + 1;
80cabfad FB	156	break;
80cabfad FB	157	case 3:
b0a21b53 FB	158	base = (d / s->count) * s->count;
b0a21b53 FB	159	period2 = ((s->count + 1) >> 1);
5fafdf24	160	if ((d - base) < period2)
b0a21b53 FB	161	next_time = base + period2;
	162	else
	163	next_time = base + s->count;
80cabfad FB	164	break;
	165	case 4:
	166	case 5:
b0a21b53 FB	167	if (d < s->count)
	168	next_time = s->count;
	169	else if (d == s->count)
	170	next_time = s->count + 1;
80cabfad	171	else
b0a21b53	172	return -1;
80cabfad FB	173	break;
80cabfad FB	174	}
b0a21b53	175	/* convert to timer units */
6ee093c9 JQ	176	next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
6ee093c9 JQ	177	PIT_FREQ);
1154e441 FB	178	/* fix potential rounding problems */
	179	/* XXX: better solution: use a clock at PIT_FREQ Hz */
	180	if (next_time <= current_time)
	181	next_time = current_time + 1;
b0a21b53	182	return next_time;
80cabfad FB	183	}
	184
	185	/* val must be 0 or 1 */
64d7e9a4	186	void pit_set_gate(ISADevice *dev, int channel, int val)
80cabfad	187	{
64d7e9a4	188	PITState *pit = DO_UPCAST(PITState, dev, dev);
ec844b96 FB	189	PITChannelState *s = &pit->channels[channel];
ec844b96 FB	190
80cabfad FB	191	switch(s->mode) {
	192	default:
	193	case 0:
	194	case 4:
	195	/* XXX: just disable/enable counting */
	196	break;
	197	case 1:
	198	case 5:
	199	if (s->gate < val) {
	200	/* restart counting on rising edge */
74475455	201	s->count_load_time = qemu_get_clock_ns(vm_clock);
b0a21b53	202	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	203	}
	204	break;
	205	case 2:
	206	case 3:
	207	if (s->gate < val) {
	208	/* restart counting on rising edge */
74475455	209	s->count_load_time = qemu_get_clock_ns(vm_clock);
b0a21b53	210	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	211	}
	212	/* XXX: disable/enable counting */
	213	break;
	214	}
	215	s->gate = val;
	216	}
	217
64d7e9a4	218	int pit_get_gate(ISADevice *dev, int channel)
ec844b96	219	{
64d7e9a4	220	PITState *pit = DO_UPCAST(PITState, dev, dev);
ec844b96 FB	221	PITChannelState *s = &pit->channels[channel];
	222	return s->gate;
	223	}
	224
64d7e9a4	225	int pit_get_initial_count(ISADevice *dev, int channel)
fd06c375	226	{
64d7e9a4	227	PITState *pit = DO_UPCAST(PITState, dev, dev);
fd06c375 FB	228	PITChannelState *s = &pit->channels[channel];
	229	return s->count;
	230	}
	231
64d7e9a4	232	int pit_get_mode(ISADevice *dev, int channel)
fd06c375	233	{
64d7e9a4	234	PITState *pit = DO_UPCAST(PITState, dev, dev);
fd06c375 FB	235	PITChannelState *s = &pit->channels[channel];
	236	return s->mode;
	237	}
	238
80cabfad FB	239	static inline void pit_load_count(PITChannelState *s, int val)
	240	{
	241	if (val == 0)
	242	val = 0x10000;
74475455	243	s->count_load_time = qemu_get_clock_ns(vm_clock);
80cabfad	244	s->count = val;
b0a21b53	245	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	246	}
80cabfad FB	247
ec844b96 FB	248	/* if already latched, do not latch again */
	249	static void pit_latch_count(PITChannelState *s)
	250	{
	251	if (!s->count_latched) {
	252	s->latched_count = pit_get_count(s);
	253	s->count_latched = s->rw_mode;
	254	}
	255	}
	256
b41a2cd1	257	static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	258	{
ec844b96	259	PITState *pit = opaque;
80cabfad FB	260	int channel, access;
	261	PITChannelState *s;
	262
	263	addr &= 3;
	264	if (addr == 3) {
	265	channel = val >> 6;
ec844b96 FB	266	if (channel == 3) {
	267	/* read back command */
	268	for(channel = 0; channel < 3; channel++) {
	269	s = &pit->channels[channel];
	270	if (val & (2 << channel)) {
	271	if (!(val & 0x20)) {
	272	pit_latch_count(s);
	273	}
	274	if (!(val & 0x10) && !s->status_latched) {
	275	/* status latch */
	276	/* XXX: add BCD and null count */
74475455	277	s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) \|
ec844b96 FB	278	(s->rw_mode << 4) \|
	279	(s->mode << 1) \|
	280	s->bcd;
	281	s->status_latched = 1;
	282	}
	283	}
	284	}
	285	} else {
	286	s = &pit->channels[channel];
	287	access = (val >> 4) & 3;
	288	if (access == 0) {
	289	pit_latch_count(s);
	290	} else {
	291	s->rw_mode = access;
	292	s->read_state = access;
	293	s->write_state = access;
	294
	295	s->mode = (val >> 1) & 7;
	296	s->bcd = val & 1;
	297	/* XXX: update irq timer ? */
	298	}
80cabfad FB	299	}
80cabfad FB	300	} else {
ec844b96 FB	301	s = &pit->channels[addr];
	302	switch(s->write_state) {
	303	default:
80cabfad FB	304	case RW_STATE_LSB:
	305	pit_load_count(s, val);
	306	break;
	307	case RW_STATE_MSB:
	308	pit_load_count(s, val << 8);
	309	break;
	310	case RW_STATE_WORD0:
ec844b96 FB	311	s->write_latch = val;
	312	s->write_state = RW_STATE_WORD1;
	313	break;
80cabfad	314	case RW_STATE_WORD1:
ec844b96 FB	315	pit_load_count(s, s->write_latch \| (val << 8));
ec844b96 FB	316	s->write_state = RW_STATE_WORD0;
80cabfad FB	317	break;
	318	}
	319	}
	320	}
	321
b41a2cd1	322	static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
80cabfad	323	{
ec844b96	324	PITState *pit = opaque;
80cabfad FB	325	int ret, count;
80cabfad FB	326	PITChannelState *s;
3b46e624	327
80cabfad	328	addr &= 3;
ec844b96 FB	329	s = &pit->channels[addr];
	330	if (s->status_latched) {
	331	s->status_latched = 0;
	332	ret = s->status;
	333	} else if (s->count_latched) {
	334	switch(s->count_latched) {
	335	default:
	336	case RW_STATE_LSB:
	337	ret = s->latched_count & 0xff;
	338	s->count_latched = 0;
	339	break;
	340	case RW_STATE_MSB:
80cabfad	341	ret = s->latched_count >> 8;
ec844b96 FB	342	s->count_latched = 0;
	343	break;
	344	case RW_STATE_WORD0:
80cabfad	345	ret = s->latched_count & 0xff;
ec844b96 FB	346	s->count_latched = RW_STATE_MSB;
	347	break;
	348	}
	349	} else {
	350	switch(s->read_state) {
	351	default:
	352	case RW_STATE_LSB:
	353	count = pit_get_count(s);
	354	ret = count & 0xff;
	355	break;
	356	case RW_STATE_MSB:
	357	count = pit_get_count(s);
	358	ret = (count >> 8) & 0xff;
	359	break;
	360	case RW_STATE_WORD0:
	361	count = pit_get_count(s);
	362	ret = count & 0xff;
	363	s->read_state = RW_STATE_WORD1;
	364	break;
	365	case RW_STATE_WORD1:
	366	count = pit_get_count(s);
	367	ret = (count >> 8) & 0xff;
	368	s->read_state = RW_STATE_WORD0;
	369	break;
	370	}
80cabfad FB	371	}
	372	return ret;
	373	}
	374
b0a21b53 FB	375	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
	376	{
	377	int64_t expire_time;
	378	int irq_level;
	379
	380	if (!s->irq_timer)
	381	return;
	382	expire_time = pit_get_next_transition_time(s, current_time);
ec844b96	383	irq_level = pit_get_out1(s, current_time);
d537cf6c	384	qemu_set_irq(s->irq, irq_level);
b0a21b53 FB	385	#ifdef DEBUG_PIT
b0a21b53 FB	386	printf("irq_level=%d next_delay=%f\n",
5fafdf24	387	irq_level,
6ee093c9	388	(double)(expire_time - current_time) / get_ticks_per_sec());
b0a21b53 FB	389	#endif
	390	s->next_transition_time = expire_time;
	391	if (expire_time != -1)
	392	qemu_mod_timer(s->irq_timer, expire_time);
	393	else
	394	qemu_del_timer(s->irq_timer);
	395	}
	396
	397	static void pit_irq_timer(void *opaque)
	398	{
	399	PITChannelState *s = opaque;
	400
	401	pit_irq_timer_update(s, s->next_transition_time);
	402	}
	403
5122b431 JQ	404	static const VMStateDescription vmstate_pit_channel = {
	405	.name = "pit channel",
	406	.version_id = 2,
	407	.minimum_version_id = 2,
	408	.minimum_version_id_old = 2,
	409	.fields = (VMStateField []) {
	410	VMSTATE_INT32(count, PITChannelState),
	411	VMSTATE_UINT16(latched_count, PITChannelState),
	412	VMSTATE_UINT8(count_latched, PITChannelState),
	413	VMSTATE_UINT8(status_latched, PITChannelState),
	414	VMSTATE_UINT8(status, PITChannelState),
	415	VMSTATE_UINT8(read_state, PITChannelState),
	416	VMSTATE_UINT8(write_state, PITChannelState),
	417	VMSTATE_UINT8(write_latch, PITChannelState),
	418	VMSTATE_UINT8(rw_mode, PITChannelState),
	419	VMSTATE_UINT8(mode, PITChannelState),
	420	VMSTATE_UINT8(bcd, PITChannelState),
	421	VMSTATE_UINT8(gate, PITChannelState),
	422	VMSTATE_INT64(count_load_time, PITChannelState),
	423	VMSTATE_INT64(next_transition_time, PITChannelState),
	424	VMSTATE_END_OF_LIST()
b0a21b53	425	}
5122b431	426	};
b0a21b53	427
5122b431	428	static int pit_load_old(QEMUFile f, void opaque, int version_id)
b0a21b53	429	{
ec844b96	430	PITState *pit = opaque;
b0a21b53 FB	431	PITChannelState *s;
b0a21b53 FB	432	int i;
3b46e624	433
b0a21b53 FB	434	if (version_id != 1)
	435	return -EINVAL;
	436
	437	for(i = 0; i < 3; i++) {
ec844b96	438	s = &pit->channels[i];
bee8d684	439	s->count=qemu_get_be32(f);
b0a21b53	440	qemu_get_be16s(f, &s->latched_count);
ec844b96 FB	441	qemu_get_8s(f, &s->count_latched);
	442	qemu_get_8s(f, &s->status_latched);
	443	qemu_get_8s(f, &s->status);
	444	qemu_get_8s(f, &s->read_state);
	445	qemu_get_8s(f, &s->write_state);
	446	qemu_get_8s(f, &s->write_latch);
	447	qemu_get_8s(f, &s->rw_mode);
b0a21b53 FB	448	qemu_get_8s(f, &s->mode);
	449	qemu_get_8s(f, &s->bcd);
	450	qemu_get_8s(f, &s->gate);
bee8d684	451	s->count_load_time=qemu_get_be64(f);
b0a21b53	452	if (s->irq_timer) {
bee8d684	453	s->next_transition_time=qemu_get_be64(f);
b0a21b53 FB	454	qemu_get_timer(f, s->irq_timer);
	455	}
	456	}
	457	return 0;
	458	}
	459
5122b431 JQ	460	static const VMStateDescription vmstate_pit = {
	461	.name = "i8254",
	462	.version_id = 2,
	463	.minimum_version_id = 2,
	464	.minimum_version_id_old = 1,
	465	.load_state_old = pit_load_old,
	466	.fields = (VMStateField []) {
	467	VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState),
	468	VMSTATE_TIMER(channels[0].irq_timer, PITState),
	469	VMSTATE_END_OF_LIST()
	470	}
	471	};
	472
64d7e9a4	473	static void pit_reset(DeviceState *dev)
80cabfad	474	{
64d7e9a4	475	PITState *pit = container_of(dev, PITState, dev.qdev);
80cabfad FB	476	PITChannelState *s;
	477	int i;
	478
	479	for(i = 0;i < 3; i++) {
ec844b96	480	s = &pit->channels[i];
80cabfad FB	481	s->mode = 3;
	482	s->gate = (i != 2);
	483	pit_load_count(s, 0);
	484	}
d7d02e3c FB	485	}
d7d02e3c FB	486
16b29ae1 AL	487	/* When HPET is operating in legacy mode, i8254 timer0 is disabled */
	488	void hpet_pit_disable(void) {
	489	PITChannelState *s;
	490	s = &pit_state.channels[0];
e0dd114c AL	491	if (s->irq_timer)
e0dd114c AL	492	qemu_del_timer(s->irq_timer);
16b29ae1 AL	493	}
16b29ae1 AL	494
c50c2d68	495	/* When HPET is reset or leaving legacy mode, it must reenable i8254
16b29ae1 AL	496	* timer 0
	497	*/
	498
	499	void hpet_pit_enable(void)
	500	{
	501	PITState *pit = &pit_state;
	502	PITChannelState *s;
	503	s = &pit->channels[0];
	504	s->mode = 3;
	505	s->gate = 1;
	506	pit_load_count(s, 0);
	507	}
	508
64d7e9a4	509	static int pit_initfn(ISADevice *dev)
d7d02e3c	510	{
64d7e9a4	511	PITState *pit = DO_UPCAST(PITState, dev, dev);
d7d02e3c FB	512	PITChannelState *s;
	513
	514	s = &pit->channels[0];
	515	/* the timer 0 is connected to an IRQ */
74475455	516	s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
ee951a37	517	s->irq = isa_get_irq(pit->irq);
80cabfad	518
64d7e9a4 BS	519	register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
	520	register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
	521	isa_init_ioport(dev, pit->iobase);
d7d02e3c	522
ca22a3a3 JK	523	qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
ca22a3a3 JK	524
64d7e9a4 BS	525	return 0;
	526	}
	527
	528	static ISADeviceInfo pit_info = {
	529	.qdev.name = "isa-pit",
	530	.qdev.size = sizeof(PITState),
	531	.qdev.vmsd = &vmstate_pit,
	532	.qdev.reset = pit_reset,
	533	.qdev.no_user = 1,
	534	.init = pit_initfn,
	535	.qdev.props = (Property[]) {
	536	DEFINE_PROP_UINT32("irq", PITState, irq, -1),
	537	DEFINE_PROP_HEX32("iobase", PITState, iobase, -1),
	538	DEFINE_PROP_END_OF_LIST(),
	539	},
	540	};
	541
	542	static void pit_register(void)
	543	{
	544	isa_qdev_register(&pit_info);
80cabfad	545	}
64d7e9a4	546	device_init(pit_register)