[qemu.git] / hw / arm / nrf51_soc.c

/*
 * Nordic Semiconductor nRF51 SoC
 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
 *
 * Copyright 2018 Joel Stanley <[email protected]>
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
#include "hw/sysbus.h"
#include "hw/misc/unimp.h"
#include "exec/address-spaces.h"
#include "qemu/log.h"
#include "cpu.h"

#include "hw/arm/nrf51.h"
#include "hw/arm/nrf51_soc.h"

/*
 * The size and base is for the NRF51822 part. If other parts
 * are supported in the future, add a sub-class of NRF51SoC for
 * the specific variants
 */
#define NRF51822_FLASH_PAGES    256
#define NRF51822_SRAM_PAGES     16
#define NRF51822_FLASH_SIZE     (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
#define NRF51822_SRAM_SIZE      (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)

#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)

static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
                  __func__, addr, size);
    return 1;
}

static void clock_write(void *opaque, hwaddr addr, uint64_t data,
                        unsigned int size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
                  __func__, addr, data, size);
}

static const MemoryRegionOps clock_ops = {
    .read = clock_read,
    .write = clock_write
};


static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
{
    NRF51State *s = NRF51_SOC(dev_soc);
    MemoryRegion *mr;
    Error *err = NULL;
    uint8_t i = 0;
    hwaddr base_addr = 0;

    if (!s->board_memory) {
        error_setg(errp, "memory property was not set");
        return;
    }

    object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err)) {
        error_propagate(errp, err);
        return;
    }

    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);

    memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);

    /* UART */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err)) {
        error_propagate(errp, err);
        return;
    }
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu),
                       BASE_TO_IRQ(NRF51_UART_BASE)));

    /* RNG */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err)) {
        error_propagate(errp, err);
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu),
                       BASE_TO_IRQ(NRF51_RNG_BASE)));

    /* UICR, FICR, NVMC, FLASH */
    object_property_set_uint(OBJECT(&s->nvm), "flash-size", s->flash_size,
                             &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), &err)) {
        error_propagate(errp, err);
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
    memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
    memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
    memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);

    /* GPIO */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err)) {
        error_propagate(errp, err);
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);

    /* Pass all GPIOs to the SOC layer so they are available to the board */
    qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);

    /* TIMER */
    for (i = 0; i < NRF51_NUM_TIMERS; i++) {
        object_property_set_uint(OBJECT(&s->timer[i]), "id", i, &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err)) {
            error_propagate(errp, err);
            return;
        }

        base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->cpu),
                                            BASE_TO_IRQ(base_addr)));
    }

    /* STUB Peripherals */
    memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
                          "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
    memory_region_add_subregion_overlap(&s->container,
                                        NRF51_IOMEM_BASE, &s->clock, -1);

    create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
                                NRF51_IOMEM_SIZE);
    create_unimplemented_device("nrf51_soc.private",
                                NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
}

static void nrf51_soc_init(Object *obj)
{
    uint8_t i = 0;

    NRF51State *s = NRF51_SOC(obj);

    memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);

    object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
                         ARM_CPU_TYPE_NAME("cortex-m0"));
    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);

    object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
    object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");

    object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);

    object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);

    object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);

    for (i = 0; i < NRF51_NUM_TIMERS; i++) {
        object_initialize_child(obj, "timer[*]", &s->timer[i],
                                TYPE_NRF51_TIMER);

    }
}

static Property nrf51_soc_properties[] = {
    DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
    DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
                       NRF51822_FLASH_SIZE),
    DEFINE_PROP_END_OF_LIST(),
};

static void nrf51_soc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = nrf51_soc_realize;
    device_class_set_props(dc, nrf51_soc_properties);
}

static const TypeInfo nrf51_soc_info = {
    .name          = TYPE_NRF51_SOC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(NRF51State),
    .instance_init = nrf51_soc_init,
    .class_init    = nrf51_soc_class_init,
};

static void nrf51_soc_types(void)
{
    type_register_static(&nrf51_soc_info);
}
type_init(nrf51_soc_types)
Commit	Line	Data
673b2d42 JS	1	/*
	2	* Nordic Semiconductor nRF51 SoC
	3	* http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
	4	*
	5	* Copyright 2018 Joel Stanley <[email protected]>
	6	*
	7	* This code is licensed under the GPL version 2 or later. See
	8	* the COPYING file in the top-level directory.
	9	*/
	10
	11	#include "qemu/osdep.h"
	12	#include "qapi/error.h"
12ec8bd5	13	#include "hw/arm/boot.h"
673b2d42	14	#include "hw/sysbus.h"
673b2d42 JS	15	#include "hw/misc/unimp.h"
673b2d42 JS	16	#include "exec/address-spaces.h"
673b2d42 JS	17	#include "qemu/log.h"
	18	#include "cpu.h"
	19
659b85e4	20	#include "hw/arm/nrf51.h"
673b2d42 JS	21	#include "hw/arm/nrf51_soc.h"
673b2d42 JS	22
673b2d42 JS	23	/*
	24	* The size and base is for the NRF51822 part. If other parts
	25	* are supported in the future, add a sub-class of NRF51SoC for
	26	* the specific variants
	27	*/
4d744b25 SG	28	#define NRF51822_FLASH_PAGES 256
	29	#define NRF51822_SRAM_PAGES 16
	30	#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
	31	#define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
673b2d42	32
b0014913 JS	33	#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
b0014913 JS	34
b39dced6 SG	35	static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
	36	{
	37	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
	38	__func__, addr, size);
	39	return 1;
	40	}
	41
	42	static void clock_write(void *opaque, hwaddr addr, uint64_t data,
	43	unsigned int size)
	44	{
	45	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
	46	__func__, addr, data, size);
	47	}
	48
	49	static const MemoryRegionOps clock_ops = {
	50	.read = clock_read,
	51	.write = clock_write
	52	};
	53
	54
673b2d42 JS	55	static void nrf51_soc_realize(DeviceState dev_soc, Error *errp)
	56	{
	57	NRF51State *s = NRF51_SOC(dev_soc);
b0014913	58	MemoryRegion *mr;
673b2d42	59	Error *err = NULL;
60facd90 SG	60	uint8_t i = 0;
60facd90 SG	61	hwaddr base_addr = 0;
673b2d42 JS	62
	63	if (!s->board_memory) {
	64	error_setg(errp, "memory property was not set");
	65	return;
	66	}
	67
5325cc34	68	object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
c24d9716	69	&error_abort);
118bfd76	70	if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err)) {
673b2d42 JS	71	error_propagate(errp, err);
	72	return;
	73	}
	74
	75	memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
	76
287a7f6e	77	memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
287a7f6e	78	&err);
673b2d42 JS	79	if (err) {
	80	error_propagate(errp, err);
	81	return;
	82	}
659b85e4	83	memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
673b2d42	84
b0014913	85	/* UART */
118bfd76	86	if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err)) {
b0014913 JS	87	error_propagate(errp, err);
	88	return;
	89	}
	90	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
659b85e4	91	memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
b0014913 JS	92	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
b0014913 JS	93	qdev_get_gpio_in(DEVICE(&s->cpu),
659b85e4	94	BASE_TO_IRQ(NRF51_UART_BASE)));
b0014913	95
f30890de	96	/* RNG */
118bfd76	97	if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err)) {
f30890de SG	98	error_propagate(errp, err);
	99	return;
	100	}
	101
	102	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
	103	memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
	104	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
	105	qdev_get_gpio_in(DEVICE(&s->cpu),
	106	BASE_TO_IRQ(NRF51_RNG_BASE)));
	107
4d744b25	108	/* UICR, FICR, NVMC, FLASH */
5325cc34	109	object_property_set_uint(OBJECT(&s->nvm), "flash-size", s->flash_size,
4d744b25 SG	110	&err);
	111	if (err) {
	112	error_propagate(errp, err);
	113	return;
	114	}
	115
118bfd76	116	if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), &err)) {
4d744b25 SG	117	error_propagate(errp, err);
	118	return;
	119	}
	120
	121	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
	122	memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
	123	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
	124	memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
	125	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
	126	memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
	127	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
	128	memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
	129
bb42c4cb	130	/* GPIO */
118bfd76	131	if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err)) {
bb42c4cb SG	132	error_propagate(errp, err);
	133	return;
	134	}
	135
	136	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
	137	memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
	138
	139	/* Pass all GPIOs to the SOC layer so they are available to the board */
	140	qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
	141
60facd90 SG	142	/* TIMER */
60facd90 SG	143	for (i = 0; i < NRF51_NUM_TIMERS; i++) {
5325cc34	144	object_property_set_uint(OBJECT(&s->timer[i]), "id", i, &err);
27d6dea3 PMD	145	if (err) {
	146	error_propagate(errp, err);
	147	return;
	148	}
118bfd76	149	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err)) {
60facd90 SG	150	error_propagate(errp, err);
	151	return;
	152	}
	153
54595a57	154	base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
60facd90 SG	155
	156	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
	157	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
	158	qdev_get_gpio_in(DEVICE(&s->cpu),
	159	BASE_TO_IRQ(base_addr)));
	160	}
	161
b39dced6	162	/* STUB Peripherals */
32b9523a	163	memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
54595a57	164	"nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
b39dced6 SG	165	memory_region_add_subregion_overlap(&s->container,
	166	NRF51_IOMEM_BASE, &s->clock, -1);
	167
659b85e4 SG	168	create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
659b85e4 SG	169	NRF51_IOMEM_SIZE);
673b2d42	170	create_unimplemented_device("nrf51_soc.private",
659b85e4	171	NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
673b2d42 JS	172	}
	173
	174	static void nrf51_soc_init(Object *obj)
	175	{
60facd90 SG	176	uint8_t i = 0;
60facd90 SG	177
673b2d42 JS	178	NRF51State *s = NRF51_SOC(obj);
	179
	180	memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
	181
db873cc5	182	object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
673b2d42 JS	183	qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
	184	ARM_CPU_TYPE_NAME("cortex-m0"));
	185	qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
b0014913	186
db873cc5	187	object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
d2623129	188	object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
f30890de	189
db873cc5	190	object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
bb42c4cb	191
db873cc5	192	object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
4d744b25	193
db873cc5	194	object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
60facd90 SG	195
60facd90 SG	196	for (i = 0; i < NRF51_NUM_TIMERS; i++) {
db873cc5 MA	197	object_initialize_child(obj, "timer[*]", &s->timer[i],
db873cc5 MA	198	TYPE_NRF51_TIMER);
60facd90 SG	199
60facd90 SG	200	}
673b2d42 JS	201	}
	202
	203	static Property nrf51_soc_properties[] = {
	204	DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
	205	MemoryRegion *),
	206	DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
	207	DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
	208	NRF51822_FLASH_SIZE),
	209	DEFINE_PROP_END_OF_LIST(),
	210	};
	211
	212	static void nrf51_soc_class_init(ObjectClass klass, void data)
	213	{
	214	DeviceClass *dc = DEVICE_CLASS(klass);
	215
	216	dc->realize = nrf51_soc_realize;
4f67d30b	217	device_class_set_props(dc, nrf51_soc_properties);
673b2d42 JS	218	}
	219
	220	static const TypeInfo nrf51_soc_info = {
	221	.name = TYPE_NRF51_SOC,
	222	.parent = TYPE_SYS_BUS_DEVICE,
	223	.instance_size = sizeof(NRF51State),
	224	.instance_init = nrf51_soc_init,
	225	.class_init = nrf51_soc_class_init,
	226	};
	227
	228	static void nrf51_soc_types(void)
	229	{
	230	type_register_static(&nrf51_soc_info);
	231	}
	232	type_init(nrf51_soc_types)