[qemu.git] / hw / acpi.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "i2c.h"
#include "smbus.h"

//#define DEBUG

/* i82731AB (PIIX4) compatible power management function */
#define PM_FREQ 3579545

#define ACPI_DBG_IO_ADDR  0xb044

typedef struct PIIX4PMState {
    PCIDevice dev;
    uint16_t pmsts;
    uint16_t pmen;
    uint16_t pmcntrl;
    uint8_t apmc;
    uint8_t apms;
    QEMUTimer *tmr_timer;
    int64_t tmr_overflow_time;
    i2c_bus *smbus;
    uint8_t smb_stat;
    uint8_t smb_ctl;
    uint8_t smb_cmd;
    uint8_t smb_addr;
    uint8_t smb_data0;
    uint8_t smb_data1;
    uint8_t smb_data[32];
    uint8_t smb_index;
} PIIX4PMState;

#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)

#define SCI_EN (1 << 0)

#define SUS_EN (1 << 13)

#define ACPI_ENABLE 0xf1
#define ACPI_DISABLE 0xf0

#define SMBHSTSTS 0x00
#define SMBHSTCNT 0x02
#define SMBHSTCMD 0x03
#define SMBHSTADD 0x04
#define SMBHSTDAT0 0x05
#define SMBHSTDAT1 0x06
#define SMBBLKDAT 0x07

static uint32_t get_pmtmr(PIIX4PMState *s)
{
    uint32_t d;
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
    return d & 0xffffff;
}

static int get_pmsts(PIIX4PMState *s)
{
    int64_t d;
    int pmsts;
    pmsts = s->pmsts;
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
    if (d >= s->tmr_overflow_time)
        s->pmsts |= TMROF_EN;
    return pmsts;
}

static void pm_update_sci(PIIX4PMState *s)
{
    int sci_level, pmsts;
    int64_t expire_time;

    pmsts = get_pmsts(s);
    sci_level = (((pmsts & s->pmen) &
                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
    qemu_set_irq(s->dev.irq[0], sci_level);
    /* schedule a timer interruption if needed */
    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
        expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
        qemu_mod_timer(s->tmr_timer, expire_time);
    } else {
        qemu_del_timer(s->tmr_timer);
    }
}

static void pm_tmr_timer(void *opaque)
{
    PIIX4PMState *s = opaque;
    pm_update_sci(s);
}

static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        {
            int64_t d;
            int pmsts;
            pmsts = get_pmsts(s);
            if (pmsts & val & TMROF_EN) {
                /* if TMRSTS is reset, then compute the new overflow time */
                d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
            }
            s->pmsts &= ~val;
            pm_update_sci(s);
        }
        break;
    case 0x02:
        s->pmen = val;
        pm_update_sci(s);
        break;
    case 0x04:
        {
            int sus_typ;
            s->pmcntrl = val & ~(SUS_EN);
            if (val & SUS_EN) {
                /* change suspend type */
                sus_typ = (val >> 10) & 3;
                switch(sus_typ) {
                case 0: /* soft power off */
                    qemu_system_shutdown_request();
                    break;
                default:
                    break;
                }
            }
        }
        break;
    default:
        break;
    }
#ifdef DEBUG
    printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
#endif
}

static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        val = get_pmsts(s);
        break;
    case 0x02:
        val = s->pmen;
        break;
    case 0x04:
        val = s->pmcntrl;
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
#endif
    return val;
}

static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
    //    PIIX4PMState *s = opaque;
    addr &= 0x3f;
#ifdef DEBUG
    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
#endif
}

static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x08:
        val = get_pmtmr(s);
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
#endif
    return val;
}

static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 1;
#ifdef DEBUG
    printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
#endif
    if (addr == 0) {
        s->apmc = val;

        /* ACPI specs 3.0, 4.7.2.5 */
        if (val == ACPI_ENABLE) {
            s->pmcntrl |= SCI_EN;
        } else if (val == ACPI_DISABLE) {
            s->pmcntrl &= ~SCI_EN;
        }

        if (s->dev.config[0x5b] & (1 << 1)) {
            cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
        }
    } else {
        s->apms = val;
    }
}

static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 1;
    if (addr == 0) {
        val = s->apmc;
    } else {
        val = s->apms;
    }
#ifdef DEBUG
    printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
#endif
    return val;
}

static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
{
#if defined(DEBUG)
    printf("ACPI: DBG: 0x%08x\n", val);
#endif
}

static void smb_transaction(PIIX4PMState *s)
{
    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
    uint8_t read = s->smb_addr & 0x01;
    uint8_t cmd = s->smb_cmd;
    uint8_t addr = s->smb_addr >> 1;
    i2c_bus *bus = s->smbus;

#ifdef DEBUG
    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
#endif
    switch(prot) {
    case 0x0:
        smbus_quick_command(bus, addr, read);
        break;
    case 0x1:
        if (read) {
            s->smb_data0 = smbus_receive_byte(bus, addr);
        } else {
            smbus_send_byte(bus, addr, cmd);
        }
        break;
    case 0x2:
        if (read) {
            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
        } else {
            smbus_write_byte(bus, addr, cmd, s->smb_data0);
        }
        break;
    case 0x3:
        if (read) {
            uint16_t val;
            val = smbus_read_word(bus, addr, cmd);
            s->smb_data0 = val;
            s->smb_data1 = val >> 8;
        } else {
            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
        }
        break;
    case 0x5:
        if (read) {
            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
        } else {
            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
        }
        break;
    default:
        goto error;
    }
    return;

  error:
    s->smb_stat |= 0x04;
}

static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 0x3f;
#ifdef DEBUG
    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    case SMBHSTSTS:
        s->smb_stat = 0;
        s->smb_index = 0;
        break;
    case SMBHSTCNT:
        s->smb_ctl = val;
        if (val & 0x40)
            smb_transaction(s);
        break;
    case SMBHSTCMD:
        s->smb_cmd = val;
        break;
    case SMBHSTADD:
        s->smb_addr = val;
        break;
    case SMBHSTDAT0:
        s->smb_data0 = val;
        break;
    case SMBHSTDAT1:
        s->smb_data1 = val;
        break;
    case SMBBLKDAT:
        s->smb_data[s->smb_index++] = val;
        if (s->smb_index > 31)
            s->smb_index = 0;
        break;
    default:
        break;
    }
}

static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case SMBHSTSTS:
        val = s->smb_stat;
        break;
    case SMBHSTCNT:
        s->smb_index = 0;
        val = s->smb_ctl & 0x1f;
        break;
    case SMBHSTCMD:
        val = s->smb_cmd;
        break;
    case SMBHSTADD:
        val = s->smb_addr;
        break;
    case SMBHSTDAT0:
        val = s->smb_data0;
        break;
    case SMBHSTDAT1:
        val = s->smb_data1;
        break;
    case SMBBLKDAT:
        val = s->smb_data[s->smb_index++];
        if (s->smb_index > 31)
            s->smb_index = 0;
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
#endif
    return val;
}

static void pm_io_space_update(PIIX4PMState *s)
{
    uint32_t pm_io_base;

    if (s->dev.config[0x80] & 1) {
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
        pm_io_base &= 0xffc0;

        /* XXX: need to improve memory and ioport allocation */
#if defined(DEBUG)
        printf("PM: mapping to 0x%x\n", pm_io_base);
#endif
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
    }
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
    if (address == 0x80)
        pm_io_space_update((PIIX4PMState *)d);
}

static void pm_save(QEMUFile* f,void *opaque)
{
    PIIX4PMState *s = opaque;

    pci_device_save(&s->dev, f);

    qemu_put_be16s(f, &s->pmsts);
    qemu_put_be16s(f, &s->pmen);
    qemu_put_be16s(f, &s->pmcntrl);
    qemu_put_8s(f, &s->apmc);
    qemu_put_8s(f, &s->apms);
    qemu_put_timer(f, s->tmr_timer);
    qemu_put_be64s(f, &s->tmr_overflow_time);
}

static int pm_load(QEMUFile* f,void* opaque,int version_id)
{
    PIIX4PMState *s = opaque;
    int ret;

    if (version_id > 1)
        return -EINVAL;

    ret = pci_device_load(&s->dev, f);
    if (ret < 0)
        return ret;

    qemu_get_be16s(f, &s->pmsts);
    qemu_get_be16s(f, &s->pmen);
    qemu_get_be16s(f, &s->pmcntrl);
    qemu_get_8s(f, &s->apmc);
    qemu_get_8s(f, &s->apms);
    qemu_get_timer(f, s->tmr_timer);
    qemu_get_be64s(f, &s->tmr_overflow_time);

    pm_io_space_update(s);

    return 0;
}

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
    PIIX4PMState *s;
    uint8_t *pci_conf;

    s = (PIIX4PMState *)pci_register_device(bus,
                                         "PM", sizeof(PIIX4PMState),
                                         devfn, NULL, pm_write_config);
    pci_conf = s->dev.config;
    pci_conf[0x00] = 0x86;
    pci_conf[0x01] = 0x80;
    pci_conf[0x02] = 0x13;
    pci_conf[0x03] = 0x71;
    pci_conf[0x06] = 0x80;
    pci_conf[0x07] = 0x02;
    pci_conf[0x08] = 0x00; // revision number
    pci_conf[0x09] = 0x00;
    pci_conf[0x0a] = 0x80; // other bridge device
    pci_conf[0x0b] = 0x06; // bridge device
    pci_conf[0x0e] = 0x00; // header_type
    pci_conf[0x3d] = 0x01; // interrupt pin 1

    pci_conf[0x40] = 0x01; /* PM io base read only bit */

    register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
    register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);

    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);

    /* XXX: which specification is used ? The i82731AB has different
       mappings */
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
    pci_conf[0x63] = 0x60;
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
	(serial_hds[1] != NULL ? 0x90 : 0);

    pci_conf[0x90] = smb_io_base | 1;
    pci_conf[0x91] = smb_io_base >> 8;
    pci_conf[0xd2] = 0x09;
    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);

    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);

    register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);

    s->smbus = i2c_init_bus();
    return s->smbus;
}
Commit	Line	Data
6515b203 FB	1	/*
6515b203 FB	2	* ACPI implementation
5fafdf24	3	*
6515b203	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
6515b203 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
87ecb68b PB	19	#include "hw.h"
	20	#include "pc.h"
	21	#include "pci.h"
	22	#include "qemu-timer.h"
	23	#include "sysemu.h"
	24	#include "i2c.h"
	25	#include "smbus.h"
6515b203 FB	26
	27	//#define DEBUG
	28
	29	/* i82731AB (PIIX4) compatible power management function */
	30	#define PM_FREQ 3579545
	31
6515b203 FB	32	#define ACPI_DBG_IO_ADDR 0xb044
	33
	34	typedef struct PIIX4PMState {
	35	PCIDevice dev;
	36	uint16_t pmsts;
	37	uint16_t pmen;
	38	uint16_t pmcntrl;
ab1e34ad FB	39	uint8_t apmc;
ab1e34ad FB	40	uint8_t apms;
6515b203 FB	41	QEMUTimer *tmr_timer;
6515b203 FB	42	int64_t tmr_overflow_time;
0ff596d0	43	i2c_bus *smbus;
3fffc223 TS	44	uint8_t smb_stat;
	45	uint8_t smb_ctl;
	46	uint8_t smb_cmd;
	47	uint8_t smb_addr;
	48	uint8_t smb_data0;
	49	uint8_t smb_data1;
	50	uint8_t smb_data[32];
	51	uint8_t smb_index;
6515b203 FB	52	} PIIX4PMState;
	53
	54	#define RTC_EN (1 << 10)
	55	#define PWRBTN_EN (1 << 8)
	56	#define GBL_EN (1 << 5)
	57	#define TMROF_EN (1 << 0)
	58
	59	#define SCI_EN (1 << 0)
	60
	61	#define SUS_EN (1 << 13)
	62
24bc1cbc TS	63	#define ACPI_ENABLE 0xf1
	64	#define ACPI_DISABLE 0xf0
	65
3fffc223 TS	66	#define SMBHSTSTS 0x00
	67	#define SMBHSTCNT 0x02
	68	#define SMBHSTCMD 0x03
	69	#define SMBHSTADD 0x04
	70	#define SMBHSTDAT0 0x05
	71	#define SMBHSTDAT1 0x06
	72	#define SMBBLKDAT 0x07
	73
6515b203 FB	74	static uint32_t get_pmtmr(PIIX4PMState *s)
	75	{
	76	uint32_t d;
	77	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	78	return d & 0xffffff;
	79	}
	80
	81	static int get_pmsts(PIIX4PMState *s)
	82	{
	83	int64_t d;
	84	int pmsts;
	85	pmsts = s->pmsts;
	86	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	87	if (d >= s->tmr_overflow_time)
	88	s->pmsts \|= TMROF_EN;
	89	return pmsts;
	90	}
	91
	92	static void pm_update_sci(PIIX4PMState *s)
	93	{
	94	int sci_level, pmsts;
	95	int64_t expire_time;
3b46e624	96
6515b203	97	pmsts = get_pmsts(s);
5fafdf24	98	sci_level = (((pmsts & s->pmen) &
6515b203	99	(RTC_EN \| PWRBTN_EN \| GBL_EN \| TMROF_EN)) != 0);
d537cf6c	100	qemu_set_irq(s->dev.irq[0], sci_level);
6515b203 FB	101	/* schedule a timer interruption if needed */
	102	if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
	103	expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
	104	qemu_mod_timer(s->tmr_timer, expire_time);
	105	} else {
	106	qemu_del_timer(s->tmr_timer);
	107	}
	108	}
	109
	110	static void pm_tmr_timer(void *opaque)
	111	{
	112	PIIX4PMState *s = opaque;
	113	pm_update_sci(s);
	114	}
	115
	116	static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	117	{
	118	PIIX4PMState *s = opaque;
	119	addr &= 0x3f;
	120	switch(addr) {
	121	case 0x00:
	122	{
	123	int64_t d;
	124	int pmsts;
	125	pmsts = get_pmsts(s);
	126	if (pmsts & val & TMROF_EN) {
	127	/* if TMRSTS is reset, then compute the new overflow time */
	128	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	129	s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
	130	}
	131	s->pmsts &= ~val;
	132	pm_update_sci(s);
	133	}
	134	break;
	135	case 0x02:
	136	s->pmen = val;
	137	pm_update_sci(s);
	138	break;
	139	case 0x04:
	140	{
	141	int sus_typ;
	142	s->pmcntrl = val & ~(SUS_EN);
	143	if (val & SUS_EN) {
	144	/* change suspend type */
	145	sus_typ = (val >> 10) & 3;
	146	switch(sus_typ) {
	147	case 0: /* soft power off */
	148	qemu_system_shutdown_request();
	149	break;
	150	default:
	151	break;
	152	}
	153	}
	154	}
	155	break;
	156	default:
	157	break;
	158	}
	159	#ifdef DEBUG
	160	printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
	161	#endif
	162	}
	163
	164	static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
165	{
166	PIIX4PMState *s = opaque;
167	uint32_t val;
168
169	addr &= 0x3f;
170	switch(addr) {
171	case 0x00:
172	val = get_pmsts(s);
173	break;
174	case 0x02:
175	val = s->pmen;
176	break;
177	case 0x04:
178	val = s->pmcntrl;
179	break;
180	default:
181	val = 0;
182	break;
183	}
184	#ifdef DEBUG
185	printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
186	#endif
187	return val;
188	}
189
190	static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
191	{
192	// PIIX4PMState *s = opaque;
193	addr &= 0x3f;
194	#ifdef DEBUG
195	printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
196	#endif
197	}
198
199	static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
200	{
201	PIIX4PMState *s = opaque;
202	uint32_t val;
203
204	addr &= 0x3f;
205	switch(addr) {
206	case 0x08:
207	val = get_pmtmr(s);
208	break;
209	default:
210	val = 0;
211	break;
212	}
213	#ifdef DEBUG
214	printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
215	#endif
216	return val;
217	}
218
ab1e34ad	219	static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
6515b203 FB	220	{
6515b203 FB	221	PIIX4PMState *s = opaque;
ab1e34ad	222	addr &= 1;
6515b203	223	#ifdef DEBUG
ab1e34ad	224	printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
6515b203	225	#endif
ab1e34ad FB	226	if (addr == 0) {
ab1e34ad FB	227	s->apmc = val;
24bc1cbc TS	228
	229	/* ACPI specs 3.0, 4.7.2.5 */
	230	if (val == ACPI_ENABLE) {
	231	s->pmcntrl \|= SCI_EN;
	232	} else if (val == ACPI_DISABLE) {
	233	s->pmcntrl &= ~SCI_EN;
	234	}
	235
47d02f6d FB	236	if (s->dev.config[0x5b] & (1 << 1)) {
47d02f6d FB	237	cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
ab1e34ad	238	}
ab1e34ad FB	239	} else {
ab1e34ad FB	240	s->apms = val;
6515b203 FB	241	}
	242	}
	243
ab1e34ad FB	244	static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
	245	{
	246	PIIX4PMState *s = opaque;
	247	uint32_t val;
3b46e624	248
ab1e34ad FB	249	addr &= 1;
	250	if (addr == 0) {
	251	val = s->apmc;
	252	} else {
	253	val = s->apms;
	254	}
	255	#ifdef DEBUG
	256	printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
	257	#endif
	258	return val;
	259	}
	260
6515b203 FB	261	static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
	262	{
	263	#if defined(DEBUG)
	264	printf("ACPI: DBG: 0x%08x\n", val);
	265	#endif
	266	}
	267
3fffc223 TS	268	static void smb_transaction(PIIX4PMState *s)
	269	{
	270	uint8_t prot = (s->smb_ctl >> 2) & 0x07;
	271	uint8_t read = s->smb_addr & 0x01;
	272	uint8_t cmd = s->smb_cmd;
	273	uint8_t addr = s->smb_addr >> 1;
0ff596d0	274	i2c_bus *bus = s->smbus;
3fffc223 TS	275
	276	#ifdef DEBUG
	277	printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
	278	#endif
3fffc223 TS	279	switch(prot) {
3fffc223 TS	280	case 0x0:
0ff596d0	281	smbus_quick_command(bus, addr, read);
3fffc223 TS	282	break;
	283	case 0x1:
	284	if (read) {
0ff596d0 PB	285	s->smb_data0 = smbus_receive_byte(bus, addr);
	286	} else {
	287	smbus_send_byte(bus, addr, cmd);
3fffc223 TS	288	}
	289	break;
	290	case 0x2:
	291	if (read) {
0ff596d0 PB	292	s->smb_data0 = smbus_read_byte(bus, addr, cmd);
	293	} else {
	294	smbus_write_byte(bus, addr, cmd, s->smb_data0);
3fffc223 TS	295	}
	296	break;
	297	case 0x3:
	298	if (read) {
	299	uint16_t val;
0ff596d0	300	val = smbus_read_word(bus, addr, cmd);
3fffc223 TS	301	s->smb_data0 = val;
3fffc223 TS	302	s->smb_data1 = val >> 8;
0ff596d0 PB	303	} else {
0ff596d0 PB	304	smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) \| s->smb_data0);
3fffc223 TS	305	}
	306	break;
	307	case 0x5:
	308	if (read) {
0ff596d0 PB	309	s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
	310	} else {
	311	smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
3fffc223 TS	312	}
	313	break;
	314	default:
	315	goto error;
	316	}
	317	return;
	318
	319	error:
	320	s->smb_stat \|= 0x04;
	321	}
	322
	323	static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	324	{
	325	PIIX4PMState *s = opaque;
	326	addr &= 0x3f;
	327	#ifdef DEBUG
	328	printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
	329	#endif
	330	switch(addr) {
	331	case SMBHSTSTS:
	332	s->smb_stat = 0;
	333	s->smb_index = 0;
	334	break;
	335	case SMBHSTCNT:
	336	s->smb_ctl = val;
	337	if (val & 0x40)
	338	smb_transaction(s);
	339	break;
	340	case SMBHSTCMD:
	341	s->smb_cmd = val;
	342	break;
	343	case SMBHSTADD:
	344	s->smb_addr = val;
	345	break;
	346	case SMBHSTDAT0:
	347	s->smb_data0 = val;
	348	break;
	349	case SMBHSTDAT1:
	350	s->smb_data1 = val;
	351	break;
	352	case SMBBLKDAT:
	353	s->smb_data[s->smb_index++] = val;
	354	if (s->smb_index > 31)
	355	s->smb_index = 0;
	356	break;
	357	default:
	358	break;
	359	}
	360	}
	361
	362	static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
	363	{
	364	PIIX4PMState *s = opaque;
	365	uint32_t val;
	366
	367	addr &= 0x3f;
	368	switch(addr) {
	369	case SMBHSTSTS:
	370	val = s->smb_stat;
	371	break;
	372	case SMBHSTCNT:
	373	s->smb_index = 0;
	374	val = s->smb_ctl & 0x1f;
	375	break;
376	case SMBHSTCMD:
377	val = s->smb_cmd;
378	break;
379	case SMBHSTADD:
380	val = s->smb_addr;
381	break;
382	case SMBHSTDAT0:
383	val = s->smb_data0;
384	break;
385	case SMBHSTDAT1:
386	val = s->smb_data1;
387	break;
388	case SMBBLKDAT:
389	val = s->smb_data[s->smb_index++];
390	if (s->smb_index > 31)
391	s->smb_index = 0;
392	break;
393	default:
394	val = 0;
395	break;
396	}
397	#ifdef DEBUG
398	printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
399	#endif
400	return val;
401	}
402
ab1e34ad FB	403	static void pm_io_space_update(PIIX4PMState *s)
	404	{
	405	uint32_t pm_io_base;
	406
	407	if (s->dev.config[0x80] & 1) {
	408	pm_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x40));
bf367b54	409	pm_io_base &= 0xffc0;
ab1e34ad FB	410
	411	/* XXX: need to improve memory and ioport allocation */
	412	#if defined(DEBUG)
	413	printf("PM: mapping to 0x%x\n", pm_io_base);
	414	#endif
	415	register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
	416	register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
	417	register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
	418	register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
	419	}
	420	}
	421
5fafdf24	422	static void pm_write_config(PCIDevice *d,
ab1e34ad FB	423	uint32_t address, uint32_t val, int len)
	424	{
	425	pci_default_write_config(d, address, val, len);
	426	if (address == 0x80)
	427	pm_io_space_update((PIIX4PMState *)d);
	428	}
	429
	430	static void pm_save(QEMUFile* f,void *opaque)
	431	{
	432	PIIX4PMState *s = opaque;
	433
	434	pci_device_save(&s->dev, f);
	435
	436	qemu_put_be16s(f, &s->pmsts);
	437	qemu_put_be16s(f, &s->pmen);
	438	qemu_put_be16s(f, &s->pmcntrl);
	439	qemu_put_8s(f, &s->apmc);
	440	qemu_put_8s(f, &s->apms);
	441	qemu_put_timer(f, s->tmr_timer);
	442	qemu_put_be64s(f, &s->tmr_overflow_time);
	443	}
	444
	445	static int pm_load(QEMUFile* f,void* opaque,int version_id)
	446	{
	447	PIIX4PMState *s = opaque;
	448	int ret;
	449
	450	if (version_id > 1)
	451	return -EINVAL;
	452
	453	ret = pci_device_load(&s->dev, f);
	454	if (ret < 0)
	455	return ret;
	456
	457	qemu_get_be16s(f, &s->pmsts);
	458	qemu_get_be16s(f, &s->pmen);
	459	qemu_get_be16s(f, &s->pmcntrl);
	460	qemu_get_8s(f, &s->apmc);
	461	qemu_get_8s(f, &s->apms);
	462	qemu_get_timer(f, s->tmr_timer);
	463	qemu_get_be64s(f, &s->tmr_overflow_time);
	464
	465	pm_io_space_update(s);
	466
	467	return 0;
	468	}
	469
7b717336	470	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base)
6515b203 FB	471	{
	472	PIIX4PMState *s;
	473	uint8_t *pci_conf;
6515b203 FB	474
	475	s = (PIIX4PMState *)pci_register_device(bus,
	476	"PM", sizeof(PIIX4PMState),
ab1e34ad	477	devfn, NULL, pm_write_config);
6515b203 FB	478	pci_conf = s->dev.config;
	479	pci_conf[0x00] = 0x86;
	480	pci_conf[0x01] = 0x80;
	481	pci_conf[0x02] = 0x13;
7ef4da1c	482	pci_conf[0x03] = 0x71;
bf367b54 TS	483	pci_conf[0x06] = 0x80;
bf367b54 TS	484	pci_conf[0x07] = 0x02;
6515b203 FB	485	pci_conf[0x08] = 0x00; // revision number
	486	pci_conf[0x09] = 0x00;
	487	pci_conf[0x0a] = 0x80; // other bridge device
	488	pci_conf[0x0b] = 0x06; // bridge device
	489	pci_conf[0x0e] = 0x00; // header_type
	490	pci_conf[0x3d] = 0x01; // interrupt pin 1
3b46e624	491
ab1e34ad	492	pci_conf[0x40] = 0x01; /* PM io base read only bit */
3b46e624	493
ab1e34ad FB	494	register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
	495	register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
	496
6515b203 FB	497	register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
6515b203 FB	498
1ce549ab FB	499	/* XXX: which specification is used ? The i82731AB has different
	500	mappings */
	501	pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) \| 0x10;
	502	pci_conf[0x63] = 0x60;
	503	pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) \|
	504	(serial_hds[1] != NULL ? 0x90 : 0);
	505
3fffc223 TS	506	pci_conf[0x90] = smb_io_base \| 1;
	507	pci_conf[0x91] = smb_io_base >> 8;
	508	pci_conf[0xd2] = 0x09;
	509	register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
	510	register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
	511
6515b203	512	s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
6515b203	513
ab1e34ad	514	register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
3fffc223	515
0ff596d0 PB	516	s->smbus = i2c_init_bus();
0ff596d0 PB	517	return s->smbus;
6515b203	518	}