[qemu.git] / hw / display / virtio-gpu-3d.c

/*
 * Virtio GPU Device
 *
 * Copyright Red Hat, Inc. 2013-2014
 *
 * Authors:
 *     Dave Airlie <[email protected]>
 *     Gerd Hoffmann <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/iov.h"
#include "trace.h"
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-gpu.h"

#ifdef CONFIG_VIRGL

#include <virglrenderer.h>

static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;

static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
                                         struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_resource_create_2d c2d;
    struct virgl_renderer_resource_create_args args;

    VIRTIO_GPU_FILL_CMD(c2d);
    trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
                                       c2d.width, c2d.height);

    args.handle = c2d.resource_id;
    args.target = 2;
    args.format = c2d.format;
    args.bind = (1 << 1);
    args.width = c2d.width;
    args.height = c2d.height;
    args.depth = 1;
    args.array_size = 1;
    args.last_level = 0;
    args.nr_samples = 0;
    args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
    virgl_renderer_resource_create(&args, NULL, 0);
}

static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
                                         struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_resource_create_3d c3d;
    struct virgl_renderer_resource_create_args args;

    VIRTIO_GPU_FILL_CMD(c3d);
    trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
                                       c3d.width, c3d.height, c3d.depth);

    args.handle = c3d.resource_id;
    args.target = c3d.target;
    args.format = c3d.format;
    args.bind = c3d.bind;
    args.width = c3d.width;
    args.height = c3d.height;
    args.depth = c3d.depth;
    args.array_size = c3d.array_size;
    args.last_level = c3d.last_level;
    args.nr_samples = c3d.nr_samples;
    args.flags = c3d.flags;
    virgl_renderer_resource_create(&args, NULL, 0);
}

static void virgl_cmd_resource_unref(VirtIOGPU *g,
                                     struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_resource_unref unref;
    struct iovec *res_iovs = NULL;
    int num_iovs = 0;

    VIRTIO_GPU_FILL_CMD(unref);
    trace_virtio_gpu_cmd_res_unref(unref.resource_id);

    virgl_renderer_resource_detach_iov(unref.resource_id,
                                       &res_iovs,
                                       &num_iovs);
    if (res_iovs != NULL && num_iovs != 0) {
        virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
    }
    virgl_renderer_resource_unref(unref.resource_id);
}

static void virgl_cmd_context_create(VirtIOGPU *g,
                                     struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_ctx_create cc;

    VIRTIO_GPU_FILL_CMD(cc);
    trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
                                    cc.debug_name);

    virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
                                  cc.debug_name);
}

static void virgl_cmd_context_destroy(VirtIOGPU *g,
                                      struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_ctx_destroy cd;

    VIRTIO_GPU_FILL_CMD(cd);
    trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);

    virgl_renderer_context_destroy(cd.hdr.ctx_id);
}

static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
                                int width, int height)
{
    if (!g->parent_obj.scanout[idx].con) {
        return;
    }

    dpy_gl_update(g->parent_obj.scanout[idx].con, x, y, width, height);
}

static void virgl_cmd_resource_flush(VirtIOGPU *g,
                                     struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_resource_flush rf;
    int i;

    VIRTIO_GPU_FILL_CMD(rf);
    trace_virtio_gpu_cmd_res_flush(rf.resource_id,
                                   rf.r.width, rf.r.height, rf.r.x, rf.r.y);

    for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
        if (g->parent_obj.scanout[i].resource_id != rf.resource_id) {
            continue;
        }
        virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
    }
}

static void virgl_cmd_set_scanout(VirtIOGPU *g,
                                  struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_set_scanout ss;
    struct virgl_renderer_resource_info info;
    int ret;

    VIRTIO_GPU_FILL_CMD(ss);
    trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
                                     ss.r.width, ss.r.height, ss.r.x, ss.r.y);

    if (ss.scanout_id >= g->parent_obj.conf.max_outputs) {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
                      __func__, ss.scanout_id);
        cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
        return;
    }
    g->parent_obj.enable = 1;

    memset(&info, 0, sizeof(info));

    if (ss.resource_id && ss.r.width && ss.r.height) {
        ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
        if (ret == -1) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: illegal resource specified %d\n",
                          __func__, ss.resource_id);
            cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
            return;
        }
        qemu_console_resize(g->parent_obj.scanout[ss.scanout_id].con,
                            ss.r.width, ss.r.height);
        virgl_renderer_force_ctx_0();
        dpy_gl_scanout_texture(
            g->parent_obj.scanout[ss.scanout_id].con, info.tex_id,
            info.flags & 1 /* FIXME: Y_0_TOP */,
            info.width, info.height,
            ss.r.x, ss.r.y, ss.r.width, ss.r.height);
    } else {
        if (ss.scanout_id != 0) {
            dpy_gfx_replace_surface(
                g->parent_obj.scanout[ss.scanout_id].con, NULL);
        }
        dpy_gl_scanout_disable(g->parent_obj.scanout[ss.scanout_id].con);
    }
    g->parent_obj.scanout[ss.scanout_id].resource_id = ss.resource_id;
}

static void virgl_cmd_submit_3d(VirtIOGPU *g,
                                struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_cmd_submit cs;
    void *buf;
    size_t s;

    VIRTIO_GPU_FILL_CMD(cs);
    trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);

    buf = g_malloc(cs.size);
    s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
                   sizeof(cs), buf, cs.size);
    if (s != cs.size) {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
                      __func__, s, cs.size);
        cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
        goto out;
    }

    if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
        g->stats.req_3d++;
        g->stats.bytes_3d += cs.size;
    }

    virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);

out:
    g_free(buf);
}

static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
                                          struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_transfer_to_host_2d t2d;
    struct virtio_gpu_box box;

    VIRTIO_GPU_FILL_CMD(t2d);
    trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);

    box.x = t2d.r.x;
    box.y = t2d.r.y;
    box.z = 0;
    box.w = t2d.r.width;
    box.h = t2d.r.height;
    box.d = 1;

    virgl_renderer_transfer_write_iov(t2d.resource_id,
                                      0,
                                      0,
                                      0,
                                      0,
                                      (struct virgl_box *)&box,
                                      t2d.offset, NULL, 0);
}

static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
                                          struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_transfer_host_3d t3d;

    VIRTIO_GPU_FILL_CMD(t3d);
    trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);

    virgl_renderer_transfer_write_iov(t3d.resource_id,
                                      t3d.hdr.ctx_id,
                                      t3d.level,
                                      t3d.stride,
                                      t3d.layer_stride,
                                      (struct virgl_box *)&t3d.box,
                                      t3d.offset, NULL, 0);
}

static void
virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
                                struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_transfer_host_3d tf3d;

    VIRTIO_GPU_FILL_CMD(tf3d);
    trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);

    virgl_renderer_transfer_read_iov(tf3d.resource_id,
                                     tf3d.hdr.ctx_id,
                                     tf3d.level,
                                     tf3d.stride,
                                     tf3d.layer_stride,
                                     (struct virgl_box *)&tf3d.box,
                                     tf3d.offset, NULL, 0);
}


static void virgl_resource_attach_backing(VirtIOGPU *g,
                                          struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_resource_attach_backing att_rb;
    struct iovec *res_iovs;
    int ret;

    VIRTIO_GPU_FILL_CMD(att_rb);
    trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);

    ret = virtio_gpu_create_mapping_iov(g, &att_rb, cmd, NULL, &res_iovs);
    if (ret != 0) {
        cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
        return;
    }

    ret = virgl_renderer_resource_attach_iov(att_rb.resource_id,
                                             res_iovs, att_rb.nr_entries);

    if (ret != 0)
        virtio_gpu_cleanup_mapping_iov(g, res_iovs, att_rb.nr_entries);
}

static void virgl_resource_detach_backing(VirtIOGPU *g,
                                          struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_resource_detach_backing detach_rb;
    struct iovec *res_iovs = NULL;
    int num_iovs = 0;

    VIRTIO_GPU_FILL_CMD(detach_rb);
    trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);

    virgl_renderer_resource_detach_iov(detach_rb.resource_id,
                                       &res_iovs,
                                       &num_iovs);
    if (res_iovs == NULL || num_iovs == 0) {
        return;
    }
    virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
}


static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
                                          struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_ctx_resource att_res;

    VIRTIO_GPU_FILL_CMD(att_res);
    trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
                                        att_res.resource_id);

    virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
}

static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
                                          struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_ctx_resource det_res;

    VIRTIO_GPU_FILL_CMD(det_res);
    trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
                                        det_res.resource_id);

    virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
}

static void virgl_cmd_get_capset_info(VirtIOGPU *g,
                                      struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_get_capset_info info;
    struct virtio_gpu_resp_capset_info resp;

    VIRTIO_GPU_FILL_CMD(info);

    memset(&resp, 0, sizeof(resp));
    if (info.capset_index == 0) {
        resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
        virgl_renderer_get_cap_set(resp.capset_id,
                                   &resp.capset_max_version,
                                   &resp.capset_max_size);
    } else if (info.capset_index == 1) {
        resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
        virgl_renderer_get_cap_set(resp.capset_id,
                                   &resp.capset_max_version,
                                   &resp.capset_max_size);
    } else {
        resp.capset_max_version = 0;
        resp.capset_max_size = 0;
    }
    resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
    virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
}

static void virgl_cmd_get_capset(VirtIOGPU *g,
                                 struct virtio_gpu_ctrl_command *cmd)
{
    struct virtio_gpu_get_capset gc;
    struct virtio_gpu_resp_capset *resp;
    uint32_t max_ver, max_size;
    VIRTIO_GPU_FILL_CMD(gc);

    virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
                               &max_size);
    if (!max_size) {
        cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
        return;
    }

    resp = g_malloc0(sizeof(*resp) + max_size);
    resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
    virgl_renderer_fill_caps(gc.capset_id,
                             gc.capset_version,
                             (void *)resp->capset_data);
    virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
    g_free(resp);
}

void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
                                      struct virtio_gpu_ctrl_command *cmd)
{
    VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);

    virgl_renderer_force_ctx_0();
    switch (cmd->cmd_hdr.type) {
    case VIRTIO_GPU_CMD_CTX_CREATE:
        virgl_cmd_context_create(g, cmd);
        break;
    case VIRTIO_GPU_CMD_CTX_DESTROY:
        virgl_cmd_context_destroy(g, cmd);
        break;
    case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
        virgl_cmd_create_resource_2d(g, cmd);
        break;
    case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
        virgl_cmd_create_resource_3d(g, cmd);
        break;
    case VIRTIO_GPU_CMD_SUBMIT_3D:
        virgl_cmd_submit_3d(g, cmd);
        break;
    case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
        virgl_cmd_transfer_to_host_2d(g, cmd);
        break;
    case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
        virgl_cmd_transfer_to_host_3d(g, cmd);
        break;
    case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
        virgl_cmd_transfer_from_host_3d(g, cmd);
        break;
    case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
        virgl_resource_attach_backing(g, cmd);
        break;
    case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
        virgl_resource_detach_backing(g, cmd);
        break;
    case VIRTIO_GPU_CMD_SET_SCANOUT:
        virgl_cmd_set_scanout(g, cmd);
        break;
    case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
        virgl_cmd_resource_flush(g, cmd);
       break;
    case VIRTIO_GPU_CMD_RESOURCE_UNREF:
        virgl_cmd_resource_unref(g, cmd);
        break;
    case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
        /* TODO add security */
        virgl_cmd_ctx_attach_resource(g, cmd);
        break;
    case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
        /* TODO add security */
        virgl_cmd_ctx_detach_resource(g, cmd);
        break;
    case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
        virgl_cmd_get_capset_info(g, cmd);
        break;
    case VIRTIO_GPU_CMD_GET_CAPSET:
        virgl_cmd_get_capset(g, cmd);
        break;

    case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
        virtio_gpu_get_display_info(g, cmd);
        break;
    case VIRTIO_GPU_CMD_GET_EDID:
        virtio_gpu_get_edid(g, cmd);
        break;
    default:
        cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
        break;
    }

    if (cmd->finished) {
        return;
    }
    if (cmd->error) {
        fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
                cmd->cmd_hdr.type, cmd->error);
        virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
        return;
    }
    if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
        virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
        return;
    }

    trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
    virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
}

static void virgl_write_fence(void *opaque, uint32_t fence)
{
    VirtIOGPU *g = opaque;
    struct virtio_gpu_ctrl_command *cmd, *tmp;

    QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
        /*
         * the guest can end up emitting fences out of order
         * so we should check all fenced cmds not just the first one.
         */
        if (cmd->cmd_hdr.fence_id > fence) {
            continue;
        }
        trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
        virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
        QTAILQ_REMOVE(&g->fenceq, cmd, next);
        g_free(cmd);
        g->inflight--;
        if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
            fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
        }
    }
}

static virgl_renderer_gl_context
virgl_create_context(void *opaque, int scanout_idx,
                     struct virgl_renderer_gl_ctx_param *params)
{
    VirtIOGPU *g = opaque;
    QEMUGLContext ctx;
    QEMUGLParams qparams;

    qparams.major_ver = params->major_ver;
    qparams.minor_ver = params->minor_ver;

    ctx = dpy_gl_ctx_create(g->parent_obj.scanout[scanout_idx].con, &qparams);
    return (virgl_renderer_gl_context)ctx;
}

static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
{
    VirtIOGPU *g = opaque;
    QEMUGLContext qctx = (QEMUGLContext)ctx;

    dpy_gl_ctx_destroy(g->parent_obj.scanout[0].con, qctx);
}

static int virgl_make_context_current(void *opaque, int scanout_idx,
                                      virgl_renderer_gl_context ctx)
{
    VirtIOGPU *g = opaque;
    QEMUGLContext qctx = (QEMUGLContext)ctx;

    return dpy_gl_ctx_make_current(g->parent_obj.scanout[scanout_idx].con,
                                   qctx);
}

static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
    .version             = 1,
    .write_fence         = virgl_write_fence,
    .create_gl_context   = virgl_create_context,
    .destroy_gl_context  = virgl_destroy_context,
    .make_current        = virgl_make_context_current,
};

static void virtio_gpu_print_stats(void *opaque)
{
    VirtIOGPU *g = opaque;

    if (g->stats.requests) {
        fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
                g->stats.requests,
                g->stats.max_inflight,
                g->stats.req_3d,
                g->stats.bytes_3d);
        g->stats.requests     = 0;
        g->stats.max_inflight = 0;
        g->stats.req_3d       = 0;
        g->stats.bytes_3d     = 0;
    } else {
        fprintf(stderr, "stats: idle\r");
    }
    timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
}

static void virtio_gpu_fence_poll(void *opaque)
{
    VirtIOGPU *g = opaque;

    virgl_renderer_poll();
    virtio_gpu_process_cmdq(g);
    if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
        timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
    }
}

void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
{
    virtio_gpu_fence_poll(g);
}

void virtio_gpu_virgl_reset(VirtIOGPU *g)
{
    int i;

    /* virgl_renderer_reset() ??? */
    for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
        if (i != 0) {
            dpy_gfx_replace_surface(g->parent_obj.scanout[i].con, NULL);
        }
        dpy_gl_scanout_disable(g->parent_obj.scanout[i].con);
    }
}

int virtio_gpu_virgl_init(VirtIOGPU *g)
{
    int ret;

    ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
    if (ret != 0) {
        return ret;
    }

    g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
                                 virtio_gpu_fence_poll, g);

    if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
        g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
                                      virtio_gpu_print_stats, g);
        timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
    }
    return 0;
}

int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g)
{
    uint32_t capset2_max_ver, capset2_max_size;
    virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
                              &capset2_max_ver,
                              &capset2_max_size);

    return capset2_max_ver ? 2 : 1;
}

#endif /* CONFIG_VIRGL */
Commit	Line	Data
9d9e1521 GH	1	/*
	2	* Virtio GPU Device
	3	*
	4	* Copyright Red Hat, Inc. 2013-2014
	5	*
	6	* Authors:
	7	* Dave Airlie <[email protected]>
	8	* Gerd Hoffmann <[email protected]>
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	11	* See the COPYING file in the top-level directory.
	12	*/
	13
9b8bfe21	14	#include "qemu/osdep.h"
9d9e1521 GH	15	#include "qemu-common.h"
	16	#include "qemu/iov.h"
	17	#include "trace.h"
	18	#include "hw/virtio/virtio.h"
	19	#include "hw/virtio/virtio-gpu.h"
	20
	21	#ifdef CONFIG_VIRGL
	22
a9c94277	23	#include <virglrenderer.h>
9d9e1521 GH	24
	25	static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
	26
	27	static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
	28	struct virtio_gpu_ctrl_command *cmd)
	29	{
	30	struct virtio_gpu_resource_create_2d c2d;
	31	struct virgl_renderer_resource_create_args args;
	32
	33	VIRTIO_GPU_FILL_CMD(c2d);
	34	trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
	35	c2d.width, c2d.height);
	36
	37	args.handle = c2d.resource_id;
	38	args.target = 2;
	39	args.format = c2d.format;
	40	args.bind = (1 << 1);
	41	args.width = c2d.width;
	42	args.height = c2d.height;
	43	args.depth = 1;
	44	args.array_size = 1;
	45	args.last_level = 0;
	46	args.nr_samples = 0;
	47	args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
	48	virgl_renderer_resource_create(&args, NULL, 0);
	49	}
	50
	51	static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
	52	struct virtio_gpu_ctrl_command *cmd)
	53	{
	54	struct virtio_gpu_resource_create_3d c3d;
	55	struct virgl_renderer_resource_create_args args;
	56
	57	VIRTIO_GPU_FILL_CMD(c3d);
	58	trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
	59	c3d.width, c3d.height, c3d.depth);
	60
	61	args.handle = c3d.resource_id;
	62	args.target = c3d.target;
	63	args.format = c3d.format;
	64	args.bind = c3d.bind;
	65	args.width = c3d.width;
	66	args.height = c3d.height;
	67	args.depth = c3d.depth;
	68	args.array_size = c3d.array_size;
	69	args.last_level = c3d.last_level;
	70	args.nr_samples = c3d.nr_samples;
	71	args.flags = c3d.flags;
	72	virgl_renderer_resource_create(&args, NULL, 0);
	73	}
	74
	75	static void virgl_cmd_resource_unref(VirtIOGPU *g,
	76	struct virtio_gpu_ctrl_command *cmd)
	77	{
	78	struct virtio_gpu_resource_unref unref;
5e8e3c4c GH	79	struct iovec *res_iovs = NULL;
5e8e3c4c GH	80	int num_iovs = 0;
9d9e1521 GH	81
	82	VIRTIO_GPU_FILL_CMD(unref);
	83	trace_virtio_gpu_cmd_res_unref(unref.resource_id);
	84
5e8e3c4c GH	85	virgl_renderer_resource_detach_iov(unref.resource_id,
	86	&res_iovs,
	87	&num_iovs);
	88	if (res_iovs != NULL && num_iovs != 0) {
3bb68f79	89	virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
5e8e3c4c	90	}
9d9e1521 GH	91	virgl_renderer_resource_unref(unref.resource_id);
	92	}
	93
	94	static void virgl_cmd_context_create(VirtIOGPU *g,
	95	struct virtio_gpu_ctrl_command *cmd)
	96	{
	97	struct virtio_gpu_ctx_create cc;
	98
	99	VIRTIO_GPU_FILL_CMD(cc);
	100	trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
	101	cc.debug_name);
	102
	103	virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
	104	cc.debug_name);
	105	}
	106
	107	static void virgl_cmd_context_destroy(VirtIOGPU *g,
	108	struct virtio_gpu_ctrl_command *cmd)
	109	{
	110	struct virtio_gpu_ctx_destroy cd;
	111
	112	VIRTIO_GPU_FILL_CMD(cd);
	113	trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
	114
	115	virgl_renderer_context_destroy(cd.hdr.ctx_id);
	116	}
	117
	118	static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
	119	int width, int height)
	120	{
50d8e25e	121	if (!g->parent_obj.scanout[idx].con) {
9d9e1521 GH	122	return;
	123	}
	124
50d8e25e	125	dpy_gl_update(g->parent_obj.scanout[idx].con, x, y, width, height);
9d9e1521 GH	126	}
	127
	128	static void virgl_cmd_resource_flush(VirtIOGPU *g,
	129	struct virtio_gpu_ctrl_command *cmd)
	130	{
	131	struct virtio_gpu_resource_flush rf;
	132	int i;
	133
	134	VIRTIO_GPU_FILL_CMD(rf);
	135	trace_virtio_gpu_cmd_res_flush(rf.resource_id,
	136	rf.r.width, rf.r.height, rf.r.x, rf.r.y);
	137
50d8e25e MAL	138	for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
50d8e25e MAL	139	if (g->parent_obj.scanout[i].resource_id != rf.resource_id) {
9d9e1521 GH	140	continue;
	141	}
	142	virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
	143	}
	144	}
	145
	146	static void virgl_cmd_set_scanout(VirtIOGPU *g,
	147	struct virtio_gpu_ctrl_command *cmd)
	148	{
	149	struct virtio_gpu_set_scanout ss;
	150	struct virgl_renderer_resource_info info;
	151	int ret;
	152
	153	VIRTIO_GPU_FILL_CMD(ss);
	154	trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
	155	ss.r.width, ss.r.height, ss.r.x, ss.r.y);
	156
50d8e25e	157	if (ss.scanout_id >= g->parent_obj.conf.max_outputs) {
9d9e1521 GH	158	qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
	159	__func__, ss.scanout_id);
	160	cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
	161	return;
	162	}
50d8e25e	163	g->parent_obj.enable = 1;
9d9e1521 GH	164
	165	memset(&info, 0, sizeof(info));
	166
	167	if (ss.resource_id && ss.r.width && ss.r.height) {
	168	ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
	169	if (ret == -1) {
	170	qemu_log_mask(LOG_GUEST_ERROR,
	171	"%s: illegal resource specified %d\n",
	172	__func__, ss.resource_id);
	173	cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
	174	return;
	175	}
50d8e25e	176	qemu_console_resize(g->parent_obj.scanout[ss.scanout_id].con,
9d9e1521 GH	177	ss.r.width, ss.r.height);
9d9e1521 GH	178	virgl_renderer_force_ctx_0();
50d8e25e MAL	179	dpy_gl_scanout_texture(
	180	g->parent_obj.scanout[ss.scanout_id].con, info.tex_id,
	181	info.flags & 1 /* FIXME: Y_0_TOP */,
	182	info.width, info.height,
	183	ss.r.x, ss.r.y, ss.r.width, ss.r.height);
9d9e1521 GH	184	} else {
9d9e1521 GH	185	if (ss.scanout_id != 0) {
50d8e25e MAL	186	dpy_gfx_replace_surface(
50d8e25e MAL	187	g->parent_obj.scanout[ss.scanout_id].con, NULL);
9d9e1521	188	}
50d8e25e	189	dpy_gl_scanout_disable(g->parent_obj.scanout[ss.scanout_id].con);
9d9e1521	190	}
50d8e25e	191	g->parent_obj.scanout[ss.scanout_id].resource_id = ss.resource_id;
9d9e1521 GH	192	}
	193
	194	static void virgl_cmd_submit_3d(VirtIOGPU *g,
	195	struct virtio_gpu_ctrl_command *cmd)
	196	{
	197	struct virtio_gpu_cmd_submit cs;
	198	void *buf;
	199	size_t s;
	200
	201	VIRTIO_GPU_FILL_CMD(cs);
	202	trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
	203
	204	buf = g_malloc(cs.size);
	205	s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
	206	sizeof(cs), buf, cs.size);
	207	if (s != cs.size) {
	208	qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
	209	__func__, s, cs.size);
	210	cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
8d94c1ca	211	goto out;
9d9e1521 GH	212	}
9d9e1521 GH	213
50d8e25e	214	if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
9d9e1521 GH	215	g->stats.req_3d++;
	216	g->stats.bytes_3d += cs.size;
	217	}
	218
	219	virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
	220
8d94c1ca	221	out:
9d9e1521 GH	222	g_free(buf);
	223	}
	224
	225	static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
	226	struct virtio_gpu_ctrl_command *cmd)
	227	{
	228	struct virtio_gpu_transfer_to_host_2d t2d;
	229	struct virtio_gpu_box box;
	230
	231	VIRTIO_GPU_FILL_CMD(t2d);
	232	trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
	233
	234	box.x = t2d.r.x;
	235	box.y = t2d.r.y;
	236	box.z = 0;
	237	box.w = t2d.r.width;
	238	box.h = t2d.r.height;
	239	box.d = 1;
	240
	241	virgl_renderer_transfer_write_iov(t2d.resource_id,
	242	0,
	243	0,
	244	0,
	245	0,
	246	(struct virgl_box *)&box,
	247	t2d.offset, NULL, 0);
	248	}
	249
	250	static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
	251	struct virtio_gpu_ctrl_command *cmd)
	252	{
	253	struct virtio_gpu_transfer_host_3d t3d;
	254
	255	VIRTIO_GPU_FILL_CMD(t3d);
	256	trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
	257
	258	virgl_renderer_transfer_write_iov(t3d.resource_id,
	259	t3d.hdr.ctx_id,
	260	t3d.level,
	261	t3d.stride,
	262	t3d.layer_stride,
	263	(struct virgl_box *)&t3d.box,
	264	t3d.offset, NULL, 0);
	265	}
	266
	267	static void
	268	virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
	269	struct virtio_gpu_ctrl_command *cmd)
	270	{
	271	struct virtio_gpu_transfer_host_3d tf3d;
	272
	273	VIRTIO_GPU_FILL_CMD(tf3d);
	274	trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
	275
	276	virgl_renderer_transfer_read_iov(tf3d.resource_id,
	277	tf3d.hdr.ctx_id,
	278	tf3d.level,
	279	tf3d.stride,
	280	tf3d.layer_stride,
	281	(struct virgl_box *)&tf3d.box,
	282	tf3d.offset, NULL, 0);
	283	}
	284
	285
286	static void virgl_resource_attach_backing(VirtIOGPU *g,
287	struct virtio_gpu_ctrl_command *cmd)
288	{
289	struct virtio_gpu_resource_attach_backing att_rb;
290	struct iovec *res_iovs;
291	int ret;
292
293	VIRTIO_GPU_FILL_CMD(att_rb);
294	trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
295
3bb68f79	296	ret = virtio_gpu_create_mapping_iov(g, &att_rb, cmd, NULL, &res_iovs);
9d9e1521 GH	297	if (ret != 0) {
	298	cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
	299	return;
	300	}
	301
33243031 LQ	302	ret = virgl_renderer_resource_attach_iov(att_rb.resource_id,
	303	res_iovs, att_rb.nr_entries);
	304
	305	if (ret != 0)
3bb68f79	306	virtio_gpu_cleanup_mapping_iov(g, res_iovs, att_rb.nr_entries);
9d9e1521 GH	307	}
	308
	309	static void virgl_resource_detach_backing(VirtIOGPU *g,
	310	struct virtio_gpu_ctrl_command *cmd)
	311	{
	312	struct virtio_gpu_resource_detach_backing detach_rb;
	313	struct iovec *res_iovs = NULL;
	314	int num_iovs = 0;
	315
	316	VIRTIO_GPU_FILL_CMD(detach_rb);
	317	trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
	318
	319	virgl_renderer_resource_detach_iov(detach_rb.resource_id,
	320	&res_iovs,
	321	&num_iovs);
	322	if (res_iovs == NULL \|\| num_iovs == 0) {
	323	return;
	324	}
3bb68f79	325	virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
9d9e1521 GH	326	}
	327
	328
	329	static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
	330	struct virtio_gpu_ctrl_command *cmd)
	331	{
	332	struct virtio_gpu_ctx_resource att_res;
	333
	334	VIRTIO_GPU_FILL_CMD(att_res);
	335	trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
	336	att_res.resource_id);
	337
	338	virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
	339	}
	340
	341	static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
	342	struct virtio_gpu_ctrl_command *cmd)
	343	{
	344	struct virtio_gpu_ctx_resource det_res;
	345
	346	VIRTIO_GPU_FILL_CMD(det_res);
	347	trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
	348	det_res.resource_id);
	349
	350	virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
	351	}
	352
	353	static void virgl_cmd_get_capset_info(VirtIOGPU *g,
	354	struct virtio_gpu_ctrl_command *cmd)
	355	{
	356	struct virtio_gpu_get_capset_info info;
	357	struct virtio_gpu_resp_capset_info resp;
	358
	359	VIRTIO_GPU_FILL_CMD(info);
	360
42a8dadc	361	memset(&resp, 0, sizeof(resp));
9d9e1521 GH	362	if (info.capset_index == 0) {
	363	resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
	364	virgl_renderer_get_cap_set(resp.capset_id,
	365	&resp.capset_max_version,
	366	&resp.capset_max_size);
5643cc94 DA	367	} else if (info.capset_index == 1) {
	368	resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
	369	virgl_renderer_get_cap_set(resp.capset_id,
	370	&resp.capset_max_version,
	371	&resp.capset_max_size);
9d9e1521 GH	372	} else {
	373	resp.capset_max_version = 0;
	374	resp.capset_max_size = 0;
	375	}
	376	resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
	377	virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
	378	}
	379
	380	static void virgl_cmd_get_capset(VirtIOGPU *g,
	381	struct virtio_gpu_ctrl_command *cmd)
	382	{
	383	struct virtio_gpu_get_capset gc;
	384	struct virtio_gpu_resp_capset *resp;
	385	uint32_t max_ver, max_size;
	386	VIRTIO_GPU_FILL_CMD(gc);
	387
	388	virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
	389	&max_size);
abd7f08b PP	390	if (!max_size) {
	391	cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
	392	return;
	393	}
9d9e1521	394
85d9d044	395	resp = g_malloc0(sizeof(*resp) + max_size);
9d9e1521 GH	396	resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
	397	virgl_renderer_fill_caps(gc.capset_id,
	398	gc.capset_version,
	399	(void *)resp->capset_data);
	400	virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
	401	g_free(resp);
	402	}
	403
	404	void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
	405	struct virtio_gpu_ctrl_command *cmd)
	406	{
	407	VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
	408
	409	virgl_renderer_force_ctx_0();
	410	switch (cmd->cmd_hdr.type) {
	411	case VIRTIO_GPU_CMD_CTX_CREATE:
	412	virgl_cmd_context_create(g, cmd);
	413	break;
	414	case VIRTIO_GPU_CMD_CTX_DESTROY:
	415	virgl_cmd_context_destroy(g, cmd);
	416	break;
	417	case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
	418	virgl_cmd_create_resource_2d(g, cmd);
	419	break;
	420	case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
	421	virgl_cmd_create_resource_3d(g, cmd);
	422	break;
	423	case VIRTIO_GPU_CMD_SUBMIT_3D:
	424	virgl_cmd_submit_3d(g, cmd);
	425	break;
	426	case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
	427	virgl_cmd_transfer_to_host_2d(g, cmd);
	428	break;
	429	case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
	430	virgl_cmd_transfer_to_host_3d(g, cmd);
	431	break;
	432	case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
	433	virgl_cmd_transfer_from_host_3d(g, cmd);
	434	break;
	435	case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
	436	virgl_resource_attach_backing(g, cmd);
	437	break;
	438	case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
	439	virgl_resource_detach_backing(g, cmd);
	440	break;
	441	case VIRTIO_GPU_CMD_SET_SCANOUT:
	442	virgl_cmd_set_scanout(g, cmd);
	443	break;
	444	case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
	445	virgl_cmd_resource_flush(g, cmd);
	446	break;
	447	case VIRTIO_GPU_CMD_RESOURCE_UNREF:
	448	virgl_cmd_resource_unref(g, cmd);
	449	break;
	450	case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
	451	/* TODO add security */
	452	virgl_cmd_ctx_attach_resource(g, cmd);
	453	break;
	454	case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
	455	/* TODO add security */
	456	virgl_cmd_ctx_detach_resource(g, cmd);
	457	break;
	458	case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
	459	virgl_cmd_get_capset_info(g, cmd);
460	break;
461	case VIRTIO_GPU_CMD_GET_CAPSET:
462	virgl_cmd_get_capset(g, cmd);
463	break;
464
465	case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
466	virtio_gpu_get_display_info(g, cmd);
467	break;
1ed2cb32 GH	468	case VIRTIO_GPU_CMD_GET_EDID:
	469	virtio_gpu_get_edid(g, cmd);
	470	break;
9d9e1521 GH	471	default:
	472	cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
	473	break;
	474	}
	475
	476	if (cmd->finished) {
	477	return;
	478	}
	479	if (cmd->error) {
	480	fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
	481	cmd->cmd_hdr.type, cmd->error);
	482	virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
	483	return;
	484	}
	485	if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
	486	virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
	487	return;
	488	}
	489
	490	trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
	491	virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
	492	}
	493
	494	static void virgl_write_fence(void *opaque, uint32_t fence)
	495	{
	496	VirtIOGPU *g = opaque;
	497	struct virtio_gpu_ctrl_command cmd, tmp;
	498
	499	QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
	500	/*
7d37435b PB	501	* the guest can end up emitting fences out of order
	502	* so we should check all fenced cmds not just the first one.
	503	*/
9d9e1521 GH	504	if (cmd->cmd_hdr.fence_id > fence) {
	505	continue;
	506	}
	507	trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
	508	virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
	509	QTAILQ_REMOVE(&g->fenceq, cmd, next);
	510	g_free(cmd);
	511	g->inflight--;
50d8e25e	512	if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
9d9e1521 GH	513	fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
	514	}
	515	}
	516	}
	517
	518	static virgl_renderer_gl_context
	519	virgl_create_context(void *opaque, int scanout_idx,
	520	struct virgl_renderer_gl_ctx_param *params)
	521	{
	522	VirtIOGPU *g = opaque;
	523	QEMUGLContext ctx;
	524	QEMUGLParams qparams;
	525
	526	qparams.major_ver = params->major_ver;
	527	qparams.minor_ver = params->minor_ver;
	528
50d8e25e	529	ctx = dpy_gl_ctx_create(g->parent_obj.scanout[scanout_idx].con, &qparams);
9d9e1521 GH	530	return (virgl_renderer_gl_context)ctx;
	531	}
	532
	533	static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
	534	{
	535	VirtIOGPU *g = opaque;
	536	QEMUGLContext qctx = (QEMUGLContext)ctx;
	537
50d8e25e	538	dpy_gl_ctx_destroy(g->parent_obj.scanout[0].con, qctx);
9d9e1521 GH	539	}
	540
	541	static int virgl_make_context_current(void *opaque, int scanout_idx,
	542	virgl_renderer_gl_context ctx)
	543	{
	544	VirtIOGPU *g = opaque;
	545	QEMUGLContext qctx = (QEMUGLContext)ctx;
	546
50d8e25e MAL	547	return dpy_gl_ctx_make_current(g->parent_obj.scanout[scanout_idx].con,
50d8e25e MAL	548	qctx);
9d9e1521 GH	549	}
	550
	551	static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
	552	.version = 1,
	553	.write_fence = virgl_write_fence,
	554	.create_gl_context = virgl_create_context,
	555	.destroy_gl_context = virgl_destroy_context,
	556	.make_current = virgl_make_context_current,
	557	};
	558
	559	static void virtio_gpu_print_stats(void *opaque)
	560	{
	561	VirtIOGPU *g = opaque;
	562
	563	if (g->stats.requests) {
	564	fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
	565	g->stats.requests,
	566	g->stats.max_inflight,
	567	g->stats.req_3d,
	568	g->stats.bytes_3d);
	569	g->stats.requests = 0;
	570	g->stats.max_inflight = 0;
	571	g->stats.req_3d = 0;
	572	g->stats.bytes_3d = 0;
	573	} else {
	574	fprintf(stderr, "stats: idle\r");
	575	}
	576	timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
	577	}
	578
	579	static void virtio_gpu_fence_poll(void *opaque)
	580	{
	581	VirtIOGPU *g = opaque;
	582
	583	virgl_renderer_poll();
0c55a1cf GH	584	virtio_gpu_process_cmdq(g);
0c55a1cf GH	585	if (!QTAILQ_EMPTY(&g->cmdq) \|\| !QTAILQ_EMPTY(&g->fenceq)) {
9d9e1521 GH	586	timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
	587	}
	588	}
	589
	590	void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
	591	{
	592	virtio_gpu_fence_poll(g);
	593	}
	594
	595	void virtio_gpu_virgl_reset(VirtIOGPU *g)
	596	{
	597	int i;
	598
	599	/* virgl_renderer_reset() ??? */
50d8e25e	600	for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
9d9e1521	601	if (i != 0) {
50d8e25e	602	dpy_gfx_replace_surface(g->parent_obj.scanout[i].con, NULL);
9d9e1521	603	}
50d8e25e	604	dpy_gl_scanout_disable(g->parent_obj.scanout[i].con);
9d9e1521 GH	605	}
	606	}
	607
	608	int virtio_gpu_virgl_init(VirtIOGPU *g)
	609	{
	610	int ret;
	611
	612	ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
	613	if (ret != 0) {
	614	return ret;
	615	}
	616
	617	g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
	618	virtio_gpu_fence_poll, g);
	619
50d8e25e	620	if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
9d9e1521 GH	621	g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
	622	virtio_gpu_print_stats, g);
	623	timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
	624	}
	625	return 0;
	626	}
	627
5643cc94 DA	628	int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g)
	629	{
	630	uint32_t capset2_max_ver, capset2_max_size;
	631	virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
	632	&capset2_max_ver,
	633	&capset2_max_size);
	634
	635	return capset2_max_ver ? 2 : 1;
	636	}
	637
9d9e1521	638	#endif /* CONFIG_VIRGL */