[qemu.git] / target / arm / kvm-consts.h

/*
 * KVM ARM ABI constant definitions
 *
 * Copyright (c) 2013 Linaro Limited
 *
 * Provide versions of KVM constant defines that can be used even
 * when CONFIG_KVM is not set and we don't have access to the
 * KVM headers. If CONFIG_KVM is set, we do a compile-time check
 * that we haven't got out of sync somehow.
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */
#ifndef ARM_KVM_CONSTS_H
#define ARM_KVM_CONSTS_H

#ifdef CONFIG_KVM
#include <linux/kvm.h>
#include <linux/psci.h>

#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)

#else

#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)

#endif

#define CP_REG_SIZE_SHIFT 52
#define CP_REG_SIZE_MASK       0x00f0000000000000ULL
#define CP_REG_SIZE_U32        0x0020000000000000ULL
#define CP_REG_SIZE_U64        0x0030000000000000ULL
#define CP_REG_ARM             0x4000000000000000ULL
#define CP_REG_ARCH_MASK       0xff00000000000000ULL

MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT);
MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK);
MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32);
MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64);
MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM);
MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK);

#define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
#define QEMU_PSCI_0_1_FN(n) (QEMU_PSCI_0_1_FN_BASE + (n))
#define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
#define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1)
#define QEMU_PSCI_0_1_FN_CPU_ON QEMU_PSCI_0_1_FN(2)
#define QEMU_PSCI_0_1_FN_MIGRATE QEMU_PSCI_0_1_FN(3)

MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND);
MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF);
MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_ON, KVM_PSCI_FN_CPU_ON);
MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);

#define QEMU_PSCI_0_2_FN_BASE 0x84000000
#define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n))

#define QEMU_PSCI_0_2_64BIT 0x40000000
#define QEMU_PSCI_0_2_FN64_BASE \
        (QEMU_PSCI_0_2_FN_BASE + QEMU_PSCI_0_2_64BIT)
#define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n))

#define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0)
#define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1)
#define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2)
#define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3)
#define QEMU_PSCI_0_2_FN_AFFINITY_INFO QEMU_PSCI_0_2_FN(4)
#define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5)
#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE QEMU_PSCI_0_2_FN(6)
#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN(7)
#define QEMU_PSCI_0_2_FN_SYSTEM_OFF QEMU_PSCI_0_2_FN(8)
#define QEMU_PSCI_0_2_FN_SYSTEM_RESET QEMU_PSCI_0_2_FN(9)

#define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1)
#define QEMU_PSCI_0_2_FN64_CPU_OFF QEMU_PSCI_0_2_FN64(2)
#define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3)
#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)
#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)

MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);

/* PSCI v0.2 return values used by TCG emulation of PSCI */

/* No Trusted OS migration to worry about when offlining CPUs */
#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED        2

/* We implement version 0.2 only */
#define QEMU_PSCI_0_2_RET_VERSION_0_2                       2

MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,
               (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2)));

/* PSCI return values (inclusive of all PSCI versions) */
#define QEMU_PSCI_RET_SUCCESS                     0
#define QEMU_PSCI_RET_NOT_SUPPORTED               -1
#define QEMU_PSCI_RET_INVALID_PARAMS              -2
#define QEMU_PSCI_RET_DENIED                      -3
#define QEMU_PSCI_RET_ALREADY_ON                  -4
#define QEMU_PSCI_RET_ON_PENDING                  -5
#define QEMU_PSCI_RET_INTERNAL_FAILURE            -6
#define QEMU_PSCI_RET_NOT_PRESENT                 -7
#define QEMU_PSCI_RET_DISABLED                    -8

MISMATCH_CHECK(QEMU_PSCI_RET_SUCCESS, PSCI_RET_SUCCESS);
MISMATCH_CHECK(QEMU_PSCI_RET_NOT_SUPPORTED, PSCI_RET_NOT_SUPPORTED);
MISMATCH_CHECK(QEMU_PSCI_RET_INVALID_PARAMS, PSCI_RET_INVALID_PARAMS);
MISMATCH_CHECK(QEMU_PSCI_RET_DENIED, PSCI_RET_DENIED);
MISMATCH_CHECK(QEMU_PSCI_RET_ALREADY_ON, PSCI_RET_ALREADY_ON);
MISMATCH_CHECK(QEMU_PSCI_RET_ON_PENDING, PSCI_RET_ON_PENDING);
MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE);
MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT);
MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);

/* Note that KVM uses overlapping values for AArch32 and AArch64
 * target CPU numbers. AArch32 targets:
 */
#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0
#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1

/* AArch64 targets: */
#define QEMU_KVM_ARM_TARGET_AEM_V8 0
#define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4

/* There's no kernel define for this: sentinel value which
 * matches no KVM target value for either 64 or 32 bit
 */
#define QEMU_KVM_ARM_TARGET_NONE UINT_MAX

#ifdef TARGET_AARCH64
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8);
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8);
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57);
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA);
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
#else
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15);
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7);
#endif

#define CP_REG_ARM64                   0x6000000000000000ULL
#define CP_REG_ARM_COPROC_MASK         0x000000000FFF0000
#define CP_REG_ARM_COPROC_SHIFT        16
#define CP_REG_ARM64_SYSREG            (0x0013 << CP_REG_ARM_COPROC_SHIFT)
#define CP_REG_ARM64_SYSREG_OP0_MASK   0x000000000000c000
#define CP_REG_ARM64_SYSREG_OP0_SHIFT  14
#define CP_REG_ARM64_SYSREG_OP1_MASK   0x0000000000003800
#define CP_REG_ARM64_SYSREG_OP1_SHIFT  11
#define CP_REG_ARM64_SYSREG_CRN_MASK   0x0000000000000780
#define CP_REG_ARM64_SYSREG_CRN_SHIFT  7
#define CP_REG_ARM64_SYSREG_CRM_MASK   0x0000000000000078
#define CP_REG_ARM64_SYSREG_CRM_SHIFT  3
#define CP_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
#define CP_REG_ARM64_SYSREG_OP2_SHIFT  0

/* No kernel define but it's useful to QEMU */
#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)

#ifdef TARGET_AARCH64
MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK);
MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT);
#endif

#undef MISMATCH_CHECK

#endif
Commit	Line	Data
72b0cd35 PM	1	/*
	2	* KVM ARM ABI constant definitions
	3	*
	4	* Copyright (c) 2013 Linaro Limited
	5	*
	6	* Provide versions of KVM constant defines that can be used even
	7	* when CONFIG_KVM is not set and we don't have access to the
	8	* KVM headers. If CONFIG_KVM is set, we do a compile-time check
	9	* that we haven't got out of sync somehow.
	10	*
	11	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	12	* See the COPYING file in the top-level directory.
	13	*/
	14	#ifndef ARM_KVM_CONSTS_H
	15	#define ARM_KVM_CONSTS_H
	16
	17	#ifdef CONFIG_KVM
72b0cd35	18	#include <linux/kvm.h>
863714ba	19	#include <linux/psci.h>
72b0cd35 PM	20
	21	#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
	22
	23	#else
705ae59f MT	24
	25	#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
	26
72b0cd35 PM	27	#endif
	28
	29	#define CP_REG_SIZE_SHIFT 52
	30	#define CP_REG_SIZE_MASK 0x00f0000000000000ULL
	31	#define CP_REG_SIZE_U32 0x0020000000000000ULL
	32	#define CP_REG_SIZE_U64 0x0030000000000000ULL
	33	#define CP_REG_ARM 0x4000000000000000ULL
f5a0a5a5	34	#define CP_REG_ARCH_MASK 0xff00000000000000ULL
72b0cd35	35
1b28762a MT	36	MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT);
	37	MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK);
	38	MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32);
	39	MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64);
	40	MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM);
	41	MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK);
72b0cd35	42
a65c9c17 CD	43	#define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
	44	#define QEMU_PSCI_0_1_FN(n) (QEMU_PSCI_0_1_FN_BASE + (n))
	45	#define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
	46	#define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1)
	47	#define QEMU_PSCI_0_1_FN_CPU_ON QEMU_PSCI_0_1_FN(2)
	48	#define QEMU_PSCI_0_1_FN_MIGRATE QEMU_PSCI_0_1_FN(3)
a22ec1e6	49
1b28762a MT	50	MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND);
	51	MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF);
	52	MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_ON, KVM_PSCI_FN_CPU_ON);
	53	MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);
a22ec1e6	54
863714ba CD	55	#define QEMU_PSCI_0_2_FN_BASE 0x84000000
	56	#define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n))
	57
	58	#define QEMU_PSCI_0_2_64BIT 0x40000000
	59	#define QEMU_PSCI_0_2_FN64_BASE \
	60	(QEMU_PSCI_0_2_FN_BASE + QEMU_PSCI_0_2_64BIT)
	61	#define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n))
	62
3df53cdf	63	#define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0)
863714ba CD	64	#define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1)
	65	#define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2)
	66	#define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3)
3df53cdf	67	#define QEMU_PSCI_0_2_FN_AFFINITY_INFO QEMU_PSCI_0_2_FN(4)
863714ba	68	#define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5)
3df53cdf AB	69	#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE QEMU_PSCI_0_2_FN(6)
	70	#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN(7)
	71	#define QEMU_PSCI_0_2_FN_SYSTEM_OFF QEMU_PSCI_0_2_FN(8)
	72	#define QEMU_PSCI_0_2_FN_SYSTEM_RESET QEMU_PSCI_0_2_FN(9)
863714ba CD	73
	74	#define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1)
	75	#define QEMU_PSCI_0_2_FN64_CPU_OFF QEMU_PSCI_0_2_FN64(2)
	76	#define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3)
3df53cdf	77	#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)
863714ba CD	78	#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)
863714ba CD	79
1b28762a MT	80	MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);
	81	MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);
	82	MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);
	83	MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);
	84	MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);
	85	MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);
	86	MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);
863714ba	87
3df53cdf AB	88	/* PSCI v0.2 return values used by TCG emulation of PSCI */
	89
	90	/* No Trusted OS migration to worry about when offlining CPUs */
	91	#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2
	92
	93	/* We implement version 0.2 only */
	94	#define QEMU_PSCI_0_2_RET_VERSION_0_2 2
	95
1b28762a	96	MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
3df53cdf	97	MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,
1b28762a	98	(PSCI_VERSION_MAJOR(0) \| PSCI_VERSION_MINOR(2)));
3df53cdf AB	99
	100	/* PSCI return values (inclusive of all PSCI versions) */
	101	#define QEMU_PSCI_RET_SUCCESS 0
	102	#define QEMU_PSCI_RET_NOT_SUPPORTED -1
	103	#define QEMU_PSCI_RET_INVALID_PARAMS -2
	104	#define QEMU_PSCI_RET_DENIED -3
	105	#define QEMU_PSCI_RET_ALREADY_ON -4
	106	#define QEMU_PSCI_RET_ON_PENDING -5
	107	#define QEMU_PSCI_RET_INTERNAL_FAILURE -6
	108	#define QEMU_PSCI_RET_NOT_PRESENT -7
	109	#define QEMU_PSCI_RET_DISABLED -8
	110
1b28762a MT	111	MISMATCH_CHECK(QEMU_PSCI_RET_SUCCESS, PSCI_RET_SUCCESS);
	112	MISMATCH_CHECK(QEMU_PSCI_RET_NOT_SUPPORTED, PSCI_RET_NOT_SUPPORTED);
	113	MISMATCH_CHECK(QEMU_PSCI_RET_INVALID_PARAMS, PSCI_RET_INVALID_PARAMS);
	114	MISMATCH_CHECK(QEMU_PSCI_RET_DENIED, PSCI_RET_DENIED);
	115	MISMATCH_CHECK(QEMU_PSCI_RET_ALREADY_ON, PSCI_RET_ALREADY_ON);
	116	MISMATCH_CHECK(QEMU_PSCI_RET_ON_PENDING, PSCI_RET_ON_PENDING);
	117	MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE);
	118	MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT);
	119	MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
3df53cdf	120
83e9a4ae PM	121	/* Note that KVM uses overlapping values for AArch32 and AArch64
	122	* target CPU numbers. AArch32 targets:
	123	*/
3541addc	124	#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0
83e9a4ae PM	125	#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1
	126
	127	/* AArch64 targets: */
	128	#define QEMU_KVM_ARM_TARGET_AEM_V8 0
	129	#define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
	130	#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
7525465e SZ	131	#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
7525465e SZ	132	#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
3541addc PM	133
	134	/* There's no kernel define for this: sentinel value which
	135	* matches no KVM target value for either 64 or 32 bit
	136	*/
	137	#define QEMU_KVM_ARM_TARGET_NONE UINT_MAX
	138
83e9a4ae	139	#ifdef TARGET_AARCH64
1b28762a MT	140	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8);
	141	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8);
	142	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57);
	143	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA);
	144	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
83e9a4ae	145	#else
1b28762a MT	146	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15);
1b28762a MT	147	MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7);
3541addc PM	148	#endif
3541addc PM	149
f5a0a5a5 PM	150	#define CP_REG_ARM64 0x6000000000000000ULL
	151	#define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000
	152	#define CP_REG_ARM_COPROC_SHIFT 16
	153	#define CP_REG_ARM64_SYSREG (0x0013 << CP_REG_ARM_COPROC_SHIFT)
	154	#define CP_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
	155	#define CP_REG_ARM64_SYSREG_OP0_SHIFT 14
	156	#define CP_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
	157	#define CP_REG_ARM64_SYSREG_OP1_SHIFT 11
	158	#define CP_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
	159	#define CP_REG_ARM64_SYSREG_CRN_SHIFT 7
	160	#define CP_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
	161	#define CP_REG_ARM64_SYSREG_CRM_SHIFT 3
	162	#define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
	163	#define CP_REG_ARM64_SYSREG_OP2_SHIFT 0
	164
	165	/* No kernel define but it's useful to QEMU */
	166	#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)
	167
	168	#ifdef TARGET_AARCH64
1b28762a MT	169	MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
	170	MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
	171	MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
	172	MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG);
	173	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK);
	174	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT);
	175	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK);
	176	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT);
	177	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK);
	178	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT);
	179	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK);
	180	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT);
	181	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK);
	182	MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT);
f5a0a5a5 PM	183	#endif
f5a0a5a5 PM	184
72b0cd35 PM	185	#undef MISMATCH_CHECK
	186
	187	#endif