[qemu.git] / target-alpha / helper.c

/*
 *  Alpha emulation cpu helpers for qemu.
 *
 *  Copyright (c) 2007 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>

#include "cpu.h"
#include "exec-all.h"
#include "softfloat.h"

uint64_t cpu_alpha_load_fpcr (CPUState *env)
{
    uint64_t r = 0;
    uint8_t t;

    t = env->fpcr_exc_status;
    if (t) {
        r = FPCR_SUM;
        if (t & float_flag_invalid) {
            r |= FPCR_INV;
        }
        if (t & float_flag_divbyzero) {
            r |= FPCR_DZE;
        }
        if (t & float_flag_overflow) {
            r |= FPCR_OVF;
        }
        if (t & float_flag_underflow) {
            r |= FPCR_UNF;
        }
        if (t & float_flag_inexact) {
            r |= FPCR_INE;
        }
    }

    t = env->fpcr_exc_mask;
    if (t & float_flag_invalid) {
        r |= FPCR_INVD;
    }
    if (t & float_flag_divbyzero) {
        r |= FPCR_DZED;
    }
    if (t & float_flag_overflow) {
        r |= FPCR_OVFD;
    }
    if (t & float_flag_underflow) {
        r |= FPCR_UNFD;
    }
    if (t & float_flag_inexact) {
        r |= FPCR_INED;
    }

    switch (env->fpcr_dyn_round) {
    case float_round_nearest_even:
        r |= FPCR_DYN_NORMAL;
        break;
    case float_round_down:
        r |= FPCR_DYN_MINUS;
        break;
    case float_round_up:
        r |= FPCR_DYN_PLUS;
        break;
    case float_round_to_zero:
        r |= FPCR_DYN_CHOPPED;
        break;
    }

    if (env->fpcr_dnz) {
        r |= FPCR_DNZ;
    }
    if (env->fpcr_dnod) {
        r |= FPCR_DNOD;
    }
    if (env->fpcr_undz) {
        r |= FPCR_UNDZ;
    }

    return r;
}

void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
{
    uint8_t t;

    t = 0;
    if (val & FPCR_INV) {
        t |= float_flag_invalid;
    }
    if (val & FPCR_DZE) {
        t |= float_flag_divbyzero;
    }
    if (val & FPCR_OVF) {
        t |= float_flag_overflow;
    }
    if (val & FPCR_UNF) {
        t |= float_flag_underflow;
    }
    if (val & FPCR_INE) {
        t |= float_flag_inexact;
    }
    env->fpcr_exc_status = t;

    t = 0;
    if (val & FPCR_INVD) {
        t |= float_flag_invalid;
    }
    if (val & FPCR_DZED) {
        t |= float_flag_divbyzero;
    }
    if (val & FPCR_OVFD) {
        t |= float_flag_overflow;
    }
    if (val & FPCR_UNFD) {
        t |= float_flag_underflow;
    }
    if (val & FPCR_INED) {
        t |= float_flag_inexact;
    }
    env->fpcr_exc_mask = t;

    switch (val & FPCR_DYN_MASK) {
    case FPCR_DYN_CHOPPED:
        t = float_round_to_zero;
        break;
    case FPCR_DYN_MINUS:
        t = float_round_down;
        break;
    case FPCR_DYN_NORMAL:
        t = float_round_nearest_even;
        break;
    case FPCR_DYN_PLUS:
        t = float_round_up;
        break;
    }
    env->fpcr_dyn_round = t;

    env->fpcr_flush_to_zero
      = (val & (FPCR_UNDZ|FPCR_UNFD)) == (FPCR_UNDZ|FPCR_UNFD);

    env->fpcr_dnz = (val & FPCR_DNZ) != 0;
    env->fpcr_dnod = (val & FPCR_DNOD) != 0;
    env->fpcr_undz = (val & FPCR_UNDZ) != 0;
}

#if defined(CONFIG_USER_ONLY)

int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                                int mmu_idx, int is_softmmu)
{
    if (rw == 2)
        env->exception_index = EXCP_ITB_MISS;
    else
        env->exception_index = EXCP_DFAULT;
    env->ipr[IPR_EXC_ADDR] = address;

    return 1;
}

void do_interrupt (CPUState *env)
{
    env->exception_index = -1;
}

#else

target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
{
    return -1;
}

int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                                int mmu_idx, int is_softmmu)
{
    uint32_t opc;

    if (rw == 2) {
        /* Instruction translation buffer miss */
        env->exception_index = EXCP_ITB_MISS;
    } else {
        if (env->ipr[IPR_EXC_ADDR] & 1)
            env->exception_index = EXCP_DTB_MISS_PAL;
        else
            env->exception_index = EXCP_DTB_MISS_NATIVE;
        opc = (ldl_code(env->pc) >> 21) << 4;
        if (rw) {
            opc |= 0x9;
        } else {
            opc |= 0x4;
        }
        env->ipr[IPR_MM_STAT] = opc;
    }

    return 1;
}

int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp)
{
    uint64_t hwpcb;
    int ret = 0;

    hwpcb = env->ipr[IPR_PCBB];
    switch (iprn) {
    case IPR_ASN:
        if (env->features & FEATURE_ASN)
            *valp = env->ipr[IPR_ASN];
        else
            *valp = 0;
        break;
    case IPR_ASTEN:
        *valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60;
        break;
    case IPR_ASTSR:
        *valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60;
        break;
    case IPR_DATFX:
        /* Write only */
        ret = -1;
        break;
    case IPR_ESP:
        if (env->features & FEATURE_SPS)
            *valp = env->ipr[IPR_ESP];
        else
            *valp = ldq_raw(hwpcb + 8);
        break;
    case IPR_FEN:
        *valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63;
        break;
    case IPR_IPIR:
        /* Write-only */
        ret = -1;
        break;
    case IPR_IPL:
        *valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
        break;
    case IPR_KSP:
        if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
            ret = -1;
        } else {
            if (env->features & FEATURE_SPS)
                *valp = env->ipr[IPR_KSP];
            else
                *valp = ldq_raw(hwpcb + 0);
        }
        break;
    case IPR_MCES:
        *valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59;
        break;
    case IPR_PERFMON:
        /* Implementation specific */
        *valp = 0;
        break;
    case IPR_PCBB:
        *valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16;
        break;
    case IPR_PRBR:
        *valp = env->ipr[IPR_PRBR];
        break;
    case IPR_PTBR:
        *valp = env->ipr[IPR_PTBR];
        break;
    case IPR_SCBB:
        *valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]);
        break;
    case IPR_SIRR:
        /* Write-only */
        ret = -1;
        break;
    case IPR_SISR:
        *valp = (int64_t)((int16_t)env->ipr[IPR_SISR]);
    case IPR_SSP:
        if (env->features & FEATURE_SPS)
            *valp = env->ipr[IPR_SSP];
        else
            *valp = ldq_raw(hwpcb + 16);
        break;
    case IPR_SYSPTBR:
        if (env->features & FEATURE_VIRBND)
            *valp = env->ipr[IPR_SYSPTBR];
        else
            ret = -1;
        break;
    case IPR_TBCHK:
        if ((env->features & FEATURE_TBCHK)) {
            /* XXX: TODO */
            *valp = 0;
            ret = -1;
        } else {
            ret = -1;
        }
        break;
    case IPR_TBIA:
        /* Write-only */
        ret = -1;
        break;
    case IPR_TBIAP:
        /* Write-only */
        ret = -1;
        break;
    case IPR_TBIS:
        /* Write-only */
        ret = -1;
        break;
    case IPR_TBISD:
        /* Write-only */
        ret = -1;
        break;
    case IPR_TBISI:
        /* Write-only */
        ret = -1;
        break;
    case IPR_USP:
        if (env->features & FEATURE_SPS)
            *valp = env->ipr[IPR_USP];
        else
            *valp = ldq_raw(hwpcb + 24);
        break;
    case IPR_VIRBND:
        if (env->features & FEATURE_VIRBND)
            *valp = env->ipr[IPR_VIRBND];
        else
            ret = -1;
        break;
    case IPR_VPTB:
        *valp = env->ipr[IPR_VPTB];
        break;
    case IPR_WHAMI:
        *valp = env->ipr[IPR_WHAMI];
        break;
    default:
        /* Invalid */
        ret = -1;
        break;
    }

    return ret;
}

int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp)
{
    uint64_t hwpcb, tmp64;
    uint8_t tmp8;
    int ret = 0;

    hwpcb = env->ipr[IPR_PCBB];
    switch (iprn) {
    case IPR_ASN:
        /* Read-only */
        ret = -1;
        break;
    case IPR_ASTEN:
        tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4;
        *oldvalp = tmp8;
        tmp8 &= val & 0xF;
        tmp8 |= (val >> 4) & 0xF;
        env->ipr[IPR_ASTEN] &= ~0xF;
        env->ipr[IPR_ASTEN] |= tmp8;
        ret = 1;
        break;
    case IPR_ASTSR:
        tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4;
        *oldvalp = tmp8;
        tmp8 &= val & 0xF;
        tmp8 |= (val >> 4) & 0xF;
        env->ipr[IPR_ASTSR] &= ~0xF;
        env->ipr[IPR_ASTSR] |= tmp8;
        ret = 1;
    case IPR_DATFX:
        env->ipr[IPR_DATFX] &= ~0x1;
        env->ipr[IPR_DATFX] |= val & 1;
        tmp64 = ldq_raw(hwpcb + 56);
        tmp64 &= ~0x8000000000000000ULL;
        tmp64 |= (val & 1) << 63;
        stq_raw(hwpcb + 56, tmp64);
        break;
    case IPR_ESP:
        if (env->features & FEATURE_SPS)
            env->ipr[IPR_ESP] = val;
        else
            stq_raw(hwpcb + 8, val);
        break;
    case IPR_FEN:
        env->ipr[IPR_FEN] = val & 1;
        tmp64 = ldq_raw(hwpcb + 56);
        tmp64 &= ~1;
        tmp64 |= val & 1;
        stq_raw(hwpcb + 56, tmp64);
        break;
    case IPR_IPIR:
        /* XXX: TODO: Send IRQ to CPU #ir[16] */
        break;
    case IPR_IPL:
        *oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
        env->ipr[IPR_IPL] &= ~0x1F;
        env->ipr[IPR_IPL] |= val & 0x1F;
        /* XXX: may issue an interrupt or ASR _now_ */
        ret = 1;
        break;
    case IPR_KSP:
        if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
            ret = -1;
        } else {
            if (env->features & FEATURE_SPS)
                env->ipr[IPR_KSP] = val;
            else
                stq_raw(hwpcb + 0, val);
        }
        break;
    case IPR_MCES:
        env->ipr[IPR_MCES] &= ~((val & 0x7) | 0x18);
        env->ipr[IPR_MCES] |= val & 0x18;
        break;
    case IPR_PERFMON:
        /* Implementation specific */
        *oldvalp = 0;
        ret = 1;
        break;
    case IPR_PCBB:
        /* Read-only */
        ret = -1;
        break;
    case IPR_PRBR:
        env->ipr[IPR_PRBR] = val;
        break;
    case IPR_PTBR:
        /* Read-only */
        ret = -1;
        break;
    case IPR_SCBB:
        env->ipr[IPR_SCBB] = (uint32_t)val;
        break;
    case IPR_SIRR:
        if (val & 0xF) {
            env->ipr[IPR_SISR] |= 1 << (val & 0xF);
            /* XXX: request a software interrupt _now_ */
        }
        break;
    case IPR_SISR:
        /* Read-only */
        ret = -1;
        break;
    case IPR_SSP:
        if (env->features & FEATURE_SPS)
            env->ipr[IPR_SSP] = val;
        else
            stq_raw(hwpcb + 16, val);
        break;
    case IPR_SYSPTBR:
        if (env->features & FEATURE_VIRBND)
            env->ipr[IPR_SYSPTBR] = val;
        else
            ret = -1;
        break;
    case IPR_TBCHK:
        /* Read-only */
        ret = -1;
        break;
    case IPR_TBIA:
        tlb_flush(env, 1);
        break;
    case IPR_TBIAP:
        tlb_flush(env, 1);
        break;
    case IPR_TBIS:
        tlb_flush_page(env, val);
        break;
    case IPR_TBISD:
        tlb_flush_page(env, val);
        break;
    case IPR_TBISI:
        tlb_flush_page(env, val);
        break;
    case IPR_USP:
        if (env->features & FEATURE_SPS)
            env->ipr[IPR_USP] = val;
        else
            stq_raw(hwpcb + 24, val);
        break;
    case IPR_VIRBND:
        if (env->features & FEATURE_VIRBND)
            env->ipr[IPR_VIRBND] = val;
        else
            ret = -1;
        break;
    case IPR_VPTB:
        env->ipr[IPR_VPTB] = val;
        break;
    case IPR_WHAMI:
        /* Read-only */
        ret = -1;
        break;
    default:
        /* Invalid */
        ret = -1;
        break;
    }

    return ret;
}

void do_interrupt (CPUState *env)
{
    int excp;

    env->ipr[IPR_EXC_ADDR] = env->pc | 1;
    excp = env->exception_index;
    env->exception_index = -1;
    env->error_code = 0;
    /* XXX: disable interrupts and memory mapping */
    if (env->ipr[IPR_PAL_BASE] != -1ULL) {
        /* We use native PALcode */
        env->pc = env->ipr[IPR_PAL_BASE] + excp;
    } else {
        /* We use emulated PALcode */
        abort();
        /* Emulate REI */
        env->pc = env->ipr[IPR_EXC_ADDR] & ~7;
        env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
        /* XXX: re-enable interrupts and memory mapping */
    }
}
#endif

void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
                     int flags)
{
    static const char *linux_reg_names[] = {
        "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
        "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
        "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
        "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
    };
    int i;

    cpu_fprintf(f, "     PC  " TARGET_FMT_lx "      PS  " TARGET_FMT_lx "\n",
                env->pc, env->ps);
    for (i = 0; i < 31; i++) {
        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
                    linux_reg_names[i], env->ir[i]);
        if ((i % 3) == 2)
            cpu_fprintf(f, "\n");
    }

    cpu_fprintf(f, "lock_a   " TARGET_FMT_lx " lock_v   " TARGET_FMT_lx "\n",
                env->lock_addr, env->lock_value);

    for (i = 0; i < 31; i++) {
        cpu_fprintf(f, "FIR%02d    " TARGET_FMT_lx " ", i,
                    *((uint64_t *)(&env->fir[i])));
        if ((i % 3) == 2)
            cpu_fprintf(f, "\n");
    }
    cpu_fprintf(f, "\n");
}
Commit	Line	Data
4c9649a9 JM	1	/*
4c9649a9 JM	2	* Alpha emulation cpu helpers for qemu.
5fafdf24	3	*
4c9649a9 JM	4	* Copyright (c) 2007 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4c9649a9 JM	18	*/
	19
	20	#include <stdint.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23
	24	#include "cpu.h"
	25	#include "exec-all.h"
ba0e276d RH	26	#include "softfloat.h"
	27
	28	uint64_t cpu_alpha_load_fpcr (CPUState *env)
	29	{
8443effb RH	30	uint64_t r = 0;
	31	uint8_t t;
	32
	33	t = env->fpcr_exc_status;
	34	if (t) {
	35	r = FPCR_SUM;
	36	if (t & float_flag_invalid) {
	37	r \|= FPCR_INV;
	38	}
	39	if (t & float_flag_divbyzero) {
	40	r \|= FPCR_DZE;
	41	}
	42	if (t & float_flag_overflow) {
	43	r \|= FPCR_OVF;
	44	}
	45	if (t & float_flag_underflow) {
	46	r \|= FPCR_UNF;
	47	}
	48	if (t & float_flag_inexact) {
	49	r \|= FPCR_INE;
	50	}
	51	}
	52
	53	t = env->fpcr_exc_mask;
	54	if (t & float_flag_invalid) {
	55	r \|= FPCR_INVD;
	56	}
	57	if (t & float_flag_divbyzero) {
	58	r \|= FPCR_DZED;
	59	}
	60	if (t & float_flag_overflow) {
	61	r \|= FPCR_OVFD;
	62	}
	63	if (t & float_flag_underflow) {
	64	r \|= FPCR_UNFD;
	65	}
	66	if (t & float_flag_inexact) {
	67	r \|= FPCR_INED;
	68	}
	69
	70	switch (env->fpcr_dyn_round) {
ba0e276d	71	case float_round_nearest_even:
8443effb	72	r \|= FPCR_DYN_NORMAL;
ba0e276d RH	73	break;
ba0e276d RH	74	case float_round_down:
8443effb	75	r \|= FPCR_DYN_MINUS;
ba0e276d RH	76	break;
ba0e276d RH	77	case float_round_up:
8443effb	78	r \|= FPCR_DYN_PLUS;
ba0e276d RH	79	break;
ba0e276d RH	80	case float_round_to_zero:
8443effb	81	r \|= FPCR_DYN_CHOPPED;
ba0e276d RH	82	break;
ba0e276d RH	83	}
8443effb RH	84
	85	if (env->fpcr_dnz) {
	86	r \|= FPCR_DNZ;
	87	}
	88	if (env->fpcr_dnod) {
	89	r \|= FPCR_DNOD;
	90	}
	91	if (env->fpcr_undz) {
	92	r \|= FPCR_UNDZ;
	93	}
	94
	95	return r;
ba0e276d RH	96	}
	97
	98	void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
	99	{
8443effb RH	100	uint8_t t;
	101
	102	t = 0;
	103	if (val & FPCR_INV) {
	104	t \|= float_flag_invalid;
	105	}
	106	if (val & FPCR_DZE) {
	107	t \|= float_flag_divbyzero;
	108	}
	109	if (val & FPCR_OVF) {
	110	t \|= float_flag_overflow;
	111	}
	112	if (val & FPCR_UNF) {
	113	t \|= float_flag_underflow;
	114	}
	115	if (val & FPCR_INE) {
	116	t \|= float_flag_inexact;
	117	}
	118	env->fpcr_exc_status = t;
	119
	120	t = 0;
	121	if (val & FPCR_INVD) {
	122	t \|= float_flag_invalid;
	123	}
	124	if (val & FPCR_DZED) {
	125	t \|= float_flag_divbyzero;
	126	}
	127	if (val & FPCR_OVFD) {
	128	t \|= float_flag_overflow;
	129	}
	130	if (val & FPCR_UNFD) {
	131	t \|= float_flag_underflow;
	132	}
	133	if (val & FPCR_INED) {
	134	t \|= float_flag_inexact;
	135	}
	136	env->fpcr_exc_mask = t;
	137
	138	switch (val & FPCR_DYN_MASK) {
	139	case FPCR_DYN_CHOPPED:
	140	t = float_round_to_zero;
ba0e276d	141	break;
8443effb RH	142	case FPCR_DYN_MINUS:
8443effb RH	143	t = float_round_down;
ba0e276d	144	break;
8443effb RH	145	case FPCR_DYN_NORMAL:
8443effb RH	146	t = float_round_nearest_even;
ba0e276d	147	break;
8443effb RH	148	case FPCR_DYN_PLUS:
8443effb RH	149	t = float_round_up;
ba0e276d RH	150	break;
ba0e276d RH	151	}
8443effb RH	152	env->fpcr_dyn_round = t;
	153
	154	env->fpcr_flush_to_zero
	155	= (val & (FPCR_UNDZ\|FPCR_UNFD)) == (FPCR_UNDZ\|FPCR_UNFD);
	156
	157	env->fpcr_dnz = (val & FPCR_DNZ) != 0;
	158	env->fpcr_dnod = (val & FPCR_DNOD) != 0;
	159	env->fpcr_undz = (val & FPCR_UNDZ) != 0;
ba0e276d	160	}
4c9649a9	161
5fafdf24	162	#if defined(CONFIG_USER_ONLY)
4c9649a9 JM	163
4c9649a9 JM	164	int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	165	int mmu_idx, int is_softmmu)
4c9649a9 JM	166	{
	167	if (rw == 2)
	168	env->exception_index = EXCP_ITB_MISS;
	169	else
	170	env->exception_index = EXCP_DFAULT;
	171	env->ipr[IPR_EXC_ADDR] = address;
3b46e624	172
4c9649a9 JM	173	return 1;
	174	}
	175
4c9649a9 JM	176	void do_interrupt (CPUState *env)
	177	{
	178	env->exception_index = -1;
	179	}
	180
	181	#else
	182
c227f099	183	target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
4c9649a9 JM	184	{
	185	return -1;
	186	}
	187
	188	int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	189	int mmu_idx, int is_softmmu)
4c9649a9 JM	190	{
	191	uint32_t opc;
	192
	193	if (rw == 2) {
	194	/* Instruction translation buffer miss */
	195	env->exception_index = EXCP_ITB_MISS;
	196	} else {
	197	if (env->ipr[IPR_EXC_ADDR] & 1)
	198	env->exception_index = EXCP_DTB_MISS_PAL;
	199	else
	200	env->exception_index = EXCP_DTB_MISS_NATIVE;
	201	opc = (ldl_code(env->pc) >> 21) << 4;
	202	if (rw) {
	203	opc \|= 0x9;
	204	} else {
	205	opc \|= 0x4;
	206	}
	207	env->ipr[IPR_MM_STAT] = opc;
	208	}
	209
	210	return 1;
	211	}
	212
	213	int cpu_alpha_mfpr (CPUState env, int iprn, uint64_t valp)
	214	{
	215	uint64_t hwpcb;
	216	int ret = 0;
	217
	218	hwpcb = env->ipr[IPR_PCBB];
	219	switch (iprn) {
	220	case IPR_ASN:
	221	if (env->features & FEATURE_ASN)
	222	*valp = env->ipr[IPR_ASN];
	223	else
	224	*valp = 0;
	225	break;
	226	case IPR_ASTEN:
	227	*valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60;
	228	break;
	229	case IPR_ASTSR:
	230	*valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60;
	231	break;
	232	case IPR_DATFX:
	233	/* Write only */
	234	ret = -1;
	235	break;
	236	case IPR_ESP:
	237	if (env->features & FEATURE_SPS)
	238	*valp = env->ipr[IPR_ESP];
	239	else
	240	*valp = ldq_raw(hwpcb + 8);
	241	break;
	242	case IPR_FEN:
	243	*valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63;
	244	break;
	245	case IPR_IPIR:
	246	/* Write-only */
	247	ret = -1;
	248	break;
	249	case IPR_IPL:
	250	*valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
	251	break;
	252	case IPR_KSP:
	253	if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
254	ret = -1;
255	} else {
256	if (env->features & FEATURE_SPS)
257	*valp = env->ipr[IPR_KSP];
258	else
259	*valp = ldq_raw(hwpcb + 0);
260	}
261	break;
262	case IPR_MCES:
263	*valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59;
264	break;
265	case IPR_PERFMON:
266	/* Implementation specific */
267	*valp = 0;
268	break;
269	case IPR_PCBB:
270	*valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16;
271	break;
272	case IPR_PRBR:
273	*valp = env->ipr[IPR_PRBR];
274	break;
275	case IPR_PTBR:
276	*valp = env->ipr[IPR_PTBR];
277	break;
278	case IPR_SCBB:
279	*valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]);
280	break;
281	case IPR_SIRR:
282	/* Write-only */
283	ret = -1;
284	break;
285	case IPR_SISR:
286	*valp = (int64_t)((int16_t)env->ipr[IPR_SISR]);
287	case IPR_SSP:
288	if (env->features & FEATURE_SPS)
289	*valp = env->ipr[IPR_SSP];
290	else
291	*valp = ldq_raw(hwpcb + 16);
292	break;
293	case IPR_SYSPTBR:
294	if (env->features & FEATURE_VIRBND)
295	*valp = env->ipr[IPR_SYSPTBR];
296	else
297	ret = -1;
298	break;
299	case IPR_TBCHK:
300	if ((env->features & FEATURE_TBCHK)) {
301	/* XXX: TODO */
302	*valp = 0;
303	ret = -1;
304	} else {
305	ret = -1;
306	}
307	break;
308	case IPR_TBIA:
309	/* Write-only */
310	ret = -1;
311	break;
312	case IPR_TBIAP:
313	/* Write-only */
314	ret = -1;
315	break;
316	case IPR_TBIS:
317	/* Write-only */
318	ret = -1;
319	break;
320	case IPR_TBISD:
321	/* Write-only */
322	ret = -1;
323	break;
324	case IPR_TBISI:
325	/* Write-only */
326	ret = -1;
327	break;
328	case IPR_USP:
329	if (env->features & FEATURE_SPS)
330	*valp = env->ipr[IPR_USP];
331	else
332	*valp = ldq_raw(hwpcb + 24);
333	break;
334	case IPR_VIRBND:
335	if (env->features & FEATURE_VIRBND)
336	*valp = env->ipr[IPR_VIRBND];
337	else
338	ret = -1;
339	break;
340	case IPR_VPTB:
341	*valp = env->ipr[IPR_VPTB];
342	break;
343	case IPR_WHAMI:
344	*valp = env->ipr[IPR_WHAMI];
345	break;
346	default:
347	/* Invalid */
348	ret = -1;
349	break;
350	}
351
352	return ret;
353	}
354
355	int cpu_alpha_mtpr (CPUState env, int iprn, uint64_t val, uint64_t oldvalp)
356	{
357	uint64_t hwpcb, tmp64;
358	uint8_t tmp8;
359	int ret = 0;
360
361	hwpcb = env->ipr[IPR_PCBB];
362	switch (iprn) {
363	case IPR_ASN:
364	/* Read-only */
365	ret = -1;
366	break;
367	case IPR_ASTEN:
368	tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4;
369	*oldvalp = tmp8;
370	tmp8 &= val & 0xF;
371	tmp8 \|= (val >> 4) & 0xF;
372	env->ipr[IPR_ASTEN] &= ~0xF;
373	env->ipr[IPR_ASTEN] \|= tmp8;
374	ret = 1;
375	break;
376	case IPR_ASTSR:
377	tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4;
378	*oldvalp = tmp8;
379	tmp8 &= val & 0xF;
380	tmp8 \|= (val >> 4) & 0xF;
381	env->ipr[IPR_ASTSR] &= ~0xF;
382	env->ipr[IPR_ASTSR] \|= tmp8;
383	ret = 1;
384	case IPR_DATFX:
385	env->ipr[IPR_DATFX] &= ~0x1;
386	env->ipr[IPR_DATFX] \|= val & 1;
387	tmp64 = ldq_raw(hwpcb + 56);
388	tmp64 &= ~0x8000000000000000ULL;
389	tmp64 \|= (val & 1) << 63;
390	stq_raw(hwpcb + 56, tmp64);
391	break;
392	case IPR_ESP:
393	if (env->features & FEATURE_SPS)
394	env->ipr[IPR_ESP] = val;
395	else
396	stq_raw(hwpcb + 8, val);
397	break;
398	case IPR_FEN:
399	env->ipr[IPR_FEN] = val & 1;
400	tmp64 = ldq_raw(hwpcb + 56);
401	tmp64 &= ~1;
402	tmp64 \|= val & 1;
403	stq_raw(hwpcb + 56, tmp64);
404	break;
405	case IPR_IPIR:
406	/* XXX: TODO: Send IRQ to CPU #ir[16] */
407	break;
408	case IPR_IPL:
409	*oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
410	env->ipr[IPR_IPL] &= ~0x1F;
411	env->ipr[IPR_IPL] \|= val & 0x1F;
412	/* XXX: may issue an interrupt or ASR _now_ */
413	ret = 1;
414	break;
415	case IPR_KSP:
416	if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
417	ret = -1;
418	} else {
419	if (env->features & FEATURE_SPS)
420	env->ipr[IPR_KSP] = val;
421	else
422	stq_raw(hwpcb + 0, val);
423	}
424	break;
425	case IPR_MCES:
426	env->ipr[IPR_MCES] &= ~((val & 0x7) \| 0x18);
427	env->ipr[IPR_MCES] \|= val & 0x18;
428	break;
429	case IPR_PERFMON:
430	/* Implementation specific */
431	*oldvalp = 0;
432	ret = 1;
433	break;
434	case IPR_PCBB:
435	/* Read-only */
436	ret = -1;
437	break;
438	case IPR_PRBR:
439	env->ipr[IPR_PRBR] = val;
440	break;
441	case IPR_PTBR:
442	/* Read-only */
443	ret = -1;
444	break;
445	case IPR_SCBB:
446	env->ipr[IPR_SCBB] = (uint32_t)val;
447	break;
448	case IPR_SIRR:
449	if (val & 0xF) {
450	env->ipr[IPR_SISR] \|= 1 << (val & 0xF);
451	/* XXX: request a software interrupt _now_ */
452	}
453	break;
454	case IPR_SISR:
455	/* Read-only */
456	ret = -1;
457	break;
458	case IPR_SSP:
459	if (env->features & FEATURE_SPS)
460	env->ipr[IPR_SSP] = val;
461	else
462	stq_raw(hwpcb + 16, val);
463	break;
464	case IPR_SYSPTBR:
465	if (env->features & FEATURE_VIRBND)
466	env->ipr[IPR_SYSPTBR] = val;
467	else
468	ret = -1;
b2c58871	469	break;
4c9649a9 JM	470	case IPR_TBCHK:
	471	/* Read-only */
	472	ret = -1;
	473	break;
	474	case IPR_TBIA:
	475	tlb_flush(env, 1);
	476	break;
	477	case IPR_TBIAP:
	478	tlb_flush(env, 1);
	479	break;
	480	case IPR_TBIS:
	481	tlb_flush_page(env, val);
	482	break;
	483	case IPR_TBISD:
	484	tlb_flush_page(env, val);
	485	break;
	486	case IPR_TBISI:
	487	tlb_flush_page(env, val);
	488	break;
	489	case IPR_USP:
	490	if (env->features & FEATURE_SPS)
	491	env->ipr[IPR_USP] = val;
	492	else
	493	stq_raw(hwpcb + 24, val);
	494	break;
	495	case IPR_VIRBND:
	496	if (env->features & FEATURE_VIRBND)
	497	env->ipr[IPR_VIRBND] = val;
	498	else
	499	ret = -1;
	500	break;
	501	case IPR_VPTB:
	502	env->ipr[IPR_VPTB] = val;
	503	break;
	504	case IPR_WHAMI:
	505	/* Read-only */
	506	ret = -1;
	507	break;
	508	default:
	509	/* Invalid */
	510	ret = -1;
	511	break;
	512	}
	513
	514	return ret;
	515	}
	516
	517	void do_interrupt (CPUState *env)
	518	{
	519	int excp;
	520
	521	env->ipr[IPR_EXC_ADDR] = env->pc \| 1;
	522	excp = env->exception_index;
ee0dc6d3	523	env->exception_index = -1;
4c9649a9 JM	524	env->error_code = 0;
	525	/* XXX: disable interrupts and memory mapping */
	526	if (env->ipr[IPR_PAL_BASE] != -1ULL) {
	527	/* We use native PALcode */
	528	env->pc = env->ipr[IPR_PAL_BASE] + excp;
	529	} else {
	530	/* We use emulated PALcode */
352e48b0	531	abort();
4c9649a9 JM	532	/* Emulate REI */
	533	env->pc = env->ipr[IPR_EXC_ADDR] & ~7;
	534	env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
	535	/* XXX: re-enable interrupts and memory mapping */
	536	}
	537	}
	538	#endif
	539
9a78eead	540	void cpu_dump_state (CPUState env, FILE f, fprintf_function cpu_fprintf,
4c9649a9 JM	541	int flags)
4c9649a9 JM	542	{
b55266b5	543	static const char *linux_reg_names[] = {
4c9649a9 JM	544	"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
	545	"t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
	546	"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
	547	"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
	548	};
	549	int i;
	550
	551	cpu_fprintf(f, " PC " TARGET_FMT_lx " PS " TARGET_FMT_lx "\n",
	552	env->pc, env->ps);
	553	for (i = 0; i < 31; i++) {
	554	cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
	555	linux_reg_names[i], env->ir[i]);
	556	if ((i % 3) == 2)
	557	cpu_fprintf(f, "\n");
	558	}
6910b8f6 RH	559
	560	cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
	561	env->lock_addr, env->lock_value);
	562
4c9649a9 JM	563	for (i = 0; i < 31; i++) {
	564	cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i,
	565	((uint64_t )(&env->fir[i])));
	566	if ((i % 3) == 2)
	567	cpu_fprintf(f, "\n");
	568	}
6910b8f6	569	cpu_fprintf(f, "\n");
4c9649a9	570	}