[qemu.git] / hw / input / pckbd.c

/*
 * QEMU PC keyboard emulation
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "hw/i386/pc.h"
#include "hw/input/ps2.h"
#include "hw/input/i8042.h"
#include "sysemu/sysemu.h"

#include "trace.h"

/*	Keyboard Controller Commands */
#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
#define KBD_CCMD_READ_INPORT    0xC0    /* read input port */
#define KBD_CCMD_READ_OUTPORT	0xD0    /* read output port */
#define KBD_CCMD_WRITE_OUTPORT	0xD1    /* write output port */
#define KBD_CCMD_WRITE_OBUF	0xD2
#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
                                           initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
#define KBD_CCMD_DISABLE_A20    0xDD    /* HP vectra only ? */
#define KBD_CCMD_ENABLE_A20     0xDF    /* HP vectra only ? */
#define KBD_CCMD_PULSE_BITS_3_0 0xF0    /* Pulse bits 3-0 of the output port P2. */
#define KBD_CCMD_RESET          0xFE    /* Pulse bit 0 of the output port P2 = CPU reset. */
#define KBD_CCMD_NO_OP          0xFF    /* Pulse no bits of the output port P2. */

/* Keyboard Commands */
#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
#define KBD_CMD_ECHO     	0xEE
#define KBD_CMD_GET_ID 	        0xF2	/* get keyboard ID */
#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
#define KBD_CMD_RESET_DISABLE	0xF5	/* reset and disable scanning */
#define KBD_CMD_RESET_ENABLE   	0xF6    /* reset and enable scanning */
#define KBD_CMD_RESET		0xFF	/* Reset */

/* Keyboard Replies */
#define KBD_REPLY_POR		0xAA	/* Power on reset */
#define KBD_REPLY_ACK		0xFA	/* Command ACK */
#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */

/* Status Register Bits */
#define KBD_STAT_OBF 		0x01	/* Keyboard output buffer full */
#define KBD_STAT_IBF 		0x02	/* Keyboard input buffer full */
#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
#define KBD_STAT_GTO 		0x40	/* General receive/xmit timeout */
#define KBD_STAT_PERR 		0x80	/* Parity error */

/* Controller Mode Register Bits */
#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 		0x04	/* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
#define KBD_MODE_KCC 		0x40	/* Scan code conversion to PC format */
#define KBD_MODE_RFU		0x80

/* Output Port Bits */
#define KBD_OUT_RESET           0x01    /* 1=normal mode, 0=reset */
#define KBD_OUT_A20             0x02    /* x86 only */
#define KBD_OUT_OBF             0x10    /* Keyboard output buffer full */
#define KBD_OUT_MOUSE_OBF       0x20    /* Mouse output buffer full */

/* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
 * We make the default value of the outport include these four bits,
 * so that the subsection is rarely necessary.
 */
#define KBD_OUT_ONES            0xcc

/* Mouse Commands */
#define AUX_SET_SCALE11		0xE6	/* Set 1:1 scaling */
#define AUX_SET_SCALE21		0xE7	/* Set 2:1 scaling */
#define AUX_SET_RES		0xE8	/* Set resolution */
#define AUX_GET_SCALE		0xE9	/* Get scaling factor */
#define AUX_SET_STREAM		0xEA	/* Set stream mode */
#define AUX_POLL		0xEB	/* Poll */
#define AUX_RESET_WRAP		0xEC	/* Reset wrap mode */
#define AUX_SET_WRAP		0xEE	/* Set wrap mode */
#define AUX_SET_REMOTE		0xF0	/* Set remote mode */
#define AUX_GET_TYPE		0xF2	/* Get type */
#define AUX_SET_SAMPLE		0xF3	/* Set sample rate */
#define AUX_ENABLE_DEV		0xF4	/* Enable aux device */
#define AUX_DISABLE_DEV		0xF5	/* Disable aux device */
#define AUX_SET_DEFAULT		0xF6
#define AUX_RESET		0xFF	/* Reset aux device */
#define AUX_ACK			0xFA	/* Command byte ACK. */

#define MOUSE_STATUS_REMOTE     0x40
#define MOUSE_STATUS_ENABLED    0x20
#define MOUSE_STATUS_SCALE21    0x10

#define KBD_PENDING_KBD         1
#define KBD_PENDING_AUX         2

typedef struct KBDState {
    uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
    uint8_t status;
    uint8_t mode;
    uint8_t outport;
    bool outport_present;
    /* Bitmask of devices with data available.  */
    uint8_t pending;
    void *kbd;
    void *mouse;

    qemu_irq irq_kbd;
    qemu_irq irq_mouse;
    qemu_irq a20_out;
    hwaddr mask;
} KBDState;

/* update irq and KBD_STAT_[MOUSE_]OBF */
/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
   incorrect, but it avoids having to simulate exact delays */
static void kbd_update_irq(KBDState *s)
{
    int irq_kbd_level, irq_mouse_level;

    irq_kbd_level = 0;
    irq_mouse_level = 0;
    s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
    s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
    if (s->pending) {
        s->status |= KBD_STAT_OBF;
        s->outport |= KBD_OUT_OBF;
        /* kbd data takes priority over aux data.  */
        if (s->pending == KBD_PENDING_AUX) {
            s->status |= KBD_STAT_MOUSE_OBF;
            s->outport |= KBD_OUT_MOUSE_OBF;
            if (s->mode & KBD_MODE_MOUSE_INT)
                irq_mouse_level = 1;
        } else {
            if ((s->mode & KBD_MODE_KBD_INT) &&
                !(s->mode & KBD_MODE_DISABLE_KBD))
                irq_kbd_level = 1;
        }
    }
    qemu_set_irq(s->irq_kbd, irq_kbd_level);
    qemu_set_irq(s->irq_mouse, irq_mouse_level);
}

static void kbd_update_kbd_irq(void *opaque, int level)
{
    KBDState *s = (KBDState *)opaque;

    if (level)
        s->pending |= KBD_PENDING_KBD;
    else
        s->pending &= ~KBD_PENDING_KBD;
    kbd_update_irq(s);
}

static void kbd_update_aux_irq(void *opaque, int level)
{
    KBDState *s = (KBDState *)opaque;

    if (level)
        s->pending |= KBD_PENDING_AUX;
    else
        s->pending &= ~KBD_PENDING_AUX;
    kbd_update_irq(s);
}

static uint64_t kbd_read_status(void *opaque, hwaddr addr,
                                unsigned size)
{
    KBDState *s = opaque;
    int val;
    val = s->status;
    trace_pckbd_kbd_read_status(val);
    return val;
}

static void kbd_queue(KBDState *s, int b, int aux)
{
    if (aux)
        ps2_queue(s->mouse, b);
    else
        ps2_queue(s->kbd, b);
}

static void outport_write(KBDState *s, uint32_t val)
{
    trace_pckbd_outport_write(val);
    s->outport = val;
    qemu_set_irq(s->a20_out, (val >> 1) & 1);
    if (!(val & 1)) {
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
    }
}

static void kbd_write_command(void *opaque, hwaddr addr,
                              uint64_t val, unsigned size)
{
    KBDState *s = opaque;

    trace_pckbd_kbd_write_command(val);

    /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
     * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
     * command specify the output port bits to be pulsed.
     * 0: Bit should be pulsed. 1: Bit should not be modified.
     * The only useful version of this command is pulsing bit 0,
     * which does a CPU reset.
     */
    if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
        if(!(val & 1))
            val = KBD_CCMD_RESET;
        else
            val = KBD_CCMD_NO_OP;
    }

    switch(val) {
    case KBD_CCMD_READ_MODE:
        kbd_queue(s, s->mode, 0);
        break;
    case KBD_CCMD_WRITE_MODE:
    case KBD_CCMD_WRITE_OBUF:
    case KBD_CCMD_WRITE_AUX_OBUF:
    case KBD_CCMD_WRITE_MOUSE:
    case KBD_CCMD_WRITE_OUTPORT:
        s->write_cmd = val;
        break;
    case KBD_CCMD_MOUSE_DISABLE:
        s->mode |= KBD_MODE_DISABLE_MOUSE;
        break;
    case KBD_CCMD_MOUSE_ENABLE:
        s->mode &= ~KBD_MODE_DISABLE_MOUSE;
        break;
    case KBD_CCMD_TEST_MOUSE:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_SELF_TEST:
        s->status |= KBD_STAT_SELFTEST;
        kbd_queue(s, 0x55, 0);
        break;
    case KBD_CCMD_KBD_TEST:
        kbd_queue(s, 0x00, 0);
        break;
    case KBD_CCMD_KBD_DISABLE:
        s->mode |= KBD_MODE_DISABLE_KBD;
        kbd_update_irq(s);
        break;
    case KBD_CCMD_KBD_ENABLE:
        s->mode &= ~KBD_MODE_DISABLE_KBD;
        kbd_update_irq(s);
        break;
    case KBD_CCMD_READ_INPORT:
        kbd_queue(s, 0x80, 0);
        break;
    case KBD_CCMD_READ_OUTPORT:
        kbd_queue(s, s->outport, 0);
        break;
    case KBD_CCMD_ENABLE_A20:
        qemu_irq_raise(s->a20_out);
        s->outport |= KBD_OUT_A20;
        break;
    case KBD_CCMD_DISABLE_A20:
        qemu_irq_lower(s->a20_out);
        s->outport &= ~KBD_OUT_A20;
        break;
    case KBD_CCMD_RESET:
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        break;
    case KBD_CCMD_NO_OP:
        /* ignore that */
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
        break;
    }
}

static uint64_t kbd_read_data(void *opaque, hwaddr addr,
                              unsigned size)
{
    KBDState *s = opaque;
    uint32_t val;

    if (s->pending == KBD_PENDING_AUX)
        val = ps2_read_data(s->mouse);
    else
        val = ps2_read_data(s->kbd);

    trace_pckbd_kbd_read_data(val);
    return val;
}

static void kbd_write_data(void *opaque, hwaddr addr,
                           uint64_t val, unsigned size)
{
    KBDState *s = opaque;

    trace_pckbd_kbd_write_data(val);

    switch(s->write_cmd) {
    case 0:
        ps2_write_keyboard(s->kbd, val);
        break;
    case KBD_CCMD_WRITE_MODE:
        s->mode = val;
        ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
        /* ??? */
        kbd_update_irq(s);
        break;
    case KBD_CCMD_WRITE_OBUF:
        kbd_queue(s, val, 0);
        break;
    case KBD_CCMD_WRITE_AUX_OBUF:
        kbd_queue(s, val, 1);
        break;
    case KBD_CCMD_WRITE_OUTPORT:
        outport_write(s, val);
        break;
    case KBD_CCMD_WRITE_MOUSE:
        ps2_write_mouse(s->mouse, val);
        break;
    default:
        break;
    }
    s->write_cmd = 0;
}

static void kbd_reset(void *opaque)
{
    KBDState *s = opaque;

    s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
    s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
    s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES;
    s->outport_present = false;
}

static uint8_t kbd_outport_default(KBDState *s)
{
    return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES
           | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
           | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
}

static int kbd_outport_post_load(void *opaque, int version_id)
{
    KBDState *s = opaque;
    s->outport_present = true;
    return 0;
}

static bool kbd_outport_needed(void *opaque)
{
    KBDState *s = opaque;
    return s->outport != kbd_outport_default(s);
}

static const VMStateDescription vmstate_kbd_outport = {
    .name = "pckbd_outport",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = kbd_outport_post_load,
    .needed = kbd_outport_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(outport, KBDState),
        VMSTATE_END_OF_LIST()
    }
};

static int kbd_post_load(void *opaque, int version_id)
{
    KBDState *s = opaque;
    if (!s->outport_present) {
        s->outport = kbd_outport_default(s);
    }
    s->outport_present = false;
    return 0;
}

static const VMStateDescription vmstate_kbd = {
    .name = "pckbd",
    .version_id = 3,
    .minimum_version_id = 3,
    .post_load = kbd_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(write_cmd, KBDState),
        VMSTATE_UINT8(status, KBDState),
        VMSTATE_UINT8(mode, KBDState),
        VMSTATE_UINT8(pending, KBDState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_kbd_outport,
        NULL
    }
};

/* Memory mapped interface */
static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
{
    KBDState *s = opaque;

    if (addr & s->mask)
        return kbd_read_status(s, 0, 1) & 0xff;
    else
        return kbd_read_data(s, 0, 1) & 0xff;
}

static void kbd_mm_writefn(void *opaque, hwaddr addr,
                           uint64_t value, unsigned size)
{
    KBDState *s = opaque;

    if (addr & s->mask)
        kbd_write_command(s, 0, value & 0xff, 1);
    else
        kbd_write_data(s, 0, value & 0xff, 1);
}


static const MemoryRegionOps i8042_mmio_ops = {
    .read = kbd_mm_readfn,
    .write = kbd_mm_writefn,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask)
{
    KBDState *s = g_malloc0(sizeof(KBDState));

    s->irq_kbd = kbd_irq;
    s->irq_mouse = mouse_irq;
    s->mask = mask;

    vmstate_register(NULL, 0, &vmstate_kbd, s);

    memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}

#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)

typedef struct ISAKBDState {
    ISADevice parent_obj;

    KBDState kbd;
    MemoryRegion io[2];
} ISAKBDState;

void i8042_isa_mouse_fake_event(void *opaque)
{
    ISADevice *dev = opaque;
    ISAKBDState *isa = I8042(dev);
    KBDState *s = &isa->kbd;

    ps2_mouse_fake_event(s->mouse);
}

void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
{
    qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
}

static const VMStateDescription vmstate_kbd_isa = {
    .name = "pckbd",
    .version_id = 3,
    .minimum_version_id = 3,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
        VMSTATE_END_OF_LIST()
    }
};

static const MemoryRegionOps i8042_data_ops = {
    .read = kbd_read_data,
    .write = kbd_write_data,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static const MemoryRegionOps i8042_cmd_ops = {
    .read = kbd_read_status,
    .write = kbd_write_command,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void i8042_initfn(Object *obj)
{
    ISAKBDState *isa_s = I8042(obj);
    KBDState *s = &isa_s->kbd;

    memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
                          "i8042-data", 1);
    memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
                          "i8042-cmd", 1);

    qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
}

static void i8042_realizefn(DeviceState *dev, Error **errp)
{
    ISADevice *isadev = ISA_DEVICE(dev);
    ISAKBDState *isa_s = I8042(dev);
    KBDState *s = &isa_s->kbd;

    isa_init_irq(isadev, &s->irq_kbd, 1);
    isa_init_irq(isadev, &s->irq_mouse, 12);

    isa_register_ioport(isadev, isa_s->io + 0, 0x60);
    isa_register_ioport(isadev, isa_s->io + 1, 0x64);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}

static void i8042_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = i8042_realizefn;
    dc->vmsd = &vmstate_kbd_isa;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo i8042_info = {
    .name          = TYPE_I8042,
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(ISAKBDState),
    .instance_init = i8042_initfn,
    .class_init    = i8042_class_initfn,
};

static void i8042_register_types(void)
{
    type_register_static(&i8042_info);
}

type_init(i8042_register_types)
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU PC keyboard emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0430891c	24	#include "qemu/osdep.h"
c2e846bb	25	#include "qemu/log.h"
83c9f4ca	26	#include "hw/hw.h"
0d09e41a PB	27	#include "hw/isa/isa.h"
	28	#include "hw/i386/pc.h"
	29	#include "hw/input/ps2.h"
47973a2d	30	#include "hw/input/i8042.h"
9c17d615	31	#include "sysemu/sysemu.h"
80cabfad	32
65b182c3	33	#include "trace.h"
80cabfad	34
80cabfad FB	35	/* Keyboard Controller Commands */
	36	#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
	37	#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
	38	#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
	39	#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
	40	#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
	41	#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
	42	#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
	43	#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
	44	#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
	45	#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
	46	#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
	47	#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
	48	#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
	49	#define KBD_CCMD_WRITE_OBUF 0xD2
	50	#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
7d37435b	51	initiated by the auxiliary device */
80cabfad FB	52	#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
	53	#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
	54	#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
5ccaa4ce BK	55	#define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
	56	#define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
	57	#define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
80cabfad FB	58
	59	/* Keyboard Commands */
	60	#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
	61	#define KBD_CMD_ECHO 0xEE
	62	#define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
	63	#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
	64	#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
	65	#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
	66	#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
	67	#define KBD_CMD_RESET 0xFF /* Reset */
	68
	69	/* Keyboard Replies */
	70	#define KBD_REPLY_POR 0xAA /* Power on reset */
	71	#define KBD_REPLY_ACK 0xFA /* Command ACK */
	72	#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
	73
	74	/* Status Register Bits */
	75	#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
	76	#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
	77	#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
	78	#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
	79	#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
	80	#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
	81	#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
	82	#define KBD_STAT_PERR 0x80 /* Parity error */
	83
	84	/* Controller Mode Register Bits */
	85	#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
	86	#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
	87	#define KBD_MODE_SYS 0x04 /* The system flag (?) */
	88	#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
	89	#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
	90	#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
	91	#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
	92	#define KBD_MODE_RFU 0x80
	93
956a3e6b BS	94	/* Output Port Bits */
	95	#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
	96	#define KBD_OUT_A20 0x02 /* x86 only */
	97	#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
	98	#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
	99
d13c0404 PB	100	/* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
	101	* We make the default value of the outport include these four bits,
	102	* so that the subsection is rarely necessary.
	103	*/
	104	#define KBD_OUT_ONES 0xcc
	105
80cabfad FB	106	/* Mouse Commands */
	107	#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
	108	#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
	109	#define AUX_SET_RES 0xE8 /* Set resolution */
	110	#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
	111	#define AUX_SET_STREAM 0xEA /* Set stream mode */
	112	#define AUX_POLL 0xEB /* Poll */
	113	#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
	114	#define AUX_SET_WRAP 0xEE /* Set wrap mode */
	115	#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
	116	#define AUX_GET_TYPE 0xF2 /* Get type */
	117	#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
	118	#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
	119	#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
	120	#define AUX_SET_DEFAULT 0xF6
	121	#define AUX_RESET 0xFF /* Reset aux device */
	122	#define AUX_ACK 0xFA /* Command byte ACK. */
	123
	124	#define MOUSE_STATUS_REMOTE 0x40
	125	#define MOUSE_STATUS_ENABLED 0x20
	126	#define MOUSE_STATUS_SCALE21 0x10
	127
daa57963 FB	128	#define KBD_PENDING_KBD 1
daa57963 FB	129	#define KBD_PENDING_AUX 2
80cabfad FB	130
80cabfad FB	131	typedef struct KBDState {
80cabfad FB	132	uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
	133	uint8_t status;
	134	uint8_t mode;
956a3e6b	135	uint8_t outport;
a28fe7e3	136	bool outport_present;
daa57963	137	/* Bitmask of devices with data available. */
7783e9f0	138	uint8_t pending;
daa57963 FB	139	void *kbd;
daa57963 FB	140	void *mouse;
b7678d96	141
d537cf6c PB	142	qemu_irq irq_kbd;
d537cf6c PB	143	qemu_irq irq_mouse;
3115b9e2	144	qemu_irq a20_out;
a8170e5e	145	hwaddr mask;
80cabfad FB	146	} KBDState;
80cabfad FB	147
80cabfad FB	148	/* update irq and KBD_STAT_[MOUSE_]OBF */
	149	/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
	150	incorrect, but it avoids having to simulate exact delays */
	151	static void kbd_update_irq(KBDState *s)
	152	{
b7678d96	153	int irq_kbd_level, irq_mouse_level;
80cabfad	154
b7678d96 TS	155	irq_kbd_level = 0;
b7678d96 TS	156	irq_mouse_level = 0;
80cabfad	157	s->status &= ~(KBD_STAT_OBF \| KBD_STAT_MOUSE_OBF);
956a3e6b	158	s->outport &= ~(KBD_OUT_OBF \| KBD_OUT_MOUSE_OBF);
daa57963	159	if (s->pending) {
80cabfad	160	s->status \|= KBD_STAT_OBF;
956a3e6b	161	s->outport \|= KBD_OUT_OBF;
b92bb99b	162	/* kbd data takes priority over aux data. */
daa57963	163	if (s->pending == KBD_PENDING_AUX) {
80cabfad	164	s->status \|= KBD_STAT_MOUSE_OBF;
956a3e6b	165	s->outport \|= KBD_OUT_MOUSE_OBF;
80cabfad	166	if (s->mode & KBD_MODE_MOUSE_INT)
b7678d96	167	irq_mouse_level = 1;
80cabfad	168	} else {
5fafdf24	169	if ((s->mode & KBD_MODE_KBD_INT) &&
80cabfad	170	!(s->mode & KBD_MODE_DISABLE_KBD))
b7678d96	171	irq_kbd_level = 1;
80cabfad FB	172	}
80cabfad FB	173	}
d537cf6c PB	174	qemu_set_irq(s->irq_kbd, irq_kbd_level);
d537cf6c PB	175	qemu_set_irq(s->irq_mouse, irq_mouse_level);
80cabfad FB	176	}
80cabfad FB	177
daa57963	178	static void kbd_update_kbd_irq(void *opaque, int level)
80cabfad	179	{
daa57963	180	KBDState s = (KBDState )opaque;
80cabfad	181
daa57963 FB	182	if (level)
daa57963 FB	183	s->pending \|= KBD_PENDING_KBD;
80cabfad	184	else
daa57963	185	s->pending &= ~KBD_PENDING_KBD;
80cabfad FB	186	kbd_update_irq(s);
	187	}
	188
daa57963	189	static void kbd_update_aux_irq(void *opaque, int level)
80cabfad	190	{
daa57963 FB	191	KBDState s = (KBDState )opaque;
	192
	193	if (level)
	194	s->pending \|= KBD_PENDING_AUX;
	195	else
	196	s->pending &= ~KBD_PENDING_AUX;
	197	kbd_update_irq(s);
80cabfad FB	198	}
80cabfad FB	199
d540bfe0 AG	200	static uint64_t kbd_read_status(void *opaque, hwaddr addr,
d540bfe0 AG	201	unsigned size)
80cabfad	202	{
b41a2cd1	203	KBDState *s = opaque;
80cabfad FB	204	int val;
80cabfad FB	205	val = s->status;
65b182c3	206	trace_pckbd_kbd_read_status(val);
80cabfad FB	207	return val;
	208	}
	209
daa57963 FB	210	static void kbd_queue(KBDState *s, int b, int aux)
	211	{
	212	if (aux)
	213	ps2_queue(s->mouse, b);
	214	else
	215	ps2_queue(s->kbd, b);
	216	}
	217
4b78a802	218	static void outport_write(KBDState *s, uint32_t val)
956a3e6b	219	{
65b182c3	220	trace_pckbd_outport_write(val);
956a3e6b	221	s->outport = val;
3115b9e2	222	qemu_set_irq(s->a20_out, (val >> 1) & 1);
956a3e6b	223	if (!(val & 1)) {
cf83f140	224	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
956a3e6b BS	225	}
	226	}
	227
d540bfe0 AG	228	static void kbd_write_command(void *opaque, hwaddr addr,
d540bfe0 AG	229	uint64_t val, unsigned size)
80cabfad	230	{
b41a2cd1	231	KBDState *s = opaque;
80cabfad	232
65b182c3	233	trace_pckbd_kbd_write_command(val);
5ccaa4ce BK	234
	235	/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
	236	* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
	237	* command specify the output port bits to be pulsed.
	238	* 0: Bit should be pulsed. 1: Bit should not be modified.
	239	* The only useful version of this command is pulsing bit 0,
	240	* which does a CPU reset.
	241	*/
	242	if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
	243	if(!(val & 1))
	244	val = KBD_CCMD_RESET;
	245	else
	246	val = KBD_CCMD_NO_OP;
	247	}
	248
80cabfad FB	249	switch(val) {
80cabfad FB	250	case KBD_CCMD_READ_MODE:
889bec69	251	kbd_queue(s, s->mode, 0);
80cabfad FB	252	break;
	253	case KBD_CCMD_WRITE_MODE:
	254	case KBD_CCMD_WRITE_OBUF:
	255	case KBD_CCMD_WRITE_AUX_OBUF:
	256	case KBD_CCMD_WRITE_MOUSE:
	257	case KBD_CCMD_WRITE_OUTPORT:
	258	s->write_cmd = val;
	259	break;
	260	case KBD_CCMD_MOUSE_DISABLE:
	261	s->mode \|= KBD_MODE_DISABLE_MOUSE;
	262	break;
	263	case KBD_CCMD_MOUSE_ENABLE:
	264	s->mode &= ~KBD_MODE_DISABLE_MOUSE;
	265	break;
	266	case KBD_CCMD_TEST_MOUSE:
	267	kbd_queue(s, 0x00, 0);
	268	break;
	269	case KBD_CCMD_SELF_TEST:
	270	s->status \|= KBD_STAT_SELFTEST;
	271	kbd_queue(s, 0x55, 0);
	272	break;
	273	case KBD_CCMD_KBD_TEST:
	274	kbd_queue(s, 0x00, 0);
	275	break;
	276	case KBD_CCMD_KBD_DISABLE:
	277	s->mode \|= KBD_MODE_DISABLE_KBD;
	278	kbd_update_irq(s);
	279	break;
	280	case KBD_CCMD_KBD_ENABLE:
	281	s->mode &= ~KBD_MODE_DISABLE_KBD;
	282	kbd_update_irq(s);
	283	break;
	284	case KBD_CCMD_READ_INPORT:
f1b7e0e4	285	kbd_queue(s, 0x80, 0);
80cabfad FB	286	break;
80cabfad FB	287	case KBD_CCMD_READ_OUTPORT:
956a3e6b	288	kbd_queue(s, s->outport, 0);
80cabfad	289	break;
80cabfad	290	case KBD_CCMD_ENABLE_A20:
3115b9e2	291	qemu_irq_raise(s->a20_out);
956a3e6b	292	s->outport \|= KBD_OUT_A20;
80cabfad FB	293	break;
80cabfad FB	294	case KBD_CCMD_DISABLE_A20:
3115b9e2	295	qemu_irq_lower(s->a20_out);
956a3e6b	296	s->outport &= ~KBD_OUT_A20;
80cabfad	297	break;
80cabfad	298	case KBD_CCMD_RESET:
cf83f140	299	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
80cabfad	300	break;
5ccaa4ce BK	301	case KBD_CCMD_NO_OP:
5ccaa4ce BK	302	/* ignore that */
80cabfad FB	303	break;
80cabfad FB	304	default:
c2e846bb PMD	305	qemu_log_mask(LOG_GUEST_ERROR,
c2e846bb PMD	306	"unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
80cabfad FB	307	break;
	308	}
	309	}
	310
d540bfe0 AG	311	static uint64_t kbd_read_data(void *opaque, hwaddr addr,
d540bfe0 AG	312	unsigned size)
80cabfad	313	{
63066f4f	314	KBDState *s = opaque;
e41c0f26	315	uint32_t val;
80cabfad	316
daa57963	317	if (s->pending == KBD_PENDING_AUX)
e41c0f26 AZ	318	val = ps2_read_data(s->mouse);
	319	else
	320	val = ps2_read_data(s->kbd);
80cabfad	321
65b182c3	322	trace_pckbd_kbd_read_data(val);
e41c0f26	323	return val;
80cabfad FB	324	}
80cabfad FB	325
d540bfe0 AG	326	static void kbd_write_data(void *opaque, hwaddr addr,
d540bfe0 AG	327	uint64_t val, unsigned size)
80cabfad	328	{
b41a2cd1	329	KBDState *s = opaque;
80cabfad	330
65b182c3	331	trace_pckbd_kbd_write_data(val);
80cabfad FB	332
	333	switch(s->write_cmd) {
	334	case 0:
daa57963	335	ps2_write_keyboard(s->kbd, val);
80cabfad FB	336	break;
	337	case KBD_CCMD_WRITE_MODE:
	338	s->mode = val;
f94f5d71	339	ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
daa57963	340	/* ??? */
80cabfad FB	341	kbd_update_irq(s);
	342	break;
	343	case KBD_CCMD_WRITE_OBUF:
	344	kbd_queue(s, val, 0);
	345	break;
	346	case KBD_CCMD_WRITE_AUX_OBUF:
	347	kbd_queue(s, val, 1);
	348	break;
	349	case KBD_CCMD_WRITE_OUTPORT:
4b78a802	350	outport_write(s, val);
80cabfad FB	351	break;
80cabfad FB	352	case KBD_CCMD_WRITE_MOUSE:
daa57963	353	ps2_write_mouse(s->mouse, val);
80cabfad FB	354	break;
	355	default:
	356	break;
	357	}
	358	s->write_cmd = 0;
	359	}
	360
d7d02e3c	361	static void kbd_reset(void *opaque)
80cabfad	362	{
d7d02e3c	363	KBDState *s = opaque;
80cabfad	364
80cabfad FB	365	s->mode = KBD_MODE_KBD_INT \| KBD_MODE_MOUSE_INT;
80cabfad FB	366	s->status = KBD_STAT_CMD \| KBD_STAT_UNLOCKED;
d13c0404	367	s->outport = KBD_OUT_RESET \| KBD_OUT_A20 \| KBD_OUT_ONES;
a28fe7e3 PD	368	s->outport_present = false;
	369	}
	370
	371	static uint8_t kbd_outport_default(KBDState *s)
	372	{
d13c0404	373	return KBD_OUT_RESET \| KBD_OUT_A20 \| KBD_OUT_ONES
a28fe7e3 PD	374	\| (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
	375	\| (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
	376	}
	377
	378	static int kbd_outport_post_load(void *opaque, int version_id)
	379	{
	380	KBDState *s = opaque;
	381	s->outport_present = true;
	382	return 0;
	383	}
	384
5cd8cada JQ	385	static bool kbd_outport_needed(void *opaque)
	386	{
	387	KBDState *s = opaque;
	388	return s->outport != kbd_outport_default(s);
	389	}
	390
a28fe7e3 PD	391	static const VMStateDescription vmstate_kbd_outport = {
	392	.name = "pckbd_outport",
	393	.version_id = 1,
	394	.minimum_version_id = 1,
	395	.post_load = kbd_outport_post_load,
5cd8cada	396	.needed = kbd_outport_needed,
a28fe7e3 PD	397	.fields = (VMStateField[]) {
	398	VMSTATE_UINT8(outport, KBDState),
	399	VMSTATE_END_OF_LIST()
	400	}
	401	};
	402
a28fe7e3 PD	403	static int kbd_post_load(void *opaque, int version_id)
	404	{
	405	KBDState *s = opaque;
	406	if (!s->outport_present) {
	407	s->outport = kbd_outport_default(s);
	408	}
	409	s->outport_present = false;
	410	return 0;
80cabfad FB	411	}
80cabfad FB	412
3c619b59 JQ	413	static const VMStateDescription vmstate_kbd = {
	414	.name = "pckbd",
	415	.version_id = 3,
	416	.minimum_version_id = 3,
a28fe7e3	417	.post_load = kbd_post_load,
d49805ae	418	.fields = (VMStateField[]) {
3c619b59 JQ	419	VMSTATE_UINT8(write_cmd, KBDState),
	420	VMSTATE_UINT8(status, KBDState),
	421	VMSTATE_UINT8(mode, KBDState),
	422	VMSTATE_UINT8(pending, KBDState),
	423	VMSTATE_END_OF_LIST()
a28fe7e3	424	},
5cd8cada JQ	425	.subsections = (const VMStateDescription*[]) {
	426	&vmstate_kbd_outport,
	427	NULL
3c619b59 JQ	428	}
3c619b59 JQ	429	};
675376f2	430
b92bb99b	431	/* Memory mapped interface */
5876503c	432	static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
b92bb99b TS	433	{
	434	KBDState *s = opaque;
	435
4efbe58f	436	if (addr & s->mask)
d540bfe0	437	return kbd_read_status(s, 0, 1) & 0xff;
4efbe58f	438	else
d540bfe0	439	return kbd_read_data(s, 0, 1) & 0xff;
b92bb99b TS	440	}
b92bb99b TS	441
5876503c PM	442	static void kbd_mm_writefn(void *opaque, hwaddr addr,
5876503c PM	443	uint64_t value, unsigned size)
b92bb99b TS	444	{
	445	KBDState *s = opaque;
	446
4efbe58f	447	if (addr & s->mask)
d540bfe0	448	kbd_write_command(s, 0, value & 0xff, 1);
4efbe58f	449	else
d540bfe0	450	kbd_write_data(s, 0, value & 0xff, 1);
b92bb99b TS	451	}
b92bb99b TS	452
5876503c	453
dbff76ac	454	static const MemoryRegionOps i8042_mmio_ops = {
5876503c PM	455	.read = kbd_mm_readfn,
	456	.write = kbd_mm_writefn,
	457	.valid.min_access_size = 1,
	458	.valid.max_access_size = 4,
dbff76ac	459	.endianness = DEVICE_NATIVE_ENDIAN,
b92bb99b TS	460	};
b92bb99b TS	461
71db710f	462	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dbff76ac	463	MemoryRegion *region, ram_addr_t size,
a8170e5e	464	hwaddr mask)
b92bb99b	465	{
7267c094	466	KBDState *s = g_malloc0(sizeof(KBDState));
b92bb99b TS	467
	468	s->irq_kbd = kbd_irq;
	469	s->irq_mouse = mouse_irq;
4efbe58f	470	s->mask = mask;
b92bb99b	471
0be71e32	472	vmstate_register(NULL, 0, &vmstate_kbd, s);
dbff76ac	473
2c9b15ca	474	memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
b92bb99b TS	475
	476	s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
	477	s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
a08d4367	478	qemu_register_reset(kbd_reset, s);
b92bb99b	479	}
da85ccfb	480
a2e0b863 AF	481	#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
a2e0b863 AF	482
da85ccfb	483	typedef struct ISAKBDState {
a2e0b863 AF	484	ISADevice parent_obj;
a2e0b863 AF	485
dbff76ac RH	486	KBDState kbd;
dbff76ac RH	487	MemoryRegion io[2];
da85ccfb GH	488	} ISAKBDState;
da85ccfb GH	489
956a3e6b BS	490	void i8042_isa_mouse_fake_event(void *opaque)
	491	{
	492	ISADevice *dev = opaque;
a2e0b863 AF	493	ISAKBDState *isa = I8042(dev);
a2e0b863 AF	494	KBDState *s = &isa->kbd;
956a3e6b BS	495
	496	ps2_mouse_fake_event(s->mouse);
	497	}
	498
d80fe99d	499	void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
956a3e6b	500	{
d80fe99d	501	qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
956a3e6b BS	502	}
956a3e6b BS	503
d05ac8fa	504	static const VMStateDescription vmstate_kbd_isa = {
be73cfe2 JQ	505	.name = "pckbd",
	506	.version_id = 3,
	507	.minimum_version_id = 3,
d49805ae	508	.fields = (VMStateField[]) {
be73cfe2 JQ	509	VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
	510	VMSTATE_END_OF_LIST()
	511	}
	512	};
	513
dbff76ac	514	static const MemoryRegionOps i8042_data_ops = {
d540bfe0 AG	515	.read = kbd_read_data,
	516	.write = kbd_write_data,
	517	.impl = {
	518	.min_access_size = 1,
	519	.max_access_size = 1,
	520	},
	521	.endianness = DEVICE_LITTLE_ENDIAN,
dbff76ac RH	522	};
	523
	524	static const MemoryRegionOps i8042_cmd_ops = {
d540bfe0 AG	525	.read = kbd_read_status,
	526	.write = kbd_write_command,
	527	.impl = {
	528	.min_access_size = 1,
	529	.max_access_size = 1,
	530	},
	531	.endianness = DEVICE_LITTLE_ENDIAN,
dbff76ac RH	532	};
dbff76ac RH	533
db895a1e	534	static void i8042_initfn(Object *obj)
da85ccfb	535	{
db895a1e	536	ISAKBDState *isa_s = I8042(obj);
dbff76ac	537	KBDState *s = &isa_s->kbd;
da85ccfb	538
1437c94b PB	539	memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
	540	"i8042-data", 1);
	541	memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
	542	"i8042-cmd", 1);
3115b9e2 EV	543
3115b9e2 EV	544	qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
db895a1e AF	545	}
	546
	547	static void i8042_realizefn(DeviceState dev, Error *errp)
	548	{
	549	ISADevice *isadev = ISA_DEVICE(dev);
	550	ISAKBDState *isa_s = I8042(dev);
	551	KBDState *s = &isa_s->kbd;
	552
	553	isa_init_irq(isadev, &s->irq_kbd, 1);
	554	isa_init_irq(isadev, &s->irq_mouse, 12);
	555
	556	isa_register_ioport(isadev, isa_s->io + 0, 0x60);
	557	isa_register_ioport(isadev, isa_s->io + 1, 0x64);
da85ccfb GH	558
	559	s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
	560	s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
da85ccfb GH	561	qemu_register_reset(kbd_reset, s);
	562	}
	563
8f04ee08 AL	564	static void i8042_class_initfn(ObjectClass klass, void data)
8f04ee08 AL	565	{
39bffca2	566	DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e AF	567
db895a1e AF	568	dc->realize = i8042_realizefn;
39bffca2	569	dc->vmsd = &vmstate_kbd_isa;
cbe9ed73	570	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
8f04ee08 AL	571	}
8f04ee08 AL	572
8c43a6f0	573	static const TypeInfo i8042_info = {
a2e0b863	574	.name = TYPE_I8042,
39bffca2 AL	575	.parent = TYPE_ISA_DEVICE,
39bffca2 AL	576	.instance_size = sizeof(ISAKBDState),
db895a1e	577	.instance_init = i8042_initfn,
39bffca2	578	.class_init = i8042_class_initfn,
da85ccfb GH	579	};
da85ccfb GH	580
83f7d43a	581	static void i8042_register_types(void)
da85ccfb	582	{
39bffca2	583	type_register_static(&i8042_info);
da85ccfb	584	}
83f7d43a AF	585
83f7d43a AF	586	type_init(i8042_register_types)