[qemu.git] / hw / intc / xics_spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
#include "qapi/visitor.h"

/*
 * Guest interfaces
 */

static bool check_emulated_xics(SpaprMachineState *spapr, const char *func)
{
    if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ||
        kvm_irqchip_in_kernel()) {
        error_report("pseries: %s must only be called for emulated XICS",
                     func);
        return false;
    }

    return true;
}

#define CHECK_EMULATED_XICS_HCALL(spapr)               \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            return H_HARDWARE;                         \
        }                                              \
    } while (0)

static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong mfrr = args[1];
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    icp_set_mfrr(icp, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
                             target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    args[1] = cpu_get_host_ticks();
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
    return H_SUCCESS;
}

static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
                            target_ulong opcode, target_ulong *args)
{
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
    uint32_t mfrr;
    uint32_t xirr;

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    xirr = icp_ipoll(icp, &mfrr);

    args[0] = xirr;
    args[1] = mfrr;

    return H_SUCCESS;
}

#define CHECK_EMULATED_XICS_RTAS(spapr, rets)          \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            rtas_st((rets), 0, RTAS_OUT_HW_ERROR);     \
            return;                                    \
        }                                              \
    } while (0)

static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno, server, priority;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
        || (priority > 0xff)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_write_xive(ics, srcno, server, priority, priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
    srcno = nr - ics->offset;
    rtas_st(rets, 1, ics->irqs[srcno].server);
    rtas_st(rets, 2, ics->irqs[srcno].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
                   ics->irqs[srcno].priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_write_xive(ics, srcno, ics->irqs[srcno].server,
                   ics->irqs[srcno].saved_priority,
                   ics->irqs[srcno].saved_priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void ics_spapr_realize(DeviceState *dev, Error **errp)
{
    ICSState *ics = ICS_SPAPR(dev);
    ICSStateClass *icsc = ICS_GET_CLASS(ics);
    Error *local_err = NULL;

    icsc->parent_realize(dev, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_XIRR_X, h_xirr_x);
    spapr_register_hypercall(H_EOI, h_eoi);
    spapr_register_hypercall(H_IPOLL, h_ipoll);
}

static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_servers,
                          void *fdt, uint32_t phandle)
{
    uint32_t interrupt_server_ranges_prop[] = {
        0, cpu_to_be32(nr_servers),
    };
    int node;

    _FDT(node = fdt_add_subnode(fdt, 0, "interrupt-controller"));

    _FDT(fdt_setprop_string(fdt, node, "device_type",
                            "PowerPC-External-Interrupt-Presentation"));
    _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
    _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
    _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
                     interrupt_server_ranges_prop,
                     sizeof(interrupt_server_ranges_prop)));
    _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
    _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
    _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}

static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc,
                                       PowerPCCPU *cpu, Error **errp)
{
    ICSState *ics = ICS_SPAPR(intc);
    Object *obj;
    SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);

    obj = icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp);
    if (!obj) {
        return -1;
    }

    spapr_cpu->icp = ICP(obj);
    return 0;
}

static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,
                                     PowerPCCPU *cpu)
{
    icp_reset(spapr_cpu_state(cpu)->icp);
}

static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc,
                                        PowerPCCPU *cpu)
{
    SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);

    icp_destroy(spapr_cpu->icp);
    spapr_cpu->icp = NULL;
}

static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,
                                bool lsi, Error **errp)
{
    ICSState *ics = ICS_SPAPR(intc);

    assert(ics);
    assert(ics_valid_irq(ics, irq));

    if (!ics_irq_free(ics, irq - ics->offset)) {
        error_setg(errp, "IRQ %d is not free", irq);
        return -EBUSY;
    }

    ics_set_irq_type(ics, irq - ics->offset, lsi);
    return 0;
}

static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq)
{
    ICSState *ics = ICS_SPAPR(intc);
    uint32_t srcno = irq - ics->offset;

    assert(ics_valid_irq(ics, irq));

    memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState));
}

static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val)
{
    ICSState *ics = ICS_SPAPR(intc);
    uint32_t srcno = irq - ics->offset;

    ics_set_irq(ics, srcno, val);
}

static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon)
{
    ICSState *ics = ICS_SPAPR(intc);
    CPUState *cs;

    CPU_FOREACH(cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
    }

    ics_pic_print_info(ics, mon);
}

static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
{
    if (!kvm_irqchip_in_kernel()) {
        CPUState *cs;
        CPU_FOREACH(cs) {
            PowerPCCPU *cpu = POWERPC_CPU(cs);
            icp_resend(spapr_cpu_state(cpu)->icp);
        }
    }
    return 0;
}

static int xics_spapr_activate(SpaprInterruptController *intc,
                               uint32_t nr_servers, Error **errp)
{
    if (kvm_enabled()) {
        return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
    }
    return 0;
}

static void xics_spapr_deactivate(SpaprInterruptController *intc)
{
    if (kvm_irqchip_in_kernel()) {
        xics_kvm_disconnect(intc);
    }
}

static void ics_spapr_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    ICSStateClass *isc = ICS_CLASS(klass);
    SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);

    device_class_set_parent_realize(dc, ics_spapr_realize,
                                    &isc->parent_realize);
    sicc->activate = xics_spapr_activate;
    sicc->deactivate = xics_spapr_deactivate;
    sicc->cpu_intc_create = xics_spapr_cpu_intc_create;
    sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;
    sicc->cpu_intc_destroy = xics_spapr_cpu_intc_destroy;
    sicc->claim_irq = xics_spapr_claim_irq;
    sicc->free_irq = xics_spapr_free_irq;
    sicc->set_irq = xics_spapr_set_irq;
    sicc->print_info = xics_spapr_print_info;
    sicc->dt = xics_spapr_dt;
    sicc->post_load = xics_spapr_post_load;
}

static const TypeInfo ics_spapr_info = {
    .name = TYPE_ICS_SPAPR,
    .parent = TYPE_ICS,
    .class_init = ics_spapr_class_init,
    .interfaces = (InterfaceInfo[]) {
        { TYPE_SPAPR_INTC },
        { }
    },
};

static void xics_spapr_register_types(void)
{
    type_register_static(&ics_spapr_info);
}

type_init(xics_spapr_register_types)
Commit	Line	Data
9c7027ba BH	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "cpu.h"
9c7027ba BH	30	#include "trace.h"
	31	#include "qemu/timer.h"
	32	#include "hw/ppc/spapr.h"
a28b9a5a	33	#include "hw/ppc/spapr_cpu_core.h"
9c7027ba	34	#include "hw/ppc/xics.h"
a51d5afc	35	#include "hw/ppc/xics_spapr.h"
9b9a1908	36	#include "hw/ppc/fdt.h"
9c7027ba	37	#include "qapi/visitor.h"
9c7027ba BH	38
	39	/*
	40	* Guest interfaces
	41	*/
	42
25c79a30	43	static bool check_emulated_xics(SpaprMachineState spapr, const char func)
d9715d67	44	{
25c79a30 GK	45	if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) \|\|
	46	kvm_irqchip_in_kernel()) {
	47	error_report("pseries: %s must only be called for emulated XICS",
d9715d67	48	func);
25c79a30	49	return false;
d9715d67 GK	50	}
d9715d67 GK	51
25c79a30	52	return true;
d9715d67 GK	53	}
d9715d67 GK	54
25c79a30 GK	55	#define CHECK_EMULATED_XICS_HCALL(spapr) \
	56	do { \
	57	if (!check_emulated_xics((spapr), __func__)) { \
	58	return H_HARDWARE; \
	59	} \
d9715d67 GK	60	} while (0)
d9715d67 GK	61
ce2918cb	62	static target_ulong h_cppr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	63	target_ulong opcode, target_ulong *args)
9c7027ba BH	64	{
9c7027ba BH	65	target_ulong cppr = args[0];
9c7027ba BH	66
25c79a30	67	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	68
a28b9a5a	69	icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
9c7027ba BH	70	return H_SUCCESS;
	71	}
	72
ce2918cb	73	static target_ulong h_ipi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	74	target_ulong opcode, target_ulong *args)
9c7027ba BH	75	{
9c7027ba	76	target_ulong mfrr = args[1];
06747ba6	77	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
9c7027ba	78
25c79a30	79	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	80
b4f27d71	81	if (!icp) {
9c7027ba BH	82	return H_PARAMETER;
	83	}
	84
b4f27d71	85	icp_set_mfrr(icp, mfrr);
9c7027ba BH	86	return H_SUCCESS;
	87	}
	88
ce2918cb	89	static target_ulong h_xirr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	90	target_ulong opcode, target_ulong *args)
9c7027ba BH	91	{
a28b9a5a	92	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	93
25c79a30	94	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	95
9c7027ba BH	96	args[0] = xirr;
	97	return H_SUCCESS;
	98	}
	99
ce2918cb	100	static target_ulong h_xirr_x(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	101	target_ulong opcode, target_ulong *args)
9c7027ba BH	102	{
a28b9a5a	103	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	104
25c79a30	105	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	106
9c7027ba BH	107	args[0] = xirr;
	108	args[1] = cpu_get_host_ticks();
	109	return H_SUCCESS;
	110	}
	111
ce2918cb	112	static target_ulong h_eoi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	113	target_ulong opcode, target_ulong *args)
9c7027ba BH	114	{
9c7027ba BH	115	target_ulong xirr = args[0];
9c7027ba BH	116
25c79a30	117	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	118
a28b9a5a	119	icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
9c7027ba BH	120	return H_SUCCESS;
	121	}
	122
ce2918cb	123	static target_ulong h_ipoll(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	124	target_ulong opcode, target_ulong *args)
9c7027ba BH	125	{
ebc184be	126	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
1cbd2220	127	uint32_t mfrr;
ebc184be BH	128	uint32_t xirr;
ebc184be BH	129
25c79a30	130	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	131
ebc184be BH	132	if (!icp) {
	133	return H_PARAMETER;
	134	}
	135
	136	xirr = icp_ipoll(icp, &mfrr);
9c7027ba	137
1cbd2220 BH	138	args[0] = xirr;
1cbd2220 BH	139	args[1] = mfrr;
9c7027ba BH	140
	141	return H_SUCCESS;
	142	}
	143
25c79a30 GK	144	#define CHECK_EMULATED_XICS_RTAS(spapr, rets) \
	145	do { \
	146	if (!check_emulated_xics((spapr), __func__)) { \
	147	rtas_st((rets), 0, RTAS_OUT_HW_ERROR); \
	148	return; \
	149	} \
d9715d67 GK	150	} while (0)
d9715d67 GK	151
ce2918cb	152	static void rtas_set_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	153	uint32_t token,
	154	uint32_t nargs, target_ulong args,
	155	uint32_t nret, target_ulong rets)
	156	{
681bfade	157	ICSState *ics = spapr->ics;
d4d7a59a	158	uint32_t nr, srcno, server, priority;
9c7027ba	159
25c79a30	160	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	161
9c7027ba BH	162	if ((nargs != 3) \|\| (nret != 1)) {
	163	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	164	return;
	165	}
cc706a53 BH	166	if (!ics) {
	167	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	168	return;
	169	}
9c7027ba BH	170
9c7027ba BH	171	nr = rtas_ld(args, 0);
06747ba6	172	server = rtas_ld(args, 1);
9c7027ba BH	173	priority = rtas_ld(args, 2);
9c7027ba BH	174
b4f27d71	175	if (!ics_valid_irq(ics, nr) \|\| !xics_icp_get(XICS_FABRIC(spapr), server)
9c7027ba BH	176	\|\| (priority > 0xff)) {
	177	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	178	return;
	179	}
	180
d4d7a59a	181	srcno = nr - ics->offset;
28976c99	182	ics_write_xive(ics, srcno, server, priority, priority);
9c7027ba BH	183
	184	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	185	}
	186
ce2918cb	187	static void rtas_get_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	188	uint32_t token,
	189	uint32_t nargs, target_ulong args,
	190	uint32_t nret, target_ulong rets)
	191	{
681bfade	192	ICSState *ics = spapr->ics;
d4d7a59a	193	uint32_t nr, srcno;
9c7027ba	194
25c79a30	195	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	196
9c7027ba BH	197	if ((nargs != 1) \|\| (nret != 3)) {
	198	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	199	return;
	200	}
cc706a53 BH	201	if (!ics) {
	202	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	203	return;
	204	}
9c7027ba BH	205
	206	nr = rtas_ld(args, 0);
	207
	208	if (!ics_valid_irq(ics, nr)) {
	209	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	210	return;
	211	}
	212
	213	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
d4d7a59a BH	214	srcno = nr - ics->offset;
	215	rtas_st(rets, 1, ics->irqs[srcno].server);
	216	rtas_st(rets, 2, ics->irqs[srcno].priority);
9c7027ba BH	217	}
9c7027ba BH	218
ce2918cb	219	static void rtas_int_off(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	220	uint32_t token,
	221	uint32_t nargs, target_ulong args,
	222	uint32_t nret, target_ulong rets)
	223	{
681bfade	224	ICSState *ics = spapr->ics;
d4d7a59a	225	uint32_t nr, srcno;
9c7027ba	226
25c79a30	227	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	228
9c7027ba BH	229	if ((nargs != 1) \|\| (nret != 1)) {
	230	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	231	return;
	232	}
cc706a53 BH	233	if (!ics) {
	234	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	235	return;
	236	}
9c7027ba BH	237
	238	nr = rtas_ld(args, 0);
	239
	240	if (!ics_valid_irq(ics, nr)) {
	241	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	242	return;
	243	}
	244
d4d7a59a	245	srcno = nr - ics->offset;
28976c99 DG	246	ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
28976c99 DG	247	ics->irqs[srcno].priority);
9c7027ba BH	248
	249	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	250	}
	251
ce2918cb	252	static void rtas_int_on(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	253	uint32_t token,
	254	uint32_t nargs, target_ulong args,
	255	uint32_t nret, target_ulong rets)
	256	{
681bfade	257	ICSState *ics = spapr->ics;
d4d7a59a	258	uint32_t nr, srcno;
9c7027ba	259
25c79a30	260	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	261
9c7027ba BH	262	if ((nargs != 1) \|\| (nret != 1)) {
	263	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	264	return;
	265	}
cc706a53 BH	266	if (!ics) {
	267	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	268	return;
	269	}
9c7027ba BH	270
	271	nr = rtas_ld(args, 0);
	272
	273	if (!ics_valid_irq(ics, nr)) {
	274	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	275	return;
	276	}
	277
d4d7a59a	278	srcno = nr - ics->offset;
28976c99 DG	279	ics_write_xive(ics, srcno, ics->irqs[srcno].server,
	280	ics->irqs[srcno].saved_priority,
	281	ics->irqs[srcno].saved_priority);
9c7027ba BH	282
	283	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	284	}
	285
9db8c551	286	static void ics_spapr_realize(DeviceState dev, Error *errp)
9c7027ba	287	{
9db8c551 DG	288	ICSState *ics = ICS_SPAPR(dev);
	289	ICSStateClass *icsc = ICS_GET_CLASS(ics);
	290	Error *local_err = NULL;
	291
	292	icsc->parent_realize(dev, &local_err);
	293	if (local_err) {
	294	error_propagate(errp, local_err);
	295	return;
	296	}
	297
9c7027ba BH	298	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
	299	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
	300	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
	301	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
	302
	303	spapr_register_hypercall(H_CPPR, h_cppr);
	304	spapr_register_hypercall(H_IPI, h_ipi);
	305	spapr_register_hypercall(H_XIRR, h_xirr);
	306	spapr_register_hypercall(H_XIRR_X, h_xirr_x);
	307	spapr_register_hypercall(H_EOI, h_eoi);
	308	spapr_register_hypercall(H_IPOLL, h_ipoll);
9c7027ba BH	309	}
9c7027ba BH	310
05289273 DG	311	static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_servers,
05289273 DG	312	void *fdt, uint32_t phandle)
9b9a1908 DG	313	{
9b9a1908 DG	314	uint32_t interrupt_server_ranges_prop[] = {
b0ec3129	315	0, cpu_to_be32(nr_servers),
9b9a1908 DG	316	};
	317	int node;
	318
14789694	319	_FDT(node = fdt_add_subnode(fdt, 0, "interrupt-controller"));
9b9a1908 DG	320
	321	_FDT(fdt_setprop_string(fdt, node, "device_type",
	322	"PowerPC-External-Interrupt-Presentation"));
	323	_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
	324	_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
	325	_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
	326	interrupt_server_ranges_prop,
	327	sizeof(interrupt_server_ranges_prop)));
	328	_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
	329	_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
	330	_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
	331	}
9db8c551	332
ebd6be08 DG	333	static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc,
	334	PowerPCCPU cpu, Error *errp)
	335	{
	336	ICSState *ics = ICS_SPAPR(intc);
	337	Object *obj;
	338	SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
	339
	340	obj = icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp);
	341	if (!obj) {
	342	return -1;
	343	}
	344
	345	spapr_cpu->icp = ICP(obj);
	346	return 0;
	347	}
	348
d49e8a9b CLG	349	static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,
	350	PowerPCCPU *cpu)
	351	{
	352	icp_reset(spapr_cpu_state(cpu)->icp);
	353	}
	354
0990ce6a GK	355	static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc,
	356	PowerPCCPU *cpu)
	357	{
	358	SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
	359
	360	icp_destroy(spapr_cpu->icp);
	361	spapr_cpu->icp = NULL;
	362	}
	363
0b0e52b1 DG	364	static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,
	365	bool lsi, Error **errp)
	366	{
	367	ICSState *ics = ICS_SPAPR(intc);
	368
	369	assert(ics);
	370	assert(ics_valid_irq(ics, irq));
	371
	372	if (!ics_irq_free(ics, irq - ics->offset)) {
	373	error_setg(errp, "IRQ %d is not free", irq);
	374	return -EBUSY;
	375	}
	376
	377	ics_set_irq_type(ics, irq - ics->offset, lsi);
	378	return 0;
	379	}
	380
	381	static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq)
	382	{
	383	ICSState *ics = ICS_SPAPR(intc);
	384	uint32_t srcno = irq - ics->offset;
	385
	386	assert(ics_valid_irq(ics, irq));
	387
	388	memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState));
	389	}
	390
7bcdbcca DG	391	static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val)
	392	{
	393	ICSState *ics = ICS_SPAPR(intc);
	394	uint32_t srcno = irq - ics->offset;
	395
	396	ics_set_irq(ics, srcno, val);
	397	}
	398
328d8eb2 DG	399	static void xics_spapr_print_info(SpaprInterruptController intc, Monitor mon)
	400	{
	401	ICSState *ics = ICS_SPAPR(intc);
	402	CPUState *cs;
	403
	404	CPU_FOREACH(cs) {
	405	PowerPCCPU *cpu = POWERPC_CPU(cs);
	406
	407	icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
	408	}
	409
	410	ics_pic_print_info(ics, mon);
	411	}
	412
605994e5 DG	413	static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
	414	{
	415	if (!kvm_irqchip_in_kernel()) {
	416	CPUState *cs;
	417	CPU_FOREACH(cs) {
	418	PowerPCCPU *cpu = POWERPC_CPU(cs);
	419	icp_resend(spapr_cpu_state(cpu)->icp);
	420	}
	421	}
	422	return 0;
	423	}
	424
4ffb7496 GK	425	static int xics_spapr_activate(SpaprInterruptController *intc,
4ffb7496 GK	426	uint32_t nr_servers, Error **errp)
567192d4 DG	427	{
567192d4 DG	428	if (kvm_enabled()) {
4ffb7496	429	return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
567192d4 DG	430	}
	431	return 0;
	432	}
	433
	434	static void xics_spapr_deactivate(SpaprInterruptController *intc)
	435	{
	436	if (kvm_irqchip_in_kernel()) {
	437	xics_kvm_disconnect(intc);
	438	}
	439	}
	440
9db8c551 DG	441	static void ics_spapr_class_init(ObjectClass klass, void data)
	442	{
	443	DeviceClass *dc = DEVICE_CLASS(klass);
	444	ICSStateClass *isc = ICS_CLASS(klass);
ebd6be08	445	SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
9db8c551 DG	446
	447	device_class_set_parent_realize(dc, ics_spapr_realize,
	448	&isc->parent_realize);
567192d4 DG	449	sicc->activate = xics_spapr_activate;
567192d4 DG	450	sicc->deactivate = xics_spapr_deactivate;
ebd6be08	451	sicc->cpu_intc_create = xics_spapr_cpu_intc_create;
d49e8a9b	452	sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;
0990ce6a	453	sicc->cpu_intc_destroy = xics_spapr_cpu_intc_destroy;
0b0e52b1 DG	454	sicc->claim_irq = xics_spapr_claim_irq;
0b0e52b1 DG	455	sicc->free_irq = xics_spapr_free_irq;
7bcdbcca	456	sicc->set_irq = xics_spapr_set_irq;
328d8eb2	457	sicc->print_info = xics_spapr_print_info;
05289273	458	sicc->dt = xics_spapr_dt;
605994e5	459	sicc->post_load = xics_spapr_post_load;
9db8c551 DG	460	}
	461
	462	static const TypeInfo ics_spapr_info = {
	463	.name = TYPE_ICS_SPAPR,
	464	.parent = TYPE_ICS,
	465	.class_init = ics_spapr_class_init,
150e25f8 DG	466	.interfaces = (InterfaceInfo[]) {
	467	{ TYPE_SPAPR_INTC },
	468	{ }
	469	},
9db8c551 DG	470	};
	471
	472	static void xics_spapr_register_types(void)
	473	{
	474	type_register_static(&ics_spapr_info);
	475	}
	476
	477	type_init(xics_spapr_register_types)