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Commit | Line | Data |
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502a5395 | 1 | /* |
3cbee15b | 2 | * QEMU Grackle PCI host (heathrow OldWorld PowerMac) |
502a5395 | 3 | * |
3cbee15b JM |
4 | * Copyright (c) 2006-2007 Fabrice Bellard |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
0d75590d | 26 | #include "qemu/osdep.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci_host.h" |
28 | #include "hw/ppc/mac.h" | |
29 | #include "hw/pci/pci.h" | |
b0318ec1 MCA |
30 | #include "hw/intc/heathrow_pic.h" |
31 | #include "qapi/error.h" | |
b728fbbc | 32 | #include "trace.h" |
ea026b2f | 33 | |
0e655047 AF |
34 | #define GRACKLE_PCI_HOST_BRIDGE(obj) \ |
35 | OBJECT_CHECK(GrackleState, (obj), TYPE_GRACKLE_PCI_HOST_BRIDGE) | |
36 | ||
426f17bb | 37 | typedef struct GrackleState { |
67c332fd | 38 | PCIHostState parent_obj; |
0e655047 | 39 | |
ac43eb2e | 40 | uint32_t ofw_addr; |
b0318ec1 MCA |
41 | HeathrowState *pic; |
42 | qemu_irq irqs[4]; | |
46f3069c BS |
43 | MemoryRegion pci_mmio; |
44 | MemoryRegion pci_hole; | |
a94e5f99 | 45 | MemoryRegion pci_io; |
426f17bb | 46 | } GrackleState; |
502a5395 | 47 | |
d2b59317 PB |
48 | /* Don't know if this matches real hardware, but it agrees with OHW. */ |
49 | static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) | |
502a5395 | 50 | { |
d2b59317 PB |
51 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
52 | } | |
53 | ||
5d4e84c8 | 54 | static void pci_grackle_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 55 | { |
b0318ec1 | 56 | GrackleState *s = opaque; |
5d4e84c8 | 57 | |
b728fbbc | 58 | trace_grackle_set_irq(irq_num, level); |
b0318ec1 | 59 | qemu_set_irq(s->irqs[irq_num], level); |
502a5395 PB |
60 | } |
61 | ||
b0318ec1 MCA |
62 | static void grackle_init_irqs(GrackleState *s) |
63 | { | |
64 | int i; | |
65 | ||
66 | for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { | |
67 | s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i); | |
68 | } | |
69 | } | |
70 | ||
b0318ec1 MCA |
71 | static void grackle_realize(DeviceState *dev, Error **errp) |
72 | { | |
73 | GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev); | |
74 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); | |
75 | ||
1115ff6d DG |
76 | phb->bus = pci_register_root_bus(dev, NULL, |
77 | pci_grackle_set_irq, | |
78 | pci_grackle_map_irq, | |
b0318ec1 MCA |
79 | s, |
80 | &s->pci_mmio, | |
a94e5f99 | 81 | &s->pci_io, |
1115ff6d | 82 | 0, 4, TYPE_PCI_BUS); |
426f17bb | 83 | |
0e655047 | 84 | pci_create_simple(phb->bus, 0, "grackle"); |
b0318ec1 | 85 | grackle_init_irqs(s); |
426f17bb BS |
86 | } |
87 | ||
b0318ec1 | 88 | static void grackle_init(Object *obj) |
426f17bb | 89 | { |
b0318ec1 MCA |
90 | GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj); |
91 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
92 | PCIHostState *phb = PCI_HOST_BRIDGE(obj); | |
426f17bb | 93 | |
b0318ec1 | 94 | memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); |
a94e5f99 MCA |
95 | memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, |
96 | "pci-isa-mmio", 0x00200000); | |
97 | ||
b0318ec1 MCA |
98 | memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio, |
99 | 0x80000000ULL, 0x7e000000ULL); | |
426f17bb | 100 | |
b0318ec1 MCA |
101 | memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, |
102 | DEVICE(obj), "pci-conf-idx", 0x1000); | |
103 | memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, | |
104 | DEVICE(obj), "pci-data-idx", 0x1000); | |
426f17bb | 105 | |
b0318ec1 MCA |
106 | object_property_add_link(obj, "pic", TYPE_HEATHROW, |
107 | (Object **) &s->pic, | |
108 | qdev_prop_allow_set_link_before_realize, | |
109 | 0, NULL); | |
110 | ||
111 | sysbus_init_mmio(sbd, &phb->conf_mem); | |
112 | sysbus_init_mmio(sbd, &phb->data_mem); | |
a773e64a | 113 | sysbus_init_mmio(sbd, &s->pci_hole); |
a94e5f99 | 114 | sysbus_init_mmio(sbd, &s->pci_io); |
426f17bb BS |
115 | } |
116 | ||
b0318ec1 | 117 | static void grackle_pci_realize(PCIDevice *d, Error **errp) |
426f17bb | 118 | { |
502a5395 | 119 | d->config[0x09] = 0x01; |
426f17bb | 120 | } |
502a5395 | 121 | |
40021f08 AL |
122 | static void grackle_pci_class_init(ObjectClass *klass, void *data) |
123 | { | |
39bffca2 | 124 | DeviceClass *dc = DEVICE_CLASS(klass); |
b0318ec1 | 125 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
40021f08 | 126 | |
b0318ec1 | 127 | k->realize = grackle_pci_realize; |
40021f08 AL |
128 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; |
129 | k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106; | |
130 | k->revision = 0x00; | |
131 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
132 | /* |
133 | * PCI-facing part of the host bridge, not usable without the | |
134 | * host-facing part, which can't be device_add'ed, yet. | |
135 | */ | |
e90f2a8c | 136 | dc->user_creatable = false; |
40021f08 AL |
137 | } |
138 | ||
4240abff | 139 | static const TypeInfo grackle_pci_info = { |
39bffca2 AL |
140 | .name = "grackle", |
141 | .parent = TYPE_PCI_DEVICE, | |
142 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 143 | .class_init = grackle_pci_class_init, |
fd3b02c8 EH |
144 | .interfaces = (InterfaceInfo[]) { |
145 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
146 | { }, | |
147 | }, | |
426f17bb | 148 | }; |
6e6b7363 | 149 | |
ac43eb2e MCA |
150 | static char *grackle_ofw_unit_address(const SysBusDevice *dev) |
151 | { | |
152 | GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev); | |
153 | ||
154 | return g_strdup_printf("%x", s->ofw_addr); | |
155 | } | |
156 | ||
157 | static Property grackle_properties[] = { | |
158 | DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1), | |
159 | DEFINE_PROP_END_OF_LIST() | |
160 | }; | |
161 | ||
b0318ec1 | 162 | static void grackle_class_init(ObjectClass *klass, void *data) |
999e12bb | 163 | { |
e1624435 | 164 | DeviceClass *dc = DEVICE_CLASS(klass); |
ac43eb2e | 165 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
999e12bb | 166 | |
b0318ec1 | 167 | dc->realize = grackle_realize; |
ac43eb2e | 168 | dc->props = grackle_properties; |
e1624435 | 169 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
ac43eb2e MCA |
170 | dc->fw_name = "pci"; |
171 | sbc->explicit_ofw_unit_address = grackle_ofw_unit_address; | |
999e12bb AL |
172 | } |
173 | ||
b0318ec1 | 174 | static const TypeInfo grackle_host_info = { |
0e655047 | 175 | .name = TYPE_GRACKLE_PCI_HOST_BRIDGE, |
8558d942 | 176 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 177 | .instance_size = sizeof(GrackleState), |
b0318ec1 MCA |
178 | .instance_init = grackle_init, |
179 | .class_init = grackle_class_init, | |
0ae46996 AF |
180 | }; |
181 | ||
83f7d43a | 182 | static void grackle_register_types(void) |
426f17bb | 183 | { |
39bffca2 | 184 | type_register_static(&grackle_pci_info); |
b0318ec1 | 185 | type_register_static(&grackle_host_info); |
502a5395 | 186 | } |
426f17bb | 187 | |
83f7d43a | 188 | type_init(grackle_register_types) |