[qemu.git] / hw / char / pl011.c

/*
 * Arm PrimeCell PL011 UART
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "sysemu/char.h"

#define TYPE_PL011 "pl011"
#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)

typedef struct PL011State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t readbuff;
    uint32_t flags;
    uint32_t lcr;
    uint32_t rsr;
    uint32_t cr;
    uint32_t dmacr;
    uint32_t int_enabled;
    uint32_t int_level;
    uint32_t read_fifo[16];
    uint32_t ilpr;
    uint32_t ibrd;
    uint32_t fbrd;
    uint32_t ifl;
    int read_pos;
    int read_count;
    int read_trigger;
    CharDriverState *chr;
    qemu_irq irq;
    const unsigned char *id;
} PL011State;

#define PL011_INT_TX 0x20
#define PL011_INT_RX 0x10

#define PL011_FLAG_TXFE 0x80
#define PL011_FLAG_RXFF 0x40
#define PL011_FLAG_TXFF 0x20
#define PL011_FLAG_RXFE 0x10

static const unsigned char pl011_id_arm[8] =
  { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const unsigned char pl011_id_luminary[8] =
  { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl011_update(PL011State *s)
{
    uint32_t flags;

    flags = s->int_level & s->int_enabled;
    qemu_set_irq(s->irq, flags != 0);
}

static uint64_t pl011_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL011State *s = (PL011State *)opaque;
    uint32_t c;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return s->id[(offset - 0xfe0) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* UARTDR */
        s->flags &= ~PL011_FLAG_RXFF;
        c = s->read_fifo[s->read_pos];
        if (s->read_count > 0) {
            s->read_count--;
            if (++s->read_pos == 16)
                s->read_pos = 0;
        }
        if (s->read_count == 0) {
            s->flags |= PL011_FLAG_RXFE;
        }
        if (s->read_count == s->read_trigger - 1)
            s->int_level &= ~ PL011_INT_RX;
        s->rsr = c >> 8;
        pl011_update(s);
        if (s->chr) {
            qemu_chr_accept_input(s->chr);
        }
        return c;
    case 1: /* UARTRSR */
        return s->rsr;
    case 6: /* UARTFR */
        return s->flags;
    case 8: /* UARTILPR */
        return s->ilpr;
    case 9: /* UARTIBRD */
        return s->ibrd;
    case 10: /* UARTFBRD */
        return s->fbrd;
    case 11: /* UARTLCR_H */
        return s->lcr;
    case 12: /* UARTCR */
        return s->cr;
    case 13: /* UARTIFLS */
        return s->ifl;
    case 14: /* UARTIMSC */
        return s->int_enabled;
    case 15: /* UARTRIS */
        return s->int_level;
    case 16: /* UARTMIS */
        return s->int_level & s->int_enabled;
    case 18: /* UARTDMACR */
        return s->dmacr;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl011_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl011_set_read_trigger(PL011State *s)
{
#if 0
    /* The docs say the RX interrupt is triggered when the FIFO exceeds
       the threshold.  However linux only reads the FIFO in response to an
       interrupt.  Triggering the interrupt when the FIFO is non-empty seems
       to make things work.  */
    if (s->lcr & 0x10)
        s->read_trigger = (s->ifl >> 1) & 0x1c;
    else
#endif
        s->read_trigger = 1;
}

static void pl011_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL011State *s = (PL011State *)opaque;
    unsigned char ch;

    switch (offset >> 2) {
    case 0: /* UARTDR */
        /* ??? Check if transmitter is enabled.  */
        ch = value;
        if (s->chr)
            qemu_chr_fe_write(s->chr, &ch, 1);
        s->int_level |= PL011_INT_TX;
        pl011_update(s);
        break;
    case 1: /* UARTRSR/UARTECR */
        s->rsr = 0;
        break;
    case 6: /* UARTFR */
        /* Writes to Flag register are ignored.  */
        break;
    case 8: /* UARTUARTILPR */
        s->ilpr = value;
        break;
    case 9: /* UARTIBRD */
        s->ibrd = value;
        break;
    case 10: /* UARTFBRD */
        s->fbrd = value;
        break;
    case 11: /* UARTLCR_H */
        /* Reset the FIFO state on FIFO enable or disable */
        if ((s->lcr ^ value) & 0x10) {
            s->read_count = 0;
            s->read_pos = 0;
        }
        s->lcr = value;
        pl011_set_read_trigger(s);
        break;
    case 12: /* UARTCR */
        /* ??? Need to implement the enable and loopback bits.  */
        s->cr = value;
        break;
    case 13: /* UARTIFS */
        s->ifl = value;
        pl011_set_read_trigger(s);
        break;
    case 14: /* UARTIMSC */
        s->int_enabled = value;
        pl011_update(s);
        break;
    case 17: /* UARTICR */
        s->int_level &= ~value;
        pl011_update(s);
        break;
    case 18: /* UARTDMACR */
        s->dmacr = value;
        if (value & 3) {
            qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl011_write: Bad offset %x\n", (int)offset);
    }
}

static int pl011_can_receive(void *opaque)
{
    PL011State *s = (PL011State *)opaque;

    if (s->lcr & 0x10)
        return s->read_count < 16;
    else
        return s->read_count < 1;
}

static void pl011_put_fifo(void *opaque, uint32_t value)
{
    PL011State *s = (PL011State *)opaque;
    int slot;

    slot = s->read_pos + s->read_count;
    if (slot >= 16)
        slot -= 16;
    s->read_fifo[slot] = value;
    s->read_count++;
    s->flags &= ~PL011_FLAG_RXFE;
    if (!(s->lcr & 0x10) || s->read_count == 16) {
        s->flags |= PL011_FLAG_RXFF;
    }
    if (s->read_count == s->read_trigger) {
        s->int_level |= PL011_INT_RX;
        pl011_update(s);
    }
}

static void pl011_receive(void *opaque, const uint8_t *buf, int size)
{
    pl011_put_fifo(opaque, *buf);
}

static void pl011_event(void *opaque, int event)
{
    if (event == CHR_EVENT_BREAK)
        pl011_put_fifo(opaque, 0x400);
}

static const MemoryRegionOps pl011_ops = {
    .read = pl011_read,
    .write = pl011_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_pl011 = {
    .name = "pl011",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(readbuff, PL011State),
        VMSTATE_UINT32(flags, PL011State),
        VMSTATE_UINT32(lcr, PL011State),
        VMSTATE_UINT32(rsr, PL011State),
        VMSTATE_UINT32(cr, PL011State),
        VMSTATE_UINT32(dmacr, PL011State),
        VMSTATE_UINT32(int_enabled, PL011State),
        VMSTATE_UINT32(int_level, PL011State),
        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
        VMSTATE_UINT32(ilpr, PL011State),
        VMSTATE_UINT32(ibrd, PL011State),
        VMSTATE_UINT32(fbrd, PL011State),
        VMSTATE_UINT32(ifl, PL011State),
        VMSTATE_INT32(read_pos, PL011State),
        VMSTATE_INT32(read_count, PL011State),
        VMSTATE_INT32(read_trigger, PL011State),
        VMSTATE_END_OF_LIST()
    }
};

static void pl011_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL011State *s = PL011(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);

    s->read_trigger = 1;
    s->ifl = 0x12;
    s->cr = 0x300;
    s->flags = 0x90;

    s->id = pl011_id_arm;
}

static void pl011_realize(DeviceState *dev, Error **errp)
{
    PL011State *s = PL011(dev);

    /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
    s->chr = qemu_char_get_next_serial();

    if (s->chr) {
        qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
                              pl011_event, s);
    }
}

static void pl011_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = pl011_realize;
    dc->vmsd = &vmstate_pl011;
    /* Reason: realize() method uses qemu_char_get_next_serial() */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo pl011_arm_info = {
    .name          = TYPE_PL011,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL011State),
    .instance_init = pl011_init,
    .class_init    = pl011_class_init,
};

static void pl011_luminary_init(Object *obj)
{
    PL011State *s = PL011(obj);

    s->id = pl011_id_luminary;
}

static const TypeInfo pl011_luminary_info = {
    .name          = "pl011_luminary",
    .parent        = TYPE_PL011,
    .instance_init = pl011_luminary_init,
};

static void pl011_register_types(void)
{
    type_register_static(&pl011_arm_info);
    type_register_static(&pl011_luminary_info);
}

type_init(pl011_register_types)
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* Arm PrimeCell PL011 UART
	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
dccfcd0e	11	#include "sysemu/char.h"
cdbdb648	12
71ffe1a0 AF	13	#define TYPE_PL011 "pl011"
	14	#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
	15
ab640bfc	16	typedef struct PL011State {
71ffe1a0 AF	17	SysBusDevice parent_obj;
71ffe1a0 AF	18
48484757	19	MemoryRegion iomem;
cdbdb648 PB	20	uint32_t readbuff;
	21	uint32_t flags;
	22	uint32_t lcr;
ce8f0905	23	uint32_t rsr;
cdbdb648 PB	24	uint32_t cr;
	25	uint32_t dmacr;
	26	uint32_t int_enabled;
	27	uint32_t int_level;
	28	uint32_t read_fifo[16];
	29	uint32_t ilpr;
	30	uint32_t ibrd;
	31	uint32_t fbrd;
	32	uint32_t ifl;
	33	int read_pos;
	34	int read_count;
	35	int read_trigger;
	36	CharDriverState *chr;
d537cf6c	37	qemu_irq irq;
a7d518a6	38	const unsigned char *id;
ab640bfc	39	} PL011State;
cdbdb648 PB	40
	41	#define PL011_INT_TX 0x20
	42	#define PL011_INT_RX 0x10
	43
	44	#define PL011_FLAG_TXFE 0x80
	45	#define PL011_FLAG_RXFF 0x40
	46	#define PL011_FLAG_TXFF 0x20
	47	#define PL011_FLAG_RXFE 0x10
	48
a7d518a6 PB	49	static const unsigned char pl011_id_arm[8] =
	50	{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	51	static const unsigned char pl011_id_luminary[8] =
	52	{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
cdbdb648	53
ab640bfc	54	static void pl011_update(PL011State *s)
cdbdb648 PB	55	{
cdbdb648 PB	56	uint32_t flags;
3b46e624	57
cdbdb648	58	flags = s->int_level & s->int_enabled;
d537cf6c	59	qemu_set_irq(s->irq, flags != 0);
cdbdb648 PB	60	}
cdbdb648 PB	61
a8170e5e	62	static uint64_t pl011_read(void *opaque, hwaddr offset,
48484757	63	unsigned size)
cdbdb648	64	{
ab640bfc	65	PL011State s = (PL011State )opaque;
cdbdb648 PB	66	uint32_t c;
cdbdb648 PB	67
cdbdb648	68	if (offset >= 0xfe0 && offset < 0x1000) {
a7d518a6	69	return s->id[(offset - 0xfe0) >> 2];
cdbdb648 PB	70	}
	71	switch (offset >> 2) {
	72	case 0: /* UARTDR */
	73	s->flags &= ~PL011_FLAG_RXFF;
	74	c = s->read_fifo[s->read_pos];
	75	if (s->read_count > 0) {
	76	s->read_count--;
	77	if (++s->read_pos == 16)
	78	s->read_pos = 0;
	79	}
	80	if (s->read_count == 0) {
	81	s->flags \|= PL011_FLAG_RXFE;
	82	}
	83	if (s->read_count == s->read_trigger - 1)
	84	s->int_level &= ~ PL011_INT_RX;
ce8f0905	85	s->rsr = c >> 8;
cdbdb648	86	pl011_update(s);
0d4abda8 PM	87	if (s->chr) {
	88	qemu_chr_accept_input(s->chr);
	89	}
cdbdb648	90	return c;
ce8f0905 RH	91	case 1: /* UARTRSR */
ce8f0905 RH	92	return s->rsr;
cdbdb648 PB	93	case 6: /* UARTFR */
	94	return s->flags;
	95	case 8: /* UARTILPR */
	96	return s->ilpr;
	97	case 9: /* UARTIBRD */
	98	return s->ibrd;
	99	case 10: /* UARTFBRD */
	100	return s->fbrd;
	101	case 11: /* UARTLCR_H */
	102	return s->lcr;
	103	case 12: /* UARTCR */
	104	return s->cr;
	105	case 13: /* UARTIFLS */
	106	return s->ifl;
	107	case 14: /* UARTIMSC */
	108	return s->int_enabled;
	109	case 15: /* UARTRIS */
	110	return s->int_level;
	111	case 16: /* UARTMIS */
	112	return s->int_level & s->int_enabled;
	113	case 18: /* UARTDMACR */
	114	return s->dmacr;
	115	default:
6d5433e0 PM	116	qemu_log_mask(LOG_GUEST_ERROR,
6d5433e0 PM	117	"pl011_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	118	return 0;
	119	}
	120	}
	121
ab640bfc	122	static void pl011_set_read_trigger(PL011State *s)
cdbdb648 PB	123	{
	124	#if 0
	125	/* The docs say the RX interrupt is triggered when the FIFO exceeds
	126	the threshold. However linux only reads the FIFO in response to an
	127	interrupt. Triggering the interrupt when the FIFO is non-empty seems
	128	to make things work. */
	129	if (s->lcr & 0x10)
	130	s->read_trigger = (s->ifl >> 1) & 0x1c;
	131	else
	132	#endif
	133	s->read_trigger = 1;
	134	}
	135
a8170e5e	136	static void pl011_write(void *opaque, hwaddr offset,
48484757	137	uint64_t value, unsigned size)
cdbdb648	138	{
ab640bfc	139	PL011State s = (PL011State )opaque;
cdbdb648 PB	140	unsigned char ch;
cdbdb648 PB	141
cdbdb648 PB	142	switch (offset >> 2) {
	143	case 0: /* UARTDR */
	144	/* ??? Check if transmitter is enabled. */
	145	ch = value;
	146	if (s->chr)
2cc6e0a1	147	qemu_chr_fe_write(s->chr, &ch, 1);
cdbdb648 PB	148	s->int_level \|= PL011_INT_TX;
	149	pl011_update(s);
	150	break;
ce8f0905 RH	151	case 1: /* UARTRSR/UARTECR */
ce8f0905 RH	152	s->rsr = 0;
cdbdb648	153	break;
9ee6e8bb PB	154	case 6: /* UARTFR */
	155	/* Writes to Flag register are ignored. */
	156	break;
cdbdb648 PB	157	case 8: /* UARTUARTILPR */
	158	s->ilpr = value;
	159	break;
	160	case 9: /* UARTIBRD */
	161	s->ibrd = value;
	162	break;
	163	case 10: /* UARTFBRD */
	164	s->fbrd = value;
	165	break;
	166	case 11: /* UARTLCR_H */
22709e90 RH	167	/* Reset the FIFO state on FIFO enable or disable */
	168	if ((s->lcr ^ value) & 0x10) {
	169	s->read_count = 0;
	170	s->read_pos = 0;
	171	}
cdbdb648 PB	172	s->lcr = value;
	173	pl011_set_read_trigger(s);
	174	break;
	175	case 12: /* UARTCR */
	176	/* ??? Need to implement the enable and loopback bits. */
	177	s->cr = value;
	178	break;
	179	case 13: /* UARTIFS */
	180	s->ifl = value;
	181	pl011_set_read_trigger(s);
	182	break;
	183	case 14: /* UARTIMSC */
	184	s->int_enabled = value;
	185	pl011_update(s);
	186	break;
	187	case 17: /* UARTICR */
	188	s->int_level &= ~value;
	189	pl011_update(s);
	190	break;
	191	case 18: /* UARTDMACR */
	192	s->dmacr = value;
6d5433e0 PM	193	if (value & 3) {
	194	qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");
	195	}
cdbdb648 PB	196	break;
cdbdb648 PB	197	default:
6d5433e0 PM	198	qemu_log_mask(LOG_GUEST_ERROR,
6d5433e0 PM	199	"pl011_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	200	}
	201	}
	202
aa1f17c1	203	static int pl011_can_receive(void *opaque)
cdbdb648	204	{
ab640bfc	205	PL011State s = (PL011State )opaque;
cdbdb648 PB	206
	207	if (s->lcr & 0x10)
	208	return s->read_count < 16;
	209	else
	210	return s->read_count < 1;
	211	}
	212
cc9c9ffc	213	static void pl011_put_fifo(void *opaque, uint32_t value)
cdbdb648	214	{
ab640bfc	215	PL011State s = (PL011State )opaque;
cdbdb648 PB	216	int slot;
	217
	218	slot = s->read_pos + s->read_count;
	219	if (slot >= 16)
	220	slot -= 16;
cc9c9ffc	221	s->read_fifo[slot] = value;
cdbdb648 PB	222	s->read_count++;
cdbdb648 PB	223	s->flags &= ~PL011_FLAG_RXFE;
f72dbf3d	224	if (!(s->lcr & 0x10) \|\| s->read_count == 16) {
cdbdb648 PB	225	s->flags \|= PL011_FLAG_RXFF;
	226	}
	227	if (s->read_count == s->read_trigger) {
	228	s->int_level \|= PL011_INT_RX;
	229	pl011_update(s);
	230	}
	231	}
	232
cc9c9ffc AJ	233	static void pl011_receive(void opaque, const uint8_t buf, int size)
	234	{
	235	pl011_put_fifo(opaque, *buf);
	236	}
	237
cdbdb648 PB	238	static void pl011_event(void *opaque, int event)
cdbdb648 PB	239	{
cc9c9ffc AJ	240	if (event == CHR_EVENT_BREAK)
cc9c9ffc AJ	241	pl011_put_fifo(opaque, 0x400);
cdbdb648 PB	242	}
cdbdb648 PB	243
48484757 AK	244	static const MemoryRegionOps pl011_ops = {
	245	.read = pl011_read,
	246	.write = pl011_write,
	247	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	248	};
cdbdb648 PB	249
02b68757 JQ	250	static const VMStateDescription vmstate_pl011 = {
02b68757 JQ	251	.name = "pl011",
ce8f0905 RH	252	.version_id = 2,
ce8f0905 RH	253	.minimum_version_id = 2,
8f1e884b	254	.fields = (VMStateField[]) {
ab640bfc AF	255	VMSTATE_UINT32(readbuff, PL011State),
	256	VMSTATE_UINT32(flags, PL011State),
	257	VMSTATE_UINT32(lcr, PL011State),
ce8f0905	258	VMSTATE_UINT32(rsr, PL011State),
ab640bfc AF	259	VMSTATE_UINT32(cr, PL011State),
	260	VMSTATE_UINT32(dmacr, PL011State),
	261	VMSTATE_UINT32(int_enabled, PL011State),
	262	VMSTATE_UINT32(int_level, PL011State),
	263	VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
	264	VMSTATE_UINT32(ilpr, PL011State),
	265	VMSTATE_UINT32(ibrd, PL011State),
	266	VMSTATE_UINT32(fbrd, PL011State),
	267	VMSTATE_UINT32(ifl, PL011State),
	268	VMSTATE_INT32(read_pos, PL011State),
	269	VMSTATE_INT32(read_count, PL011State),
	270	VMSTATE_INT32(read_trigger, PL011State),
02b68757 JQ	271	VMSTATE_END_OF_LIST()
	272	}
	273	};
23e39294	274
71ffe1a0	275	static void pl011_init(Object *obj)
cdbdb648	276	{
71ffe1a0 AF	277	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
71ffe1a0 AF	278	PL011State *s = PL011(obj);
cdbdb648	279
300b1fc6	280	memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
71ffe1a0 AF	281	sysbus_init_mmio(sbd, &s->iomem);
71ffe1a0 AF	282	sysbus_init_irq(sbd, &s->irq);
a7d518a6	283
cdbdb648 PB	284	s->read_trigger = 1;
	285	s->ifl = 0x12;
	286	s->cr = 0x300;
	287	s->flags = 0x90;
a7d518a6	288
71ffe1a0	289	s->id = pl011_id_arm;
a7d518a6 PB	290	}
a7d518a6 PB	291
71ffe1a0	292	static void pl011_realize(DeviceState dev, Error *errp)
a7d518a6	293	{
71ffe1a0 AF	294	PL011State *s = PL011(dev);
71ffe1a0 AF	295
d71b22bb	296	/* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
71ffe1a0 AF	297	s->chr = qemu_char_get_next_serial();
	298
	299	if (s->chr) {
	300	qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
	301	pl011_event, s);
	302	}
a7d518a6 PB	303	}
a7d518a6 PB	304
71ffe1a0	305	static void pl011_class_init(ObjectClass oc, void data)
999e12bb	306	{
71ffe1a0	307	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	308
71ffe1a0 AF	309	dc->realize = pl011_realize;
71ffe1a0 AF	310	dc->vmsd = &vmstate_pl011;
9f9bdf43 MA	311	/* Reason: realize() method uses qemu_char_get_next_serial() */
9f9bdf43 MA	312	dc->cannot_instantiate_with_device_add_yet = true;
999e12bb AL	313	}
999e12bb AL	314
8c43a6f0	315	static const TypeInfo pl011_arm_info = {
71ffe1a0	316	.name = TYPE_PL011,
39bffca2	317	.parent = TYPE_SYS_BUS_DEVICE,
ab640bfc	318	.instance_size = sizeof(PL011State),
71ffe1a0 AF	319	.instance_init = pl011_init,
71ffe1a0 AF	320	.class_init = pl011_class_init,
999e12bb AL	321	};
999e12bb AL	322
71ffe1a0	323	static void pl011_luminary_init(Object *obj)
999e12bb	324	{
71ffe1a0	325	PL011State *s = PL011(obj);
999e12bb	326
71ffe1a0	327	s->id = pl011_id_luminary;
999e12bb AL	328	}
999e12bb AL	329
8c43a6f0	330	static const TypeInfo pl011_luminary_info = {
39bffca2	331	.name = "pl011_luminary",
71ffe1a0 AF	332	.parent = TYPE_PL011,
71ffe1a0 AF	333	.instance_init = pl011_luminary_init,
999e12bb AL	334	};
999e12bb AL	335
83f7d43a	336	static void pl011_register_types(void)
a7d518a6	337	{
39bffca2 AL	338	type_register_static(&pl011_arm_info);
39bffca2 AL	339	type_register_static(&pl011_luminary_info);
a7d518a6 PB	340	}
a7d518a6 PB	341
83f7d43a	342	type_init(pl011_register_types)