]> Git Repo - qemu.git/blame - hw/riscv/meson.build
Merge tag 'fixes-pull-request' of gitlab.com:marcandre.lureau/qemu into staging
[qemu.git] / hw / riscv / meson.build
CommitLineData
2c44220d 1riscv_ss = ss.source_set()
feabc71d 2riscv_ss.add(files('boot.c'), fdt)
6e4dd94f 3riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
30a4af16 4riscv_ss.add(files('riscv_hart.c'))
2c44220d
MAL
5riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
6riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
7a261baf 7riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
2c44220d 8riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
2c44220d 9riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
2c44220d 10riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
56f6e31e 11riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
2c44220d
MAL
12
13hw_arch += {'riscv': riscv_ss}
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