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Commit | Line | Data |
---|---|---|
2c44220d | 1 | riscv_ss = ss.source_set() |
feabc71d | 2 | riscv_ss.add(files('boot.c'), fdt) |
6e4dd94f | 3 | riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) |
30a4af16 | 4 | riscv_ss.add(files('riscv_hart.c')) |
2c44220d MAL |
5 | riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) |
6 | riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) | |
7a261baf | 7 | riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) |
2c44220d | 8 | riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) |
2c44220d | 9 | riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) |
2c44220d | 10 | riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) |
56f6e31e | 11 | riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) |
2c44220d MAL |
12 | |
13 | hw_arch += {'riscv': riscv_ss} |