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Remember the state of level-triggered interrupts
[qemu.git] / hw / omap1.c
CommitLineData
c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
b4e3104b 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
c3d2689d
AZ		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
827df9f3
AZ		 8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
c3d2689d
AZ		 10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
87ecb68b
PB		 21#include "hw.h"
22#include "arm-misc.h"
23#include "omap.h"
24#include "sysemu.h"
25#include "qemu-timer.h"
827df9f3 26#include "qemu-char.h"
87ecb68b
PB		 27/* We use pc-style serial ports. */
28#include "pc.h"
c3d2689d 29
827df9f3 30/* Should signal the TCMI/GPMC */
66450b15
AZ		 31uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
32{
02645926
AZ		 33 uint8_t ret;
34
66450b15 35 OMAP_8B_REG(addr);
b854bc19 36 cpu_physical_memory_read(addr, (void *) &ret, 1);
02645926 37 return ret;
66450b15
AZ		 38}
39
40void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
41 uint32_t value)
42{
b854bc19
AZ		 43 uint8_t val8 = value;
44
66450b15 45 OMAP_8B_REG(addr);
b854bc19 46 cpu_physical_memory_write(addr, (void *) &val8, 1);
66450b15
AZ		 47}
48
b30bb3a2 49uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
c3d2689d 50{
b854bc19
AZ		 51 uint16_t ret;
52
c3d2689d 53 OMAP_16B_REG(addr);
b854bc19
AZ		 54 cpu_physical_memory_read(addr, (void *) &ret, 2);
55 return ret;
c3d2689d
AZ		 56}
57
b30bb3a2 58void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 59 uint32_t value)
60{
b854bc19
AZ		 61 uint16_t val16 = value;
62
c3d2689d 63 OMAP_16B_REG(addr);
b854bc19 64 cpu_physical_memory_write(addr, (void *) &val16, 2);
c3d2689d
AZ		 65}
66
b30bb3a2 67uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
c3d2689d 68{
b854bc19
AZ		 69 uint32_t ret;
70
c3d2689d 71 OMAP_32B_REG(addr);
b854bc19
AZ		 72 cpu_physical_memory_read(addr, (void *) &ret, 4);
73 return ret;
c3d2689d
AZ		 74}
75
b30bb3a2 76void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 77 uint32_t value)
78{
79 OMAP_32B_REG(addr);
b854bc19 80 cpu_physical_memory_write(addr, (void *) &value, 4);
c3d2689d
AZ		 81}
82
c3d2689d 83/* Interrupt Handlers */
106627d0 84struct omap_intr_handler_bank_s {
c3d2689d 85 uint32_t irqs;
106627d0 86 uint32_t inputs;
c3d2689d 87 uint32_t mask;
c3d2689d 88 uint32_t fiq;
106627d0 89 uint32_t sens_edge;
827df9f3 90 uint32_t swi;
106627d0 91 unsigned char priority[32];
c3d2689d
AZ		 92};
93
106627d0
AZ		 94struct omap_intr_handler_s {
95 qemu_irq *pins;
96 qemu_irq parent_intr[2];
97 target_phys_addr_t base;
98 unsigned char nbanks;
827df9f3 99 int level_only;
c3d2689d 100
106627d0
AZ		 101 /* state */
102 uint32_t new_agr[2];
103 int sir_intr[2];
827df9f3
AZ		 104 int autoidle;
105 uint32_t mask;
106 struct omap_intr_handler_bank_s bank[];
106627d0 107};
c3d2689d 108
106627d0
AZ		 109static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
110{
111 int i, j, sir_intr, p_intr, p, f;
112 uint32_t level;
113 sir_intr = 0;
114 p_intr = 255;
115
116 /* Find the interrupt line with the highest dynamic priority.
117 * Note: 0 denotes the hightest priority.
118 * If all interrupts have the same priority, the default order is IRQ_N,
119 * IRQ_N-1,...,IRQ_0. */
120 for (j = 0; j < s->nbanks; ++j) {
827df9f3
AZ		 121 level = s->bank[j].irqs & ~s->bank[j].mask &
122 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
106627d0
AZ		 123 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
124 level >>= f) {
827df9f3 125 p = s->bank[j].priority[i];
106627d0
AZ		 126 if (p <= p_intr) {
127 p_intr = p;
128 sir_intr = 32 * j + i;
129 }
130 f = ffs(level >> 1);
131 }
cfa0b71d 132 }
106627d0 133 s->sir_intr[is_fiq] = sir_intr;
c3d2689d
AZ		 134}
135
106627d0 136static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
c3d2689d 137{
106627d0
AZ		 138 int i;
139 uint32_t has_intr = 0;
c3d2689d 140
106627d0 141 for (i = 0; i < s->nbanks; ++i)
827df9f3
AZ		 142 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
143 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
c3d2689d 144
827df9f3 145 if (s->new_agr[is_fiq] & has_intr & s->mask) {
106627d0
AZ		 146 s->new_agr[is_fiq] = 0;
147 omap_inth_sir_update(s, is_fiq);
148 qemu_set_irq(s->parent_intr[is_fiq], 1);
c3d2689d 149 }
c3d2689d
AZ		 150}
151
152#define INT_FALLING_EDGE 0
153#define INT_LOW_LEVEL 1
154
155static void omap_set_intr(void *opaque, int irq, int req)
156{
157 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
158 uint32_t rise;
159
827df9f3 160 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
106627d0
AZ		 161 int n = irq & 31;
162
c3d2689d 163 if (req) {
106627d0
AZ		 164 rise = ~bank->irqs & (1 << n);
165 if (~bank->sens_edge & (1 << n))
827df9f3 166 rise &= ~bank->inputs;
106627d0
AZ		 167
168 bank->inputs |= (1 << n);
169 if (rise) {
170 bank->irqs |= rise;
171 omap_inth_update(ih, 0);
172 omap_inth_update(ih, 1);
173 }
c3d2689d 174 } else {
106627d0
AZ		 175 rise = bank->sens_edge & bank->irqs & (1 << n);
176 bank->irqs &= ~rise;
177 bank->inputs &= ~(1 << n);
c3d2689d
AZ		 178 }
179}
180
827df9f3
AZ		 181/* Simplified version with no edge detection */
182static void omap_set_intr_noedge(void *opaque, int irq, int req)
183{
184 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
185 uint32_t rise;
186
187 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
188 int n = irq & 31;
189
190 if (req) {
191 rise = ~bank->inputs & (1 << n);
192 if (rise) {
193 bank->irqs |= bank->inputs |= rise;
194 omap_inth_update(ih, 0);
195 omap_inth_update(ih, 1);
196 }
197 } else
198 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
199}
200
c3d2689d
AZ		 201static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
202{
203 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
204 int i, offset = addr - s->base;
106627d0
AZ		 205 int bank_no = offset >> 8;
206 int line_no;
827df9f3 207 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
106627d0 208 offset &= 0xff;
c3d2689d
AZ		 209
210 switch (offset) {
211 case 0x00: /* ITR */
106627d0 212 return bank->irqs;
c3d2689d
AZ		 213
214 case 0x04: /* MIR */
106627d0 215 return bank->mask;
c3d2689d
AZ		 216
217 case 0x10: /* SIR_IRQ_CODE */
106627d0
AZ		 218 case 0x14: /* SIR_FIQ_CODE */
219 if (bank_no != 0)
220 break;
221 line_no = s->sir_intr[(offset - 0x10) >> 2];
827df9f3 222 bank = &s->bank[line_no >> 5];
106627d0
AZ		 223 i = line_no & 31;
224 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
225 bank->irqs &= ~(1 << i);
f2df5260 226 return line_no;
c3d2689d
AZ		 227
228 case 0x18: /* CONTROL_REG */
106627d0
AZ		 229 if (bank_no != 0)
230 break;
c3d2689d
AZ		 231 return 0;
232
233 case 0x1c: /* ILR0 */
234 case 0x20: /* ILR1 */
235 case 0x24: /* ILR2 */
236 case 0x28: /* ILR3 */
237 case 0x2c: /* ILR4 */
238 case 0x30: /* ILR5 */
239 case 0x34: /* ILR6 */
240 case 0x38: /* ILR7 */
241 case 0x3c: /* ILR8 */
242 case 0x40: /* ILR9 */
243 case 0x44: /* ILR10 */
244 case 0x48: /* ILR11 */
245 case 0x4c: /* ILR12 */
246 case 0x50: /* ILR13 */
247 case 0x54: /* ILR14 */
248 case 0x58: /* ILR15 */
249 case 0x5c: /* ILR16 */
250 case 0x60: /* ILR17 */
251 case 0x64: /* ILR18 */
252 case 0x68: /* ILR19 */
253 case 0x6c: /* ILR20 */
254 case 0x70: /* ILR21 */
255 case 0x74: /* ILR22 */
256 case 0x78: /* ILR23 */
257 case 0x7c: /* ILR24 */
258 case 0x80: /* ILR25 */
259 case 0x84: /* ILR26 */
260 case 0x88: /* ILR27 */
261 case 0x8c: /* ILR28 */
262 case 0x90: /* ILR29 */
263 case 0x94: /* ILR30 */
264 case 0x98: /* ILR31 */
265 i = (offset - 0x1c) >> 2;
106627d0
AZ		 266 return (bank->priority[i] << 2) |
267 (((bank->sens_edge >> i) & 1) << 1) |
268 ((bank->fiq >> i) & 1);
c3d2689d
AZ		 269
270 case 0x9c: /* ISR */
271 return 0x00000000;
272
c3d2689d 273 }
106627d0 274 OMAP_BAD_REG(addr);
c3d2689d
AZ		 275 return 0;
276}
277
278static void omap_inth_write(void *opaque, target_phys_addr_t addr,
279 uint32_t value)
280{
281 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
282 int i, offset = addr - s->base;
106627d0 283 int bank_no = offset >> 8;
827df9f3 284 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
106627d0 285 offset &= 0xff;
c3d2689d
AZ		 286
287 switch (offset) {
288 case 0x00: /* ITR */
106627d0
AZ		 289 /* Important: ignore the clearing if the IRQ is level-triggered and
290 the input bit is 1 */
291 bank->irqs &= value | (bank->inputs & bank->sens_edge);
c3d2689d
AZ		 292 return;
293
294 case 0x04: /* MIR */
106627d0
AZ		 295 bank->mask = value;
296 omap_inth_update(s, 0);
297 omap_inth_update(s, 1);
c3d2689d
AZ		 298 return;
299
300 case 0x10: /* SIR_IRQ_CODE */
301 case 0x14: /* SIR_FIQ_CODE */
302 OMAP_RO_REG(addr);
303 break;
304
305 case 0x18: /* CONTROL_REG */
106627d0
AZ		 306 if (bank_no != 0)
307 break;
308 if (value & 2) {
309 qemu_set_irq(s->parent_intr[1], 0);
310 s->new_agr[1] = ~0;
311 omap_inth_update(s, 1);
312 }
313 if (value & 1) {
314 qemu_set_irq(s->parent_intr[0], 0);
315 s->new_agr[0] = ~0;
316 omap_inth_update(s, 0);
317 }
c3d2689d
AZ		 318 return;
319
320 case 0x1c: /* ILR0 */
321 case 0x20: /* ILR1 */
322 case 0x24: /* ILR2 */
323 case 0x28: /* ILR3 */
324 case 0x2c: /* ILR4 */
325 case 0x30: /* ILR5 */
326 case 0x34: /* ILR6 */
327 case 0x38: /* ILR7 */
328 case 0x3c: /* ILR8 */
329 case 0x40: /* ILR9 */
330 case 0x44: /* ILR10 */
331 case 0x48: /* ILR11 */
332 case 0x4c: /* ILR12 */
333 case 0x50: /* ILR13 */
334 case 0x54: /* ILR14 */
335 case 0x58: /* ILR15 */
336 case 0x5c: /* ILR16 */
337 case 0x60: /* ILR17 */
338 case 0x64: /* ILR18 */
339 case 0x68: /* ILR19 */
340 case 0x6c: /* ILR20 */
341 case 0x70: /* ILR21 */
342 case 0x74: /* ILR22 */
343 case 0x78: /* ILR23 */
344 case 0x7c: /* ILR24 */
345 case 0x80: /* ILR25 */
346 case 0x84: /* ILR26 */
347 case 0x88: /* ILR27 */
348 case 0x8c: /* ILR28 */
349 case 0x90: /* ILR29 */
350 case 0x94: /* ILR30 */
351 case 0x98: /* ILR31 */
352 i = (offset - 0x1c) >> 2;
106627d0
AZ		 353 bank->priority[i] = (value >> 2) & 0x1f;
354 bank->sens_edge &= ~(1 << i);
355 bank->sens_edge |= ((value >> 1) & 1) << i;
356 bank->fiq &= ~(1 << i);
357 bank->fiq |= (value & 1) << i;
c3d2689d
AZ		 358 return;
359
360 case 0x9c: /* ISR */
361 for (i = 0; i < 32; i ++)
362 if (value & (1 << i)) {
106627d0 363 omap_set_intr(s, 32 * bank_no + i, 1);
c3d2689d
AZ		 364 return;
365 }
366 return;
c3d2689d 367 }
106627d0 368 OMAP_BAD_REG(addr);
c3d2689d
AZ		 369}
370
371static CPUReadMemoryFunc *omap_inth_readfn[] = {
372 omap_badwidth_read32,
373 omap_badwidth_read32,
374 omap_inth_read,
375};
376
377static CPUWriteMemoryFunc *omap_inth_writefn[] = {
378 omap_inth_write,
379 omap_inth_write,
380 omap_inth_write,
381};
382
106627d0 383void omap_inth_reset(struct omap_intr_handler_s *s)
c3d2689d 384{
106627d0
AZ		 385 int i;
386
387 for (i = 0; i < s->nbanks; ++i){
827df9f3
AZ		 388 s->bank[i].irqs = 0x00000000;
389 s->bank[i].mask = 0xffffffff;
390 s->bank[i].sens_edge = 0x00000000;
391 s->bank[i].fiq = 0x00000000;
392 s->bank[i].inputs = 0x00000000;
393 s->bank[i].swi = 0x00000000;
394 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
395
396 if (s->level_only)
397 s->bank[i].sens_edge = 0xffffffff;
106627d0 398 }
c3d2689d 399
106627d0
AZ		 400 s->new_agr[0] = ~0;
401 s->new_agr[1] = ~0;
402 s->sir_intr[0] = 0;
403 s->sir_intr[1] = 0;
827df9f3
AZ		 404 s->autoidle = 0;
405 s->mask = ~0;
106627d0
AZ		 406
407 qemu_set_irq(s->parent_intr[0], 0);
408 qemu_set_irq(s->parent_intr[1], 0);
c3d2689d
AZ		 409}
410
411struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
827df9f3 412 unsigned long size, unsigned char nbanks, qemu_irq **pins,
106627d0 413 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
c3d2689d
AZ		 414{
415 int iomemtype;
416 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
106627d0
AZ		 417 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
418 sizeof(struct omap_intr_handler_bank_s) * nbanks);
c3d2689d 419
106627d0
AZ		 420 s->parent_intr[0] = parent_irq;
421 s->parent_intr[1] = parent_fiq;
c3d2689d 422 s->base = base;
106627d0
AZ		 423 s->nbanks = nbanks;
424 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
827df9f3
AZ		 425 if (pins)
426 *pins = s->pins;
106627d0 427
c3d2689d
AZ		 428 omap_inth_reset(s);
429
430 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
431 omap_inth_writefn, s);
432 cpu_register_physical_memory(s->base, size, iomemtype);
433
434 return s;
435}
436
827df9f3
AZ		 437static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
438{
439 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
440 int offset = addr - s->base;
441 int bank_no, line_no;
442 struct omap_intr_handler_bank_s *bank = 0;
443
444 if ((offset & 0xf80) == 0x80) {
445 bank_no = (offset & 0x60) >> 5;
446 if (bank_no < s->nbanks) {
447 offset &= ~0x60;
448 bank = &s->bank[bank_no];
449 }
450 }
451
452 switch (offset) {
453 case 0x00: /* INTC_REVISION */
454 return 0x21;
455
456 case 0x10: /* INTC_SYSCONFIG */
457 return (s->autoidle >> 2) & 1;
458
459 case 0x14: /* INTC_SYSSTATUS */
460 return 1; /* RESETDONE */
461
462 case 0x40: /* INTC_SIR_IRQ */
463 return s->sir_intr[0];
464
465 case 0x44: /* INTC_SIR_FIQ */
466 return s->sir_intr[1];
467
468 case 0x48: /* INTC_CONTROL */
469 return (!s->mask) << 2; /* GLOBALMASK */
470
471 case 0x4c: /* INTC_PROTECTION */
472 return 0;
473
474 case 0x50: /* INTC_IDLE */
475 return s->autoidle & 3;
476
477 /* Per-bank registers */
478 case 0x80: /* INTC_ITR */
479 return bank->inputs;
480
481 case 0x84: /* INTC_MIR */
482 return bank->mask;
483
484 case 0x88: /* INTC_MIR_CLEAR */
485 case 0x8c: /* INTC_MIR_SET */
486 return 0;
487
488 case 0x90: /* INTC_ISR_SET */
489 return bank->swi;
490
491 case 0x94: /* INTC_ISR_CLEAR */
492 return 0;
493
494 case 0x98: /* INTC_PENDING_IRQ */
495 return bank->irqs & ~bank->mask & ~bank->fiq;
496
497 case 0x9c: /* INTC_PENDING_FIQ */
498 return bank->irqs & ~bank->mask & bank->fiq;
499
500 /* Per-line registers */
501 case 0x100 ... 0x300: /* INTC_ILR */
502 bank_no = (offset - 0x100) >> 7;
503 if (bank_no > s->nbanks)
504 break;
505 bank = &s->bank[bank_no];
506 line_no = (offset & 0x7f) >> 2;
507 return (bank->priority[line_no] << 2) |
508 ((bank->fiq >> line_no) & 1);
509 }
510 OMAP_BAD_REG(addr);
511 return 0;
512}
513
514static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
515 uint32_t value)
516{
517 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
518 int offset = addr - s->base;
519 int bank_no, line_no;
520 struct omap_intr_handler_bank_s *bank = 0;
521
522 if ((offset & 0xf80) == 0x80) {
523 bank_no = (offset & 0x60) >> 5;
524 if (bank_no < s->nbanks) {
525 offset &= ~0x60;
526 bank = &s->bank[bank_no];
527 }
528 }
529
530 switch (offset) {
531 case 0x10: /* INTC_SYSCONFIG */
532 s->autoidle &= 4;
533 s->autoidle |= (value & 1) << 2;
534 if (value & 2) /* SOFTRESET */
535 omap_inth_reset(s);
536 return;
537
538 case 0x48: /* INTC_CONTROL */
539 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
540 if (value & 2) { /* NEWFIQAGR */
541 qemu_set_irq(s->parent_intr[1], 0);
542 s->new_agr[1] = ~0;
543 omap_inth_update(s, 1);
544 }
545 if (value & 1) { /* NEWIRQAGR */
546 qemu_set_irq(s->parent_intr[0], 0);
547 s->new_agr[0] = ~0;
548 omap_inth_update(s, 0);
549 }
550 return;
551
552 case 0x4c: /* INTC_PROTECTION */
553 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
554 * for every register, see Chapter 3 and 4 for privileged mode. */
555 if (value & 1)
556 fprintf(stderr, "%s: protection mode enable attempt\n",
557 __FUNCTION__);
558 return;
559
560 case 0x50: /* INTC_IDLE */
561 s->autoidle &= ~3;
562 s->autoidle |= value & 3;
563 return;
564
565 /* Per-bank registers */
566 case 0x84: /* INTC_MIR */
567 bank->mask = value;
568 omap_inth_update(s, 0);
569 omap_inth_update(s, 1);
570 return;
571
572 case 0x88: /* INTC_MIR_CLEAR */
573 bank->mask &= ~value;
574 omap_inth_update(s, 0);
575 omap_inth_update(s, 1);
576 return;
577
578 case 0x8c: /* INTC_MIR_SET */
579 bank->mask |= value;
580 return;
581
582 case 0x90: /* INTC_ISR_SET */
583 bank->irqs |= bank->swi |= value;
584 omap_inth_update(s, 0);
585 omap_inth_update(s, 1);
586 return;
587
588 case 0x94: /* INTC_ISR_CLEAR */
589 bank->swi &= ~value;
590 bank->irqs = bank->swi & bank->inputs;
591 return;
592
593 /* Per-line registers */
594 case 0x100 ... 0x300: /* INTC_ILR */
595 bank_no = (offset - 0x100) >> 7;
596 if (bank_no > s->nbanks)
597 break;
598 bank = &s->bank[bank_no];
599 line_no = (offset & 0x7f) >> 2;
600 bank->priority[line_no] = (value >> 2) & 0x3f;
601 bank->fiq &= ~(1 << line_no);
602 bank->fiq |= (value & 1) << line_no;
603 return;
604
605 case 0x00: /* INTC_REVISION */
606 case 0x14: /* INTC_SYSSTATUS */
607 case 0x40: /* INTC_SIR_IRQ */
608 case 0x44: /* INTC_SIR_FIQ */
609 case 0x80: /* INTC_ITR */
610 case 0x98: /* INTC_PENDING_IRQ */
611 case 0x9c: /* INTC_PENDING_FIQ */
612 OMAP_RO_REG(addr);
613 return;
614 }
615 OMAP_BAD_REG(addr);
616}
617
618static CPUReadMemoryFunc *omap2_inth_readfn[] = {
619 omap_badwidth_read32,
620 omap_badwidth_read32,
621 omap2_inth_read,
622};
623
624static CPUWriteMemoryFunc *omap2_inth_writefn[] = {
625 omap2_inth_write,
626 omap2_inth_write,
627 omap2_inth_write,
628};
629
630struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
631 int size, int nbanks, qemu_irq **pins,
632 qemu_irq parent_irq, qemu_irq parent_fiq,
633 omap_clk fclk, omap_clk iclk)
634{
635 int iomemtype;
636 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
637 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
638 sizeof(struct omap_intr_handler_bank_s) * nbanks);
639
640 s->parent_intr[0] = parent_irq;
641 s->parent_intr[1] = parent_fiq;
642 s->base = base;
643 s->nbanks = nbanks;
644 s->level_only = 1;
645 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
646 if (pins)
647 *pins = s->pins;
648
649 omap_inth_reset(s);
650
651 iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
652 omap2_inth_writefn, s);
653 cpu_register_physical_memory(s->base, size, iomemtype);
654
655 return s;
656}
657
c3d2689d
AZ		 658/* MPU OS timers */
659struct omap_mpu_timer_s {
660 qemu_irq irq;
661 omap_clk clk;
662 target_phys_addr_t base;
663 uint32_t val;
664 int64_t time;
665 QEMUTimer *timer;
666 int64_t rate;
667 int it_ena;
668
669 int enable;
670 int ptv;
671 int ar;
672 int st;
673 uint32_t reset_val;
674};
675
676static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
677{
678 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
679
680 if (timer->st && timer->enable && timer->rate)
681 return timer->val - muldiv64(distance >> (timer->ptv + 1),
682 timer->rate, ticks_per_sec);
683 else
684 return timer->val;
685}
686
687static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
688{
689 timer->val = omap_timer_read(timer);
690 timer->time = qemu_get_clock(vm_clock);
691}
692
693static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
694{
695 int64_t expires;
696
697 if (timer->enable && timer->st && timer->rate) {
698 timer->val = timer->reset_val; /* Should skip this on clk enable */
b854bc19 699 expires = muldiv64(timer->val << (timer->ptv + 1),
c3d2689d 700 ticks_per_sec, timer->rate);
b854bc19
AZ		 701
702 /* If timer expiry would be sooner than in about 1 ms and
703 * auto-reload isn't set, then fire immediately. This is a hack
704 * to make systems like PalmOS run in acceptable time. PalmOS
705 * sets the interval to a very low value and polls the status bit
706 * in a busy loop when it wants to sleep just a couple of CPU
707 * ticks. */
708 if (expires > (ticks_per_sec >> 10) || timer->ar)
709 qemu_mod_timer(timer->timer, timer->time + expires);
710 else {
711 timer->val = 0;
712 timer->st = 0;
713 if (timer->it_ena)
106627d0
AZ		 714 /* Edge-triggered irq */
715 qemu_irq_pulse(timer->irq);
b854bc19 716 }
c3d2689d
AZ		 717 } else
718 qemu_del_timer(timer->timer);
719}
720
721static void omap_timer_tick(void *opaque)
722{
723 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
724 omap_timer_sync(timer);
725
726 if (!timer->ar) {
727 timer->val = 0;
728 timer->st = 0;
729 }
730
731 if (timer->it_ena)
106627d0
AZ		 732 /* Edge-triggered irq */
733 qemu_irq_pulse(timer->irq);
c3d2689d
AZ		 734 omap_timer_update(timer);
735}
736
737static void omap_timer_clk_update(void *opaque, int line, int on)
738{
739 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
740
741 omap_timer_sync(timer);
742 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
743 omap_timer_update(timer);
744}
745
746static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
747{
748 omap_clk_adduser(timer->clk,
749 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
750 timer->rate = omap_clk_getrate(timer->clk);
751}
752
753static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
754{
755 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
756 int offset = addr - s->base;
757
758 switch (offset) {
759 case 0x00: /* CNTL_TIMER */
760 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
761
762 case 0x04: /* LOAD_TIM */
763 break;
764
765 case 0x08: /* READ_TIM */
766 return omap_timer_read(s);
767 }
768
769 OMAP_BAD_REG(addr);
770 return 0;
771}
772
773static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
774 uint32_t value)
775{
776 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
777 int offset = addr - s->base;
778
779 switch (offset) {
780 case 0x00: /* CNTL_TIMER */
781 omap_timer_sync(s);
782 s->enable = (value >> 5) & 1;
783 s->ptv = (value >> 2) & 7;
784 s->ar = (value >> 1) & 1;
785 s->st = value & 1;
786 omap_timer_update(s);
787 return;
788
789 case 0x04: /* LOAD_TIM */
790 s->reset_val = value;
791 return;
792
793 case 0x08: /* READ_TIM */
794 OMAP_RO_REG(addr);
795 break;
796
797 default:
798 OMAP_BAD_REG(addr);
799 }
800}
801
802static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
803 omap_badwidth_read32,
804 omap_badwidth_read32,
805 omap_mpu_timer_read,
806};
807
808static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
809 omap_badwidth_write32,
810 omap_badwidth_write32,
811 omap_mpu_timer_write,
812};
813
814static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
815{
816 qemu_del_timer(s->timer);
817 s->enable = 0;
818 s->reset_val = 31337;
819 s->val = 0;
820 s->ptv = 0;
821 s->ar = 0;
822 s->st = 0;
823 s->it_ena = 1;
824}
825
826struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
827 qemu_irq irq, omap_clk clk)
828{
829 int iomemtype;
830 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
831 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
832
833 s->irq = irq;
834 s->clk = clk;
835 s->base = base;
836 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
837 omap_mpu_timer_reset(s);
838 omap_timer_clk_setup(s);
839
840 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
841 omap_mpu_timer_writefn, s);
842 cpu_register_physical_memory(s->base, 0x100, iomemtype);
843
844 return s;
845}
846
847/* Watchdog timer */
848struct omap_watchdog_timer_s {
849 struct omap_mpu_timer_s timer;
850 uint8_t last_wr;
851 int mode;
852 int free;
853 int reset;
854};
855
856static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
857{
858 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
859 int offset = addr - s->timer.base;
860
861 switch (offset) {
862 case 0x00: /* CNTL_TIMER */
863 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
864 (s->timer.st << 7) | (s->free << 1);
865
866 case 0x04: /* READ_TIMER */
867 return omap_timer_read(&s->timer);
868
869 case 0x08: /* TIMER_MODE */
870 return s->mode << 15;
871 }
872
873 OMAP_BAD_REG(addr);
874 return 0;
875}
876
877static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
878 uint32_t value)
879{
880 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
881 int offset = addr - s->timer.base;
882
883 switch (offset) {
884 case 0x00: /* CNTL_TIMER */
885 omap_timer_sync(&s->timer);
886 s->timer.ptv = (value >> 9) & 7;
887 s->timer.ar = (value >> 8) & 1;
888 s->timer.st = (value >> 7) & 1;
889 s->free = (value >> 1) & 1;
890 omap_timer_update(&s->timer);
891 break;
892
893 case 0x04: /* LOAD_TIMER */
894 s->timer.reset_val = value & 0xffff;
895 break;
896
897 case 0x08: /* TIMER_MODE */
898 if (!s->mode && ((value >> 15) & 1))
899 omap_clk_get(s->timer.clk);
900 s->mode |= (value >> 15) & 1;
901 if (s->last_wr == 0xf5) {
902 if ((value & 0xff) == 0xa0) {
d8f699cb
AZ		 903 if (s->mode) {
904 s->mode = 0;
905 omap_clk_put(s->timer.clk);
906 }
c3d2689d
AZ		 907 } else {
908 /* XXX: on T|E hardware somehow this has no effect,
909 * on Zire 71 it works as specified. */
910 s->reset = 1;
911 qemu_system_reset_request();
912 }
913 }
914 s->last_wr = value & 0xff;
915 break;
916
917 default:
918 OMAP_BAD_REG(addr);
919 }
920}
921
922static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
923 omap_badwidth_read16,
924 omap_wd_timer_read,
925 omap_badwidth_read16,
926};
927
928static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
929 omap_badwidth_write16,
930 omap_wd_timer_write,
931 omap_badwidth_write16,
932};
933
934static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
935{
936 qemu_del_timer(s->timer.timer);
937 if (!s->mode)
938 omap_clk_get(s->timer.clk);
939 s->mode = 1;
940 s->free = 1;
941 s->reset = 0;
942 s->timer.enable = 1;
943 s->timer.it_ena = 1;
944 s->timer.reset_val = 0xffff;
945 s->timer.val = 0;
946 s->timer.st = 0;
947 s->timer.ptv = 0;
948 s->timer.ar = 0;
949 omap_timer_update(&s->timer);
950}
951
952struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
953 qemu_irq irq, omap_clk clk)
954{
955 int iomemtype;
956 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
957 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
958
959 s->timer.irq = irq;
960 s->timer.clk = clk;
961 s->timer.base = base;
962 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
963 omap_wd_timer_reset(s);
964 omap_timer_clk_setup(&s->timer);
965
966 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
967 omap_wd_timer_writefn, s);
968 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
969
970 return s;
971}
972
973/* 32-kHz timer */
974struct omap_32khz_timer_s {
975 struct omap_mpu_timer_s timer;
976};
977
978static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
979{
980 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 981 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d
AZ		 982
983 switch (offset) {
984 case 0x00: /* TVR */
985 return s->timer.reset_val;
986
987 case 0x04: /* TCR */
988 return omap_timer_read(&s->timer);
989
990 case 0x08: /* CR */
991 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
992
993 default:
994 break;
995 }
996 OMAP_BAD_REG(addr);
997 return 0;
998}
999
1000static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1001 uint32_t value)
1002{
1003 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 1004 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d
AZ		 1005
1006 switch (offset) {
1007 case 0x00: /* TVR */
1008 s->timer.reset_val = value & 0x00ffffff;
1009 break;
1010
1011 case 0x04: /* TCR */
1012 OMAP_RO_REG(addr);
1013 break;
1014
1015 case 0x08: /* CR */
1016 s->timer.ar = (value >> 3) & 1;
1017 s->timer.it_ena = (value >> 2) & 1;
1018 if (s->timer.st != (value & 1) || (value & 2)) {
1019 omap_timer_sync(&s->timer);
1020 s->timer.enable = value & 1;
1021 s->timer.st = value & 1;
1022 omap_timer_update(&s->timer);
1023 }
1024 break;
1025
1026 default:
1027 OMAP_BAD_REG(addr);
1028 }
1029}
1030
1031static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
1032 omap_badwidth_read32,
1033 omap_badwidth_read32,
1034 omap_os_timer_read,
1035};
1036
1037static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
1038 omap_badwidth_write32,
1039 omap_badwidth_write32,
1040 omap_os_timer_write,
1041};
1042
1043static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1044{
1045 qemu_del_timer(s->timer.timer);
1046 s->timer.enable = 0;
1047 s->timer.it_ena = 0;
1048 s->timer.reset_val = 0x00ffffff;
1049 s->timer.val = 0;
1050 s->timer.st = 0;
1051 s->timer.ptv = 0;
1052 s->timer.ar = 1;
1053}
1054
1055struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
1056 qemu_irq irq, omap_clk clk)
1057{
1058 int iomemtype;
1059 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1060 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1061
1062 s->timer.irq = irq;
1063 s->timer.clk = clk;
1064 s->timer.base = base;
1065 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1066 omap_os_timer_reset(s);
1067 omap_timer_clk_setup(&s->timer);
1068
1069 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
1070 omap_os_timer_writefn, s);
1071 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
1072
1073 return s;
1074}
1075
1076/* Ultra Low-Power Device Module */
1077static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
1078{
1079 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1080 int offset = addr - s->ulpd_pm_base;
1081 uint16_t ret;
1082
1083 switch (offset) {
1084 case 0x14: /* IT_STATUS */
1085 ret = s->ulpd_pm_regs[offset >> 2];
1086 s->ulpd_pm_regs[offset >> 2] = 0;
1087 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1088 return ret;
1089
1090 case 0x18: /* Reserved */
1091 case 0x1c: /* Reserved */
1092 case 0x20: /* Reserved */
1093 case 0x28: /* Reserved */
1094 case 0x2c: /* Reserved */
1095 OMAP_BAD_REG(addr);
1096 case 0x00: /* COUNTER_32_LSB */
1097 case 0x04: /* COUNTER_32_MSB */
1098 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1099 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1100 case 0x10: /* GAUGING_CTRL */
1101 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1102 case 0x30: /* CLOCK_CTRL */
1103 case 0x34: /* SOFT_REQ */
1104 case 0x38: /* COUNTER_32_FIQ */
1105 case 0x3c: /* DPLL_CTRL */
1106 case 0x40: /* STATUS_REQ */
1107 /* XXX: check clk::usecount state for every clock */
1108 case 0x48: /* LOCL_TIME */
1109 case 0x4c: /* APLL_CTRL */
1110 case 0x50: /* POWER_CTRL */
1111 return s->ulpd_pm_regs[offset >> 2];
1112 }
1113
1114 OMAP_BAD_REG(addr);
1115 return 0;
1116}
1117
1118static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1119 uint16_t diff, uint16_t value)
1120{
1121 if (diff & (1 << 4)) /* USB_MCLK_EN */
1122 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1123 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1124 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1125}
1126
1127static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1128 uint16_t diff, uint16_t value)
1129{
1130 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1131 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1132 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1133 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1134 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1135 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1136 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1137 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1138}
1139
1140static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
1141 uint32_t value)
1142{
1143 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1144 int offset = addr - s->ulpd_pm_base;
1145 int64_t now, ticks;
1146 int div, mult;
1147 static const int bypass_div[4] = { 1, 2, 4, 4 };
1148 uint16_t diff;
1149
1150 switch (offset) {
1151 case 0x00: /* COUNTER_32_LSB */
1152 case 0x04: /* COUNTER_32_MSB */
1153 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1154 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1155 case 0x14: /* IT_STATUS */
1156 case 0x40: /* STATUS_REQ */
1157 OMAP_RO_REG(addr);
1158 break;
1159
1160 case 0x10: /* GAUGING_CTRL */
1161 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1162 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
1163 now = qemu_get_clock(vm_clock);
1164
1165 if (value & 1)
1166 s->ulpd_gauge_start = now;
1167 else {
1168 now -= s->ulpd_gauge_start;
1169
1170 /* 32-kHz ticks */
1171 ticks = muldiv64(now, 32768, ticks_per_sec);
1172 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1173 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1174 if (ticks >> 32) /* OVERFLOW_32K */
1175 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1176
1177 /* High frequency ticks */
1178 ticks = muldiv64(now, 12000000, ticks_per_sec);
1179 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1180 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1181 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1182 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1183
1184 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1185 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1186 }
1187 }
1188 s->ulpd_pm_regs[offset >> 2] = value;
1189 break;
1190
1191 case 0x18: /* Reserved */
1192 case 0x1c: /* Reserved */
1193 case 0x20: /* Reserved */
1194 case 0x28: /* Reserved */
1195 case 0x2c: /* Reserved */
1196 OMAP_BAD_REG(addr);
1197 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1198 case 0x38: /* COUNTER_32_FIQ */
1199 case 0x48: /* LOCL_TIME */
1200 case 0x50: /* POWER_CTRL */
1201 s->ulpd_pm_regs[offset >> 2] = value;
1202 break;
1203
1204 case 0x30: /* CLOCK_CTRL */
1205 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1206 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
1207 omap_ulpd_clk_update(s, diff, value);
1208 break;
1209
1210 case 0x34: /* SOFT_REQ */
1211 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1212 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
1213 omap_ulpd_req_update(s, diff, value);
1214 break;
1215
1216 case 0x3c: /* DPLL_CTRL */
1217 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1218 * omitted altogether, probably a typo. */
1219 /* This register has identical semantics with DPLL(1:3) control
1220 * registers, see omap_dpll_write() */
1221 diff = s->ulpd_pm_regs[offset >> 2] & value;
1222 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
1223 if (diff & (0x3ff << 2)) {
1224 if (value & (1 << 4)) { /* PLL_ENABLE */
1225 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1226 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1227 } else {
1228 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1229 mult = 1;
1230 }
1231 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1232 }
1233
1234 /* Enter the desired mode. */
1235 s->ulpd_pm_regs[offset >> 2] =
1236 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
1237 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
1238
1239 /* Act as if the lock is restored. */
1240 s->ulpd_pm_regs[offset >> 2] |= 2;
1241 break;
1242
1243 case 0x4c: /* APLL_CTRL */
1244 diff = s->ulpd_pm_regs[offset >> 2] & value;
1245 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
1246 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1247 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1248 (value & (1 << 0)) ? "apll" : "dpll4"));
1249 break;
1250
1251 default:
1252 OMAP_BAD_REG(addr);
1253 }
1254}
1255
1256static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
1257 omap_badwidth_read16,
1258 omap_ulpd_pm_read,
1259 omap_badwidth_read16,
1260};
1261
1262static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
1263 omap_badwidth_write16,
1264 omap_ulpd_pm_write,
1265 omap_badwidth_write16,
1266};
1267
1268static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1269{
1270 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1271 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1272 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1273 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1274 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1275 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1276 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1277 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1278 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1279 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1280 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1281 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1282 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1283 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1284 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1285 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1286 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1287 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1288 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1289 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1290 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1291 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1292 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1293}
1294
1295static void omap_ulpd_pm_init(target_phys_addr_t base,
1296 struct omap_mpu_state_s *mpu)
1297{
1298 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
1299 omap_ulpd_pm_writefn, mpu);
1300
1301 mpu->ulpd_pm_base = base;
1302 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
1303 omap_ulpd_pm_reset(mpu);
1304}
1305
1306/* OMAP Pin Configuration */
1307static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
1308{
1309 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1310 int offset = addr - s->pin_cfg_base;
1311
1312 switch (offset) {
1313 case 0x00: /* FUNC_MUX_CTRL_0 */
1314 case 0x04: /* FUNC_MUX_CTRL_1 */
1315 case 0x08: /* FUNC_MUX_CTRL_2 */
1316 return s->func_mux_ctrl[offset >> 2];
1317
1318 case 0x0c: /* COMP_MODE_CTRL_0 */
1319 return s->comp_mode_ctrl[0];
1320
1321 case 0x10: /* FUNC_MUX_CTRL_3 */
1322 case 0x14: /* FUNC_MUX_CTRL_4 */
1323 case 0x18: /* FUNC_MUX_CTRL_5 */
1324 case 0x1c: /* FUNC_MUX_CTRL_6 */
1325 case 0x20: /* FUNC_MUX_CTRL_7 */
1326 case 0x24: /* FUNC_MUX_CTRL_8 */
1327 case 0x28: /* FUNC_MUX_CTRL_9 */
1328 case 0x2c: /* FUNC_MUX_CTRL_A */
1329 case 0x30: /* FUNC_MUX_CTRL_B */
1330 case 0x34: /* FUNC_MUX_CTRL_C */
1331 case 0x38: /* FUNC_MUX_CTRL_D */
1332 return s->func_mux_ctrl[(offset >> 2) - 1];
1333
1334 case 0x40: /* PULL_DWN_CTRL_0 */
1335 case 0x44: /* PULL_DWN_CTRL_1 */
1336 case 0x48: /* PULL_DWN_CTRL_2 */
1337 case 0x4c: /* PULL_DWN_CTRL_3 */
1338 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
1339
1340 case 0x50: /* GATE_INH_CTRL_0 */
1341 return s->gate_inh_ctrl[0];
1342
1343 case 0x60: /* VOLTAGE_CTRL_0 */
1344 return s->voltage_ctrl[0];
1345
1346 case 0x70: /* TEST_DBG_CTRL_0 */
1347 return s->test_dbg_ctrl[0];
1348
1349 case 0x80: /* MOD_CONF_CTRL_0 */
1350 return s->mod_conf_ctrl[0];
1351 }
1352
1353 OMAP_BAD_REG(addr);
1354 return 0;
1355}
1356
1357static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1358 uint32_t diff, uint32_t value)
1359{
1360 if (s->compat1509) {
1361 if (diff & (1 << 9)) /* BLUETOOTH */
1362 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1363 (~value >> 9) & 1);
1364 if (diff & (1 << 7)) /* USB.CLKO */
1365 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1366 (value >> 7) & 1);
1367 }
1368}
1369
1370static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1371 uint32_t diff, uint32_t value)
1372{
1373 if (s->compat1509) {
1374 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1375 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1376 (value >> 31) & 1);
1377 if (diff & (1 << 1)) /* CLK32K */
1378 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1379 (~value >> 1) & 1);
1380 }
1381}
1382
1383static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1384 uint32_t diff, uint32_t value)
1385{
1386 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1387 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1388 omap_findclk(s, ((value >> 31) & 1) ?
1389 "ck_48m" : "armper_ck"));
1390 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1391 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1392 omap_findclk(s, ((value >> 30) & 1) ?
1393 "ck_48m" : "armper_ck"));
1394 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1395 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1396 omap_findclk(s, ((value >> 29) & 1) ?
1397 "ck_48m" : "armper_ck"));
1398 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1399 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1400 omap_findclk(s, ((value >> 23) & 1) ?
1401 "ck_48m" : "armper_ck"));
1402 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1403 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1404 omap_findclk(s, ((value >> 12) & 1) ?
1405 "ck_48m" : "armper_ck"));
1406 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1407 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1408}
1409
1410static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
1411 uint32_t value)
1412{
1413 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1414 int offset = addr - s->pin_cfg_base;
1415 uint32_t diff;
1416
1417 switch (offset) {
1418 case 0x00: /* FUNC_MUX_CTRL_0 */
1419 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1420 s->func_mux_ctrl[offset >> 2] = value;
1421 omap_pin_funcmux0_update(s, diff, value);
1422 return;
1423
1424 case 0x04: /* FUNC_MUX_CTRL_1 */
1425 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1426 s->func_mux_ctrl[offset >> 2] = value;
1427 omap_pin_funcmux1_update(s, diff, value);
1428 return;
1429
1430 case 0x08: /* FUNC_MUX_CTRL_2 */
1431 s->func_mux_ctrl[offset >> 2] = value;
1432 return;
1433
1434 case 0x0c: /* COMP_MODE_CTRL_0 */
1435 s->comp_mode_ctrl[0] = value;
1436 s->compat1509 = (value != 0x0000eaef);
1437 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1438 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1439 return;
1440
1441 case 0x10: /* FUNC_MUX_CTRL_3 */
1442 case 0x14: /* FUNC_MUX_CTRL_4 */
1443 case 0x18: /* FUNC_MUX_CTRL_5 */
1444 case 0x1c: /* FUNC_MUX_CTRL_6 */
1445 case 0x20: /* FUNC_MUX_CTRL_7 */
1446 case 0x24: /* FUNC_MUX_CTRL_8 */
1447 case 0x28: /* FUNC_MUX_CTRL_9 */
1448 case 0x2c: /* FUNC_MUX_CTRL_A */
1449 case 0x30: /* FUNC_MUX_CTRL_B */
1450 case 0x34: /* FUNC_MUX_CTRL_C */
1451 case 0x38: /* FUNC_MUX_CTRL_D */
1452 s->func_mux_ctrl[(offset >> 2) - 1] = value;
1453 return;
1454
1455 case 0x40: /* PULL_DWN_CTRL_0 */
1456 case 0x44: /* PULL_DWN_CTRL_1 */
1457 case 0x48: /* PULL_DWN_CTRL_2 */
1458 case 0x4c: /* PULL_DWN_CTRL_3 */
1459 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
1460 return;
1461
1462 case 0x50: /* GATE_INH_CTRL_0 */
1463 s->gate_inh_ctrl[0] = value;
1464 return;
1465
1466 case 0x60: /* VOLTAGE_CTRL_0 */
1467 s->voltage_ctrl[0] = value;
1468 return;
1469
1470 case 0x70: /* TEST_DBG_CTRL_0 */
1471 s->test_dbg_ctrl[0] = value;
1472 return;
1473
1474 case 0x80: /* MOD_CONF_CTRL_0 */
1475 diff = s->mod_conf_ctrl[0] ^ value;
1476 s->mod_conf_ctrl[0] = value;
1477 omap_pin_modconf1_update(s, diff, value);
1478 return;
1479
1480 default:
1481 OMAP_BAD_REG(addr);
1482 }
1483}
1484
1485static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
1486 omap_badwidth_read32,
1487 omap_badwidth_read32,
1488 omap_pin_cfg_read,
1489};
1490
1491static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
1492 omap_badwidth_write32,
1493 omap_badwidth_write32,
1494 omap_pin_cfg_write,
1495};
1496
1497static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1498{
1499 /* Start in Compatibility Mode. */
1500 mpu->compat1509 = 1;
1501 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1502 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1503 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1504 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1505 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1506 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1507 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1508 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1509 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1510 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1511}
1512
1513static void omap_pin_cfg_init(target_phys_addr_t base,
1514 struct omap_mpu_state_s *mpu)
1515{
1516 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
1517 omap_pin_cfg_writefn, mpu);
1518
1519 mpu->pin_cfg_base = base;
1520 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
1521 omap_pin_cfg_reset(mpu);
1522}
1523
1524/* Device Identification, Die Identification */
1525static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1526{
1527 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1528
1529 switch (addr) {
1530 case 0xfffe1800: /* DIE_ID_LSB */
1531 return 0xc9581f0e;
1532 case 0xfffe1804: /* DIE_ID_MSB */
1533 return 0xa8858bfa;
1534
1535 case 0xfffe2000: /* PRODUCT_ID_LSB */
1536 return 0x00aaaafc;
1537 case 0xfffe2004: /* PRODUCT_ID_MSB */
1538 return 0xcafeb574;
1539
1540 case 0xfffed400: /* JTAG_ID_LSB */
1541 switch (s->mpu_model) {
1542 case omap310:
1543 return 0x03310315;
1544 case omap1510:
1545 return 0x03310115;
827df9f3
AZ		 1546 default:
1547 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1548 }
1549 break;
1550
1551 case 0xfffed404: /* JTAG_ID_MSB */
1552 switch (s->mpu_model) {
1553 case omap310:
1554 return 0xfb57402f;
1555 case omap1510:
1556 return 0xfb47002f;
827df9f3
AZ		 1557 default:
1558 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1559 }
1560 break;
1561 }
1562
1563 OMAP_BAD_REG(addr);
1564 return 0;
1565}
1566
1567static void omap_id_write(void *opaque, target_phys_addr_t addr,
1568 uint32_t value)
1569{
1570 OMAP_BAD_REG(addr);
1571}
1572
1573static CPUReadMemoryFunc *omap_id_readfn[] = {
1574 omap_badwidth_read32,
1575 omap_badwidth_read32,
1576 omap_id_read,
1577};
1578
1579static CPUWriteMemoryFunc *omap_id_writefn[] = {
1580 omap_badwidth_write32,
1581 omap_badwidth_write32,
1582 omap_id_write,
1583};
1584
1585static void omap_id_init(struct omap_mpu_state_s *mpu)
1586{
1587 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
1588 omap_id_writefn, mpu);
1589 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
1590 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
1591 if (!cpu_is_omap15xx(mpu))
1592 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
1593}
1594
1595/* MPUI Control (Dummy) */
1596static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
1597{
1598 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1599 int offset = addr - s->mpui_base;
1600
1601 switch (offset) {
1602 case 0x00: /* CTRL */
1603 return s->mpui_ctrl;
1604 case 0x04: /* DEBUG_ADDR */
1605 return 0x01ffffff;
1606 case 0x08: /* DEBUG_DATA */
1607 return 0xffffffff;
1608 case 0x0c: /* DEBUG_FLAG */
1609 return 0x00000800;
1610 case 0x10: /* STATUS */
1611 return 0x00000000;
1612
1613 /* Not in OMAP310 */
1614 case 0x14: /* DSP_STATUS */
1615 case 0x18: /* DSP_BOOT_CONFIG */
1616 return 0x00000000;
1617 case 0x1c: /* DSP_MPUI_CONFIG */
1618 return 0x0000ffff;
1619 }
1620
1621 OMAP_BAD_REG(addr);
1622 return 0;
1623}
1624
1625static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
1626 uint32_t value)
1627{
1628 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1629 int offset = addr - s->mpui_base;
1630
1631 switch (offset) {
1632 case 0x00: /* CTRL */
1633 s->mpui_ctrl = value & 0x007fffff;
1634 break;
1635
1636 case 0x04: /* DEBUG_ADDR */
1637 case 0x08: /* DEBUG_DATA */
1638 case 0x0c: /* DEBUG_FLAG */
1639 case 0x10: /* STATUS */
1640 /* Not in OMAP310 */
1641 case 0x14: /* DSP_STATUS */
1642 OMAP_RO_REG(addr);
1643 case 0x18: /* DSP_BOOT_CONFIG */
1644 case 0x1c: /* DSP_MPUI_CONFIG */
1645 break;
1646
1647 default:
1648 OMAP_BAD_REG(addr);
1649 }
1650}
1651
1652static CPUReadMemoryFunc *omap_mpui_readfn[] = {
1653 omap_badwidth_read32,
1654 omap_badwidth_read32,
1655 omap_mpui_read,
1656};
1657
1658static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
1659 omap_badwidth_write32,
1660 omap_badwidth_write32,
1661 omap_mpui_write,
1662};
1663
1664static void omap_mpui_reset(struct omap_mpu_state_s *s)
1665{
1666 s->mpui_ctrl = 0x0003ff1b;
1667}
1668
1669static void omap_mpui_init(target_phys_addr_t base,
1670 struct omap_mpu_state_s *mpu)
1671{
1672 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
1673 omap_mpui_writefn, mpu);
1674
1675 mpu->mpui_base = base;
1676 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
1677
1678 omap_mpui_reset(mpu);
1679}
1680
1681/* TIPB Bridges */
1682struct omap_tipb_bridge_s {
1683 target_phys_addr_t base;
1684 qemu_irq abort;
1685
1686 int width_intr;
1687 uint16_t control;
1688 uint16_t alloc;
1689 uint16_t buffer;
1690 uint16_t enh_control;
1691};
1692
1693static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
1694{
1695 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1696 int offset = addr - s->base;
1697
1698 switch (offset) {
1699 case 0x00: /* TIPB_CNTL */
1700 return s->control;
1701 case 0x04: /* TIPB_BUS_ALLOC */
1702 return s->alloc;
1703 case 0x08: /* MPU_TIPB_CNTL */
1704 return s->buffer;
1705 case 0x0c: /* ENHANCED_TIPB_CNTL */
1706 return s->enh_control;
1707 case 0x10: /* ADDRESS_DBG */
1708 case 0x14: /* DATA_DEBUG_LOW */
1709 case 0x18: /* DATA_DEBUG_HIGH */
1710 return 0xffff;
1711 case 0x1c: /* DEBUG_CNTR_SIG */
1712 return 0x00f8;
1713 }
1714
1715 OMAP_BAD_REG(addr);
1716 return 0;
1717}
1718
1719static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
1720 uint32_t value)
1721{
1722 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1723 int offset = addr - s->base;
1724
1725 switch (offset) {
1726 case 0x00: /* TIPB_CNTL */
1727 s->control = value & 0xffff;
1728 break;
1729
1730 case 0x04: /* TIPB_BUS_ALLOC */
1731 s->alloc = value & 0x003f;
1732 break;
1733
1734 case 0x08: /* MPU_TIPB_CNTL */
1735 s->buffer = value & 0x0003;
1736 break;
1737
1738 case 0x0c: /* ENHANCED_TIPB_CNTL */
1739 s->width_intr = !(value & 2);
1740 s->enh_control = value & 0x000f;
1741 break;
1742
1743 case 0x10: /* ADDRESS_DBG */
1744 case 0x14: /* DATA_DEBUG_LOW */
1745 case 0x18: /* DATA_DEBUG_HIGH */
1746 case 0x1c: /* DEBUG_CNTR_SIG */
1747 OMAP_RO_REG(addr);
1748 break;
1749
1750 default:
1751 OMAP_BAD_REG(addr);
1752 }
1753}
1754
1755static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
1756 omap_badwidth_read16,
1757 omap_tipb_bridge_read,
1758 omap_tipb_bridge_read,
1759};
1760
1761static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
1762 omap_badwidth_write16,
1763 omap_tipb_bridge_write,
1764 omap_tipb_bridge_write,
1765};
1766
1767static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1768{
1769 s->control = 0xffff;
1770 s->alloc = 0x0009;
1771 s->buffer = 0x0000;
1772 s->enh_control = 0x000f;
1773}
1774
1775struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
1776 qemu_irq abort_irq, omap_clk clk)
1777{
1778 int iomemtype;
1779 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1780 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1781
1782 s->abort = abort_irq;
1783 s->base = base;
1784 omap_tipb_bridge_reset(s);
1785
1786 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
1787 omap_tipb_bridge_writefn, s);
1788 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1789
1790 return s;
1791}
1792
1793/* Dummy Traffic Controller's Memory Interface */
1794static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
1795{
1796 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1797 int offset = addr - s->tcmi_base;
1798 uint32_t ret;
1799
1800 switch (offset) {
d8f699cb
AZ		 1801 case 0x00: /* IMIF_PRIO */
1802 case 0x04: /* EMIFS_PRIO */
1803 case 0x08: /* EMIFF_PRIO */
1804 case 0x0c: /* EMIFS_CONFIG */
1805 case 0x10: /* EMIFS_CS0_CONFIG */
1806 case 0x14: /* EMIFS_CS1_CONFIG */
1807 case 0x18: /* EMIFS_CS2_CONFIG */
1808 case 0x1c: /* EMIFS_CS3_CONFIG */
1809 case 0x24: /* EMIFF_MRS */
1810 case 0x28: /* TIMEOUT1 */
1811 case 0x2c: /* TIMEOUT2 */
1812 case 0x30: /* TIMEOUT3 */
1813 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1814 case 0x40: /* EMIFS_CFG_DYN_WAIT */
c3d2689d
AZ		 1815 return s->tcmi_regs[offset >> 2];
1816
d8f699cb 1817 case 0x20: /* EMIFF_SDRAM_CONFIG */
c3d2689d
AZ		 1818 ret = s->tcmi_regs[offset >> 2];
1819 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1820 /* XXX: We can try using the VGA_DIRTY flag for this */
1821 return ret;
1822 }
1823
1824 OMAP_BAD_REG(addr);
1825 return 0;
1826}
1827
1828static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
1829 uint32_t value)
1830{
1831 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1832 int offset = addr - s->tcmi_base;
1833
1834 switch (offset) {
d8f699cb
AZ		 1835 case 0x00: /* IMIF_PRIO */
1836 case 0x04: /* EMIFS_PRIO */
1837 case 0x08: /* EMIFF_PRIO */
1838 case 0x10: /* EMIFS_CS0_CONFIG */
1839 case 0x14: /* EMIFS_CS1_CONFIG */
1840 case 0x18: /* EMIFS_CS2_CONFIG */
1841 case 0x1c: /* EMIFS_CS3_CONFIG */
1842 case 0x20: /* EMIFF_SDRAM_CONFIG */
1843 case 0x24: /* EMIFF_MRS */
1844 case 0x28: /* TIMEOUT1 */
1845 case 0x2c: /* TIMEOUT2 */
1846 case 0x30: /* TIMEOUT3 */
1847 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1848 case 0x40: /* EMIFS_CFG_DYN_WAIT */
c3d2689d
AZ		 1849 s->tcmi_regs[offset >> 2] = value;
1850 break;
d8f699cb 1851 case 0x0c: /* EMIFS_CONFIG */
c3d2689d
AZ		 1852 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
1853 break;
1854
1855 default:
1856 OMAP_BAD_REG(addr);
1857 }
1858}
1859
1860static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
1861 omap_badwidth_read32,
1862 omap_badwidth_read32,
1863 omap_tcmi_read,
1864};
1865
1866static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
1867 omap_badwidth_write32,
1868 omap_badwidth_write32,
1869 omap_tcmi_write,
1870};
1871
1872static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1873{
1874 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1875 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1876 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1877 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1878 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1879 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1880 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1881 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1882 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1883 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1884 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1885 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1886 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1887 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1888 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1889}
1890
1891static void omap_tcmi_init(target_phys_addr_t base,
1892 struct omap_mpu_state_s *mpu)
1893{
1894 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
1895 omap_tcmi_writefn, mpu);
1896
1897 mpu->tcmi_base = base;
1898 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
1899 omap_tcmi_reset(mpu);
1900}
1901
1902/* Digital phase-locked loops control */
1903static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
1904{
1905 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1906 int offset = addr - s->base;
1907
1908 if (offset == 0x00) /* CTL_REG */
1909 return s->mode;
1910
1911 OMAP_BAD_REG(addr);
1912 return 0;
1913}
1914
1915static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
1916 uint32_t value)
1917{
1918 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1919 uint16_t diff;
1920 int offset = addr - s->base;
1921 static const int bypass_div[4] = { 1, 2, 4, 4 };
1922 int div, mult;
1923
1924 if (offset == 0x00) { /* CTL_REG */
1925 /* See omap_ulpd_pm_write() too */
1926 diff = s->mode & value;
1927 s->mode = value & 0x2fff;
1928 if (diff & (0x3ff << 2)) {
1929 if (value & (1 << 4)) { /* PLL_ENABLE */
1930 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1931 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1932 } else {
1933 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1934 mult = 1;
1935 }
1936 omap_clk_setrate(s->dpll, div, mult);
1937 }
1938
1939 /* Enter the desired mode. */
1940 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1941
1942 /* Act as if the lock is restored. */
1943 s->mode |= 2;
1944 } else {
1945 OMAP_BAD_REG(addr);
1946 }
1947}
1948
1949static CPUReadMemoryFunc *omap_dpll_readfn[] = {
1950 omap_badwidth_read16,
1951 omap_dpll_read,
1952 omap_badwidth_read16,
1953};
1954
1955static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
1956 omap_badwidth_write16,
1957 omap_dpll_write,
1958 omap_badwidth_write16,
1959};
1960
1961static void omap_dpll_reset(struct dpll_ctl_s *s)
1962{
1963 s->mode = 0x2002;
1964 omap_clk_setrate(s->dpll, 1, 1);
1965}
1966
1967static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
1968 omap_clk clk)
1969{
1970 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
1971 omap_dpll_writefn, s);
1972
1973 s->base = base;
1974 s->dpll = clk;
1975 omap_dpll_reset(s);
1976
1977 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1978}
1979
1980/* UARTs */
1981struct omap_uart_s {
1982 SerialState *serial; /* TODO */
827df9f3
AZ		 1983 struct omap_target_agent_s *ta;
1984 target_phys_addr_t base;
1985
1986 uint8_t eblr;
1987 uint8_t syscontrol;
1988 uint8_t wkup;
1989 uint8_t cfps;
c3d2689d
AZ		 1990};
1991
827df9f3 1992void omap_uart_reset(struct omap_uart_s *s)
c3d2689d 1993{
827df9f3
AZ		 1994 s->eblr = 0x00;
1995 s->syscontrol = 0;
1996 s->wkup = 0x3f;
1997 s->cfps = 0x69;
c3d2689d
AZ		 1998}
1999
2000struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
827df9f3
AZ		 2001 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2002 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
c3d2689d
AZ		 2003{
2004 struct omap_uart_s *s = (struct omap_uart_s *)
2005 qemu_mallocz(sizeof(struct omap_uart_s));
827df9f3
AZ		 2006
2007 s->serial = serial_mm_init(base, 2, irq, chr ?: qemu_chr_open("null"), 1);
2008
2009 return s;
2010}
2011
2012static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
2013{
2014 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2015 int offset = addr - s->base;
2016
2017 switch (offset) {
2018 case 0x48: /* EBLR */
2019 return s->eblr;
2020 case 0x50: /* MVR */
2021 return 0x30;
2022 case 0x54: /* SYSC */
2023 return s->syscontrol;
2024 case 0x58: /* SYSS */
2025 return 1;
2026 case 0x5c: /* WER */
2027 return s->wkup;
2028 case 0x60: /* CFPS */
2029 return s->cfps;
2030 }
2031
2032 OMAP_BAD_REG(addr);
2033 return 0;
2034}
2035
2036static void omap_uart_write(void *opaque, target_phys_addr_t addr,
2037 uint32_t value)
2038{
2039 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2040 int offset = addr - s->base;
2041
2042 switch (offset) {
2043 case 0x48: /* EBLR */
2044 s->eblr = value & 0xff;
2045 break;
2046 case 0x50: /* MVR */
2047 case 0x58: /* SYSS */
2048 OMAP_RO_REG(addr);
2049 break;
2050 case 0x54: /* SYSC */
2051 s->syscontrol = value & 0x1d;
2052 if (value & 2)
2053 omap_uart_reset(s);
2054 break;
2055 case 0x5c: /* WER */
2056 s->wkup = value & 0x7f;
2057 break;
2058 case 0x60: /* CFPS */
2059 s->cfps = value & 0xff;
2060 break;
2061 default:
2062 OMAP_BAD_REG(addr);
2063 }
2064}
2065
2066static CPUReadMemoryFunc *omap_uart_readfn[] = {
2067 omap_uart_read,
2068 omap_uart_read,
2069 omap_badwidth_read8,
2070};
2071
2072static CPUWriteMemoryFunc *omap_uart_writefn[] = {
2073 omap_uart_write,
2074 omap_uart_write,
2075 omap_badwidth_write8,
2076};
2077
2078struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
2079 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2080 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2081{
2082 target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
2083 struct omap_uart_s *s = omap_uart_init(base, irq,
2084 fclk, iclk, txdma, rxdma, chr);
2085 int iomemtype = cpu_register_io_memory(0, omap_uart_readfn,
2086 omap_uart_writefn, s);
2087
2088 s->ta = ta;
2089 s->base = base;
2090
2091 cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
2092
c3d2689d
AZ		 2093 return s;
2094}
2095
2096/* MPU Clock/Reset/Power Mode Control */
2097static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2098{
2099 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2100 int offset = addr - s->clkm.mpu_base;
2101
2102 switch (offset) {
2103 case 0x00: /* ARM_CKCTL */
2104 return s->clkm.arm_ckctl;
2105
2106 case 0x04: /* ARM_IDLECT1 */
2107 return s->clkm.arm_idlect1;
2108
2109 case 0x08: /* ARM_IDLECT2 */
2110 return s->clkm.arm_idlect2;
2111
2112 case 0x0c: /* ARM_EWUPCT */
2113 return s->clkm.arm_ewupct;
2114
2115 case 0x10: /* ARM_RSTCT1 */
2116 return s->clkm.arm_rstct1;
2117
2118 case 0x14: /* ARM_RSTCT2 */
2119 return s->clkm.arm_rstct2;
2120
2121 case 0x18: /* ARM_SYSST */
d8f699cb 2122 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
c3d2689d
AZ		 2123
2124 case 0x1c: /* ARM_CKOUT1 */
2125 return s->clkm.arm_ckout1;
2126
2127 case 0x20: /* ARM_CKOUT2 */
2128 break;
2129 }
2130
2131 OMAP_BAD_REG(addr);
2132 return 0;
2133}
2134
2135static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2136 uint16_t diff, uint16_t value)
2137{
2138 omap_clk clk;
2139
2140 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2141 if (value & (1 << 14))
2142 /* Reserved */;
2143 else {
2144 clk = omap_findclk(s, "arminth_ck");
2145 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2146 }
2147 }
2148 if (diff & (1 << 12)) { /* ARM_TIMXO */
2149 clk = omap_findclk(s, "armtim_ck");
2150 if (value & (1 << 12))
2151 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2152 else
2153 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2154 }
2155 /* XXX: en_dspck */
2156 if (diff & (3 << 10)) { /* DSPMMUDIV */
2157 clk = omap_findclk(s, "dspmmu_ck");
2158 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2159 }
2160 if (diff & (3 << 8)) { /* TCDIV */
2161 clk = omap_findclk(s, "tc_ck");
2162 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2163 }
2164 if (diff & (3 << 6)) { /* DSPDIV */
2165 clk = omap_findclk(s, "dsp_ck");
2166 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2167 }
2168 if (diff & (3 << 4)) { /* ARMDIV */
2169 clk = omap_findclk(s, "arm_ck");
2170 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2171 }
2172 if (diff & (3 << 2)) { /* LCDDIV */
2173 clk = omap_findclk(s, "lcd_ck");
2174 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2175 }
2176 if (diff & (3 << 0)) { /* PERDIV */
2177 clk = omap_findclk(s, "armper_ck");
2178 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2179 }
2180}
2181
2182static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2183 uint16_t diff, uint16_t value)
2184{
2185 omap_clk clk;
2186
2187 if (value & (1 << 11)) /* SETARM_IDLE */
2188 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2189 if (!(value & (1 << 10))) /* WKUP_MODE */
2190 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2191
2192#define SET_CANIDLE(clock, bit) \
2193 if (diff & (1 << bit)) { \
2194 clk = omap_findclk(s, clock); \
2195 omap_clk_canidle(clk, (value >> bit) & 1); \
2196 }
2197 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2198 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2199 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2200 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2201 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2202 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2203 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2204 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2205 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2206 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2207 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2208 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2209 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2210 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2211}
2212
2213static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2214 uint16_t diff, uint16_t value)
2215{
2216 omap_clk clk;
2217
2218#define SET_ONOFF(clock, bit) \
2219 if (diff & (1 << bit)) { \
2220 clk = omap_findclk(s, clock); \
2221 omap_clk_onoff(clk, (value >> bit) & 1); \
2222 }
2223 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2224 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2225 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2226 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2227 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2228 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2229 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2230 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2231 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2232 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2233 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2234}
2235
2236static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2237 uint16_t diff, uint16_t value)
2238{
2239 omap_clk clk;
2240
2241 if (diff & (3 << 4)) { /* TCLKOUT */
2242 clk = omap_findclk(s, "tclk_out");
2243 switch ((value >> 4) & 3) {
2244 case 1:
2245 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2246 omap_clk_onoff(clk, 1);
2247 break;
2248 case 2:
2249 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2250 omap_clk_onoff(clk, 1);
2251 break;
2252 default:
2253 omap_clk_onoff(clk, 0);
2254 }
2255 }
2256 if (diff & (3 << 2)) { /* DCLKOUT */
2257 clk = omap_findclk(s, "dclk_out");
2258 switch ((value >> 2) & 3) {
2259 case 0:
2260 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2261 break;
2262 case 1:
2263 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2264 break;
2265 case 2:
2266 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2267 break;
2268 case 3:
2269 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2270 break;
2271 }
2272 }
2273 if (diff & (3 << 0)) { /* ACLKOUT */
2274 clk = omap_findclk(s, "aclk_out");
2275 switch ((value >> 0) & 3) {
2276 case 1:
2277 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2278 omap_clk_onoff(clk, 1);
2279 break;
2280 case 2:
2281 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2282 omap_clk_onoff(clk, 1);
2283 break;
2284 case 3:
2285 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2286 omap_clk_onoff(clk, 1);
2287 break;
2288 default:
2289 omap_clk_onoff(clk, 0);
2290 }
2291 }
2292}
2293
2294static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
2295 uint32_t value)
2296{
2297 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2298 int offset = addr - s->clkm.mpu_base;
2299 uint16_t diff;
2300 omap_clk clk;
2301 static const char *clkschemename[8] = {
2302 "fully synchronous", "fully asynchronous", "synchronous scalable",
2303 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2304 };
2305
2306 switch (offset) {
2307 case 0x00: /* ARM_CKCTL */
2308 diff = s->clkm.arm_ckctl ^ value;
2309 s->clkm.arm_ckctl = value & 0x7fff;
2310 omap_clkm_ckctl_update(s, diff, value);
2311 return;
2312
2313 case 0x04: /* ARM_IDLECT1 */
2314 diff = s->clkm.arm_idlect1 ^ value;
2315 s->clkm.arm_idlect1 = value & 0x0fff;
2316 omap_clkm_idlect1_update(s, diff, value);
2317 return;
2318
2319 case 0x08: /* ARM_IDLECT2 */
2320 diff = s->clkm.arm_idlect2 ^ value;
2321 s->clkm.arm_idlect2 = value & 0x07ff;
2322 omap_clkm_idlect2_update(s, diff, value);
2323 return;
2324
2325 case 0x0c: /* ARM_EWUPCT */
2326 diff = s->clkm.arm_ewupct ^ value;
2327 s->clkm.arm_ewupct = value & 0x003f;
2328 return;
2329
2330 case 0x10: /* ARM_RSTCT1 */
2331 diff = s->clkm.arm_rstct1 ^ value;
2332 s->clkm.arm_rstct1 = value & 0x0007;
2333 if (value & 9) {
2334 qemu_system_reset_request();
2335 s->clkm.cold_start = 0xa;
2336 }
2337 if (diff & ~value & 4) { /* DSP_RST */
2338 omap_mpui_reset(s);
2339 omap_tipb_bridge_reset(s->private_tipb);
2340 omap_tipb_bridge_reset(s->public_tipb);
2341 }
2342 if (diff & 2) { /* DSP_EN */
2343 clk = omap_findclk(s, "dsp_ck");
2344 omap_clk_canidle(clk, (~value >> 1) & 1);
2345 }
2346 return;
2347
2348 case 0x14: /* ARM_RSTCT2 */
2349 s->clkm.arm_rstct2 = value & 0x0001;
2350 return;
2351
2352 case 0x18: /* ARM_SYSST */
2353 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2354 s->clkm.clocking_scheme = (value >> 11) & 7;
2355 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2356 clkschemename[s->clkm.clocking_scheme]);
2357 }
2358 s->clkm.cold_start &= value & 0x3f;
2359 return;
2360
2361 case 0x1c: /* ARM_CKOUT1 */
2362 diff = s->clkm.arm_ckout1 ^ value;
2363 s->clkm.arm_ckout1 = value & 0x003f;
2364 omap_clkm_ckout1_update(s, diff, value);
2365 return;
2366
2367 case 0x20: /* ARM_CKOUT2 */
2368 default:
2369 OMAP_BAD_REG(addr);
2370 }
2371}
2372
2373static CPUReadMemoryFunc *omap_clkm_readfn[] = {
2374 omap_badwidth_read16,
2375 omap_clkm_read,
2376 omap_badwidth_read16,
2377};
2378
2379static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
2380 omap_badwidth_write16,
2381 omap_clkm_write,
2382 omap_badwidth_write16,
2383};
2384
2385static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
2386{
2387 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2388 int offset = addr - s->clkm.dsp_base;
2389
2390 switch (offset) {
2391 case 0x04: /* DSP_IDLECT1 */
2392 return s->clkm.dsp_idlect1;
2393
2394 case 0x08: /* DSP_IDLECT2 */
2395 return s->clkm.dsp_idlect2;
2396
2397 case 0x14: /* DSP_RSTCT2 */
2398 return s->clkm.dsp_rstct2;
2399
2400 case 0x18: /* DSP_SYSST */
d8f699cb 2401 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
c3d2689d
AZ		 2402 (s->env->halted << 6); /* Quite useless... */
2403 }
2404
2405 OMAP_BAD_REG(addr);
2406 return 0;
2407}
2408
2409static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2410 uint16_t diff, uint16_t value)
2411{
2412 omap_clk clk;
2413
2414 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2415}
2416
2417static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2418 uint16_t diff, uint16_t value)
2419{
2420 omap_clk clk;
2421
2422 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2423}
2424
2425static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
2426 uint32_t value)
2427{
2428 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2429 int offset = addr - s->clkm.dsp_base;
2430 uint16_t diff;
2431
2432 switch (offset) {
2433 case 0x04: /* DSP_IDLECT1 */
2434 diff = s->clkm.dsp_idlect1 ^ value;
2435 s->clkm.dsp_idlect1 = value & 0x01f7;
2436 omap_clkdsp_idlect1_update(s, diff, value);
2437 break;
2438
2439 case 0x08: /* DSP_IDLECT2 */
2440 s->clkm.dsp_idlect2 = value & 0x0037;
2441 diff = s->clkm.dsp_idlect1 ^ value;
2442 omap_clkdsp_idlect2_update(s, diff, value);
2443 break;
2444
2445 case 0x14: /* DSP_RSTCT2 */
2446 s->clkm.dsp_rstct2 = value & 0x0001;
2447 break;
2448
2449 case 0x18: /* DSP_SYSST */
2450 s->clkm.cold_start &= value & 0x3f;
2451 break;
2452
2453 default:
2454 OMAP_BAD_REG(addr);
2455 }
2456}
2457
2458static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
2459 omap_badwidth_read16,
2460 omap_clkdsp_read,
2461 omap_badwidth_read16,
2462};
2463
2464static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
2465 omap_badwidth_write16,
2466 omap_clkdsp_write,
2467 omap_badwidth_write16,
2468};
2469
2470static void omap_clkm_reset(struct omap_mpu_state_s *s)
2471{
2472 if (s->wdt && s->wdt->reset)
2473 s->clkm.cold_start = 0x6;
2474 s->clkm.clocking_scheme = 0;
2475 omap_clkm_ckctl_update(s, ~0, 0x3000);
2476 s->clkm.arm_ckctl = 0x3000;
d8f699cb 2477 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
c3d2689d 2478 s->clkm.arm_idlect1 = 0x0400;
d8f699cb 2479 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
c3d2689d
AZ		 2480 s->clkm.arm_idlect2 = 0x0100;
2481 s->clkm.arm_ewupct = 0x003f;
2482 s->clkm.arm_rstct1 = 0x0000;
2483 s->clkm.arm_rstct2 = 0x0000;
2484 s->clkm.arm_ckout1 = 0x0015;
2485 s->clkm.dpll1_mode = 0x2002;
2486 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2487 s->clkm.dsp_idlect1 = 0x0040;
2488 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2489 s->clkm.dsp_idlect2 = 0x0000;
2490 s->clkm.dsp_rstct2 = 0x0000;
2491}
2492
2493static void omap_clkm_init(target_phys_addr_t mpu_base,
2494 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
2495{
2496 int iomemtype[2] = {
2497 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
2498 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
2499 };
2500
2501 s->clkm.mpu_base = mpu_base;
2502 s->clkm.dsp_base = dsp_base;
d8f699cb
AZ		 2503 s->clkm.arm_idlect1 = 0x03ff;
2504 s->clkm.arm_idlect2 = 0x0100;
2505 s->clkm.dsp_idlect1 = 0x0002;
c3d2689d 2506 omap_clkm_reset(s);
d8f699cb 2507 s->clkm.cold_start = 0x3a;
c3d2689d
AZ		 2508
2509 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
2510 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
2511}
2512
fe71e81a
AZ		 2513/* MPU I/O */
2514struct omap_mpuio_s {
2515 target_phys_addr_t base;
2516 qemu_irq irq;
2517 qemu_irq kbd_irq;
2518 qemu_irq *in;
2519 qemu_irq handler[16];
2520 qemu_irq wakeup;
2521
2522 uint16_t inputs;
2523 uint16_t outputs;
2524 uint16_t dir;
2525 uint16_t edge;
2526 uint16_t mask;
2527 uint16_t ints;
2528
2529 uint16_t debounce;
2530 uint16_t latch;
2531 uint8_t event;
2532
2533 uint8_t buttons[5];
2534 uint8_t row_latch;
2535 uint8_t cols;
2536 int kbd_mask;
2537 int clk;
2538};
2539
2540static void omap_mpuio_set(void *opaque, int line, int level)
2541{
2542 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2543 uint16_t prev = s->inputs;
2544
2545 if (level)
2546 s->inputs |= 1 << line;
2547 else
2548 s->inputs &= ~(1 << line);
2549
2550 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2551 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2552 s->ints |= 1 << line;
2553 qemu_irq_raise(s->irq);
2554 /* TODO: wakeup */
2555 }
2556 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2557 (s->event >> 1) == line) /* PIN_SELECT */
2558 s->latch = s->inputs;
2559 }
2560}
2561
2562static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2563{
2564 int i;
2565 uint8_t *row, rows = 0, cols = ~s->cols;
2566
38a34e1d 2567 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
fe71e81a 2568 if (*row & cols)
38a34e1d 2569 rows |= i;
fe71e81a 2570
cf6d9118
AZ		 2571 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
2572 s->row_latch = ~rows;
fe71e81a
AZ		 2573}
2574
2575static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
2576{
2577 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2578 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2579 uint16_t ret;
2580
2581 switch (offset) {
2582 case 0x00: /* INPUT_LATCH */
2583 return s->inputs;
2584
2585 case 0x04: /* OUTPUT_REG */
2586 return s->outputs;
2587
2588 case 0x08: /* IO_CNTL */
2589 return s->dir;
2590
2591 case 0x10: /* KBR_LATCH */
2592 return s->row_latch;
2593
2594 case 0x14: /* KBC_REG */
2595 return s->cols;
2596
2597 case 0x18: /* GPIO_EVENT_MODE_REG */
2598 return s->event;
2599
2600 case 0x1c: /* GPIO_INT_EDGE_REG */
2601 return s->edge;
2602
2603 case 0x20: /* KBD_INT */
cf6d9118 2604 return (~s->row_latch & 0x1f) && !s->kbd_mask;
fe71e81a
AZ		 2605
2606 case 0x24: /* GPIO_INT */
2607 ret = s->ints;
8e129e07
AZ		 2608 s->ints &= s->mask;
2609 if (ret)
2610 qemu_irq_lower(s->irq);
fe71e81a
AZ		 2611 return ret;
2612
2613 case 0x28: /* KBD_MASKIT */
2614 return s->kbd_mask;
2615
2616 case 0x2c: /* GPIO_MASKIT */
2617 return s->mask;
2618
2619 case 0x30: /* GPIO_DEBOUNCING_REG */
2620 return s->debounce;
2621
2622 case 0x34: /* GPIO_LATCH_REG */
2623 return s->latch;
2624 }
2625
2626 OMAP_BAD_REG(addr);
2627 return 0;
2628}
2629
2630static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
2631 uint32_t value)
2632{
2633 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2634 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2635 uint16_t diff;
2636 int ln;
2637
2638 switch (offset) {
2639 case 0x04: /* OUTPUT_REG */
d8f699cb 2640 diff = (s->outputs ^ value) & ~s->dir;
fe71e81a 2641 s->outputs = value;
fe71e81a
AZ		 2642 while ((ln = ffs(diff))) {
2643 ln --;
2644 if (s->handler[ln])
2645 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2646 diff &= ~(1 << ln);
2647 }
2648 break;
2649
2650 case 0x08: /* IO_CNTL */
2651 diff = s->outputs & (s->dir ^ value);
2652 s->dir = value;
2653
2654 value = s->outputs & ~s->dir;
2655 while ((ln = ffs(diff))) {
2656 ln --;
2657 if (s->handler[ln])
2658 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2659 diff &= ~(1 << ln);
2660 }
2661 break;
2662
2663 case 0x14: /* KBC_REG */
2664 s->cols = value;
2665 omap_mpuio_kbd_update(s);
2666 break;
2667
2668 case 0x18: /* GPIO_EVENT_MODE_REG */
2669 s->event = value & 0x1f;
2670 break;
2671
2672 case 0x1c: /* GPIO_INT_EDGE_REG */
2673 s->edge = value;
2674 break;
2675
2676 case 0x28: /* KBD_MASKIT */
2677 s->kbd_mask = value & 1;
2678 omap_mpuio_kbd_update(s);
2679 break;
2680
2681 case 0x2c: /* GPIO_MASKIT */
2682 s->mask = value;
2683 break;
2684
2685 case 0x30: /* GPIO_DEBOUNCING_REG */
2686 s->debounce = value & 0x1ff;
2687 break;
2688
2689 case 0x00: /* INPUT_LATCH */
2690 case 0x10: /* KBR_LATCH */
2691 case 0x20: /* KBD_INT */
2692 case 0x24: /* GPIO_INT */
2693 case 0x34: /* GPIO_LATCH_REG */
2694 OMAP_RO_REG(addr);
2695 return;
2696
2697 default:
2698 OMAP_BAD_REG(addr);
2699 return;
2700 }
2701}
2702
2703static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
2704 omap_badwidth_read16,
2705 omap_mpuio_read,
2706 omap_badwidth_read16,
2707};
2708
2709static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
2710 omap_badwidth_write16,
2711 omap_mpuio_write,
2712 omap_badwidth_write16,
2713};
2714
9596ebb7 2715static void omap_mpuio_reset(struct omap_mpuio_s *s)
fe71e81a
AZ		 2716{
2717 s->inputs = 0;
2718 s->outputs = 0;
2719 s->dir = ~0;
2720 s->event = 0;
2721 s->edge = 0;
2722 s->kbd_mask = 0;
2723 s->mask = 0;
2724 s->debounce = 0;
2725 s->latch = 0;
2726 s->ints = 0;
2727 s->row_latch = 0x1f;
38a34e1d 2728 s->clk = 1;
fe71e81a
AZ		 2729}
2730
2731static void omap_mpuio_onoff(void *opaque, int line, int on)
2732{
2733 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2734
2735 s->clk = on;
2736 if (on)
2737 omap_mpuio_kbd_update(s);
2738}
2739
2740struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
2741 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2742 omap_clk clk)
2743{
2744 int iomemtype;
2745 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2746 qemu_mallocz(sizeof(struct omap_mpuio_s));
2747
2748 s->base = base;
2749 s->irq = gpio_int;
2750 s->kbd_irq = kbd_int;
2751 s->wakeup = wakeup;
2752 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2753 omap_mpuio_reset(s);
2754
2755 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
2756 omap_mpuio_writefn, s);
2757 cpu_register_physical_memory(s->base, 0x800, iomemtype);
2758
2759 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2760
2761 return s;
2762}
2763
2764qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2765{
2766 return s->in;
2767}
2768
2769void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2770{
2771 if (line >= 16 || line < 0)
2772 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2773 s->handler[line] = handler;
2774}
2775
2776void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2777{
2778 if (row >= 5 || row < 0)
2779 cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
2780 __FUNCTION__, col, row);
2781
2782 if (down)
38a34e1d 2783 s->buttons[row] |= 1 << col;
fe71e81a 2784 else
38a34e1d 2785 s->buttons[row] &= ~(1 << col);
fe71e81a
AZ		 2786
2787 omap_mpuio_kbd_update(s);
2788}
2789
64330148
AZ		 2790/* General-Purpose I/O */
2791struct omap_gpio_s {
2792 target_phys_addr_t base;
2793 qemu_irq irq;
2794 qemu_irq *in;
2795 qemu_irq handler[16];
2796
2797 uint16_t inputs;
2798 uint16_t outputs;
2799 uint16_t dir;
2800 uint16_t edge;
2801 uint16_t mask;
2802 uint16_t ints;
d8f699cb 2803 uint16_t pins;
64330148
AZ		 2804};
2805
2806static void omap_gpio_set(void *opaque, int line, int level)
2807{
2808 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2809 uint16_t prev = s->inputs;
2810
2811 if (level)
2812 s->inputs |= 1 << line;
2813 else
2814 s->inputs &= ~(1 << line);
2815
2816 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
2817 (1 << line) & s->dir & ~s->mask) {
2818 s->ints |= 1 << line;
2819 qemu_irq_raise(s->irq);
2820 }
2821}
2822
2823static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
2824{
2825 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
cf965d24 2826 int offset = addr & OMAP_MPUI_REG_MASK;
64330148
AZ		 2827
2828 switch (offset) {
2829 case 0x00: /* DATA_INPUT */
d8f699cb 2830 return s->inputs & s->pins;
64330148
AZ		 2831
2832 case 0x04: /* DATA_OUTPUT */
2833 return s->outputs;
2834
2835 case 0x08: /* DIRECTION_CONTROL */
2836 return s->dir;
2837
2838 case 0x0c: /* INTERRUPT_CONTROL */
2839 return s->edge;
2840
2841 case 0x10: /* INTERRUPT_MASK */
2842 return s->mask;
2843
2844 case 0x14: /* INTERRUPT_STATUS */
2845 return s->ints;
d8f699cb
AZ		 2846
2847 case 0x18: /* PIN_CONTROL (not in OMAP310) */
2848 OMAP_BAD_REG(addr);
2849 return s->pins;
64330148
AZ		 2850 }
2851
2852 OMAP_BAD_REG(addr);
2853 return 0;
2854}
2855
2856static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
2857 uint32_t value)
2858{
2859 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
cf965d24 2860 int offset = addr & OMAP_MPUI_REG_MASK;
64330148
AZ		 2861 uint16_t diff;
2862 int ln;
2863
2864 switch (offset) {
2865 case 0x00: /* DATA_INPUT */
2866 OMAP_RO_REG(addr);
2867 return;
2868
2869 case 0x04: /* DATA_OUTPUT */
66450b15 2870 diff = (s->outputs ^ value) & ~s->dir;
64330148 2871 s->outputs = value;
64330148
AZ		 2872 while ((ln = ffs(diff))) {
2873 ln --;
2874 if (s->handler[ln])
2875 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2876 diff &= ~(1 << ln);
2877 }
2878 break;
2879
2880 case 0x08: /* DIRECTION_CONTROL */
2881 diff = s->outputs & (s->dir ^ value);
2882 s->dir = value;
2883
2884 value = s->outputs & ~s->dir;
2885 while ((ln = ffs(diff))) {
2886 ln --;
2887 if (s->handler[ln])
2888 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2889 diff &= ~(1 << ln);
2890 }
2891 break;
2892
2893 case 0x0c: /* INTERRUPT_CONTROL */
2894 s->edge = value;
2895 break;
2896
2897 case 0x10: /* INTERRUPT_MASK */
2898 s->mask = value;
2899 break;
2900
2901 case 0x14: /* INTERRUPT_STATUS */
2902 s->ints &= ~value;
2903 if (!s->ints)
2904 qemu_irq_lower(s->irq);
2905 break;
2906
d8f699cb
AZ		 2907 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
2908 OMAP_BAD_REG(addr);
2909 s->pins = value;
2910 break;
2911
64330148
AZ		 2912 default:
2913 OMAP_BAD_REG(addr);
2914 return;
2915 }
2916}
2917
3efda49d 2918/* *Some* sources say the memory region is 32-bit. */
64330148 2919static CPUReadMemoryFunc *omap_gpio_readfn[] = {
3efda49d 2920 omap_badwidth_read16,
64330148 2921 omap_gpio_read,
3efda49d 2922 omap_badwidth_read16,
64330148
AZ		 2923};
2924
2925static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
3efda49d 2926 omap_badwidth_write16,
64330148 2927 omap_gpio_write,
3efda49d 2928 omap_badwidth_write16,
64330148
AZ		 2929};
2930
9596ebb7 2931static void omap_gpio_reset(struct omap_gpio_s *s)
64330148
AZ		 2932{
2933 s->inputs = 0;
2934 s->outputs = ~0;
2935 s->dir = ~0;
2936 s->edge = ~0;
2937 s->mask = ~0;
2938 s->ints = 0;
d8f699cb 2939 s->pins = ~0;
64330148
AZ		 2940}
2941
2942struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
2943 qemu_irq irq, omap_clk clk)
2944{
2945 int iomemtype;
2946 struct omap_gpio_s *s = (struct omap_gpio_s *)
2947 qemu_mallocz(sizeof(struct omap_gpio_s));
2948
2949 s->base = base;
2950 s->irq = irq;
2951 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
2952 omap_gpio_reset(s);
2953
2954 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
2955 omap_gpio_writefn, s);
2956 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
2957
2958 return s;
2959}
2960
2961qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
2962{
2963 return s->in;
2964}
2965
2966void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
2967{
2968 if (line >= 16 || line < 0)
2969 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2970 s->handler[line] = handler;
2971}
2972
d951f6ff
AZ		 2973/* MicroWire Interface */
2974struct omap_uwire_s {
2975 target_phys_addr_t base;
2976 qemu_irq txirq;
2977 qemu_irq rxirq;
2978 qemu_irq txdrq;
2979
2980 uint16_t txbuf;
2981 uint16_t rxbuf;
2982 uint16_t control;
2983 uint16_t setup[5];
2984
2985 struct uwire_slave_s *chip[4];
2986};
2987
2988static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2989{
2990 int chipselect = (s->control >> 10) & 3; /* INDEX */
2991 struct uwire_slave_s *slave = s->chip[chipselect];
2992
2993 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2994 if (s->control & (1 << 12)) /* CS_CMD */
2995 if (slave && slave->send)
2996 slave->send(slave->opaque,
2997 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2998 s->control &= ~(1 << 14); /* CSRB */
2999 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3000 * a DRQ. When is the level IRQ supposed to be reset? */
3001 }
3002
3003 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
3004 if (s->control & (1 << 12)) /* CS_CMD */
3005 if (slave && slave->receive)
3006 s->rxbuf = slave->receive(slave->opaque);
3007 s->control |= 1 << 15; /* RDRB */
3008 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3009 * a DRQ. When is the level IRQ supposed to be reset? */
3010 }
3011}
3012
3013static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
3014{
3015 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 3016 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 3017
3018 switch (offset) {
3019 case 0x00: /* RDR */
3020 s->control &= ~(1 << 15); /* RDRB */
3021 return s->rxbuf;
3022
3023 case 0x04: /* CSR */
3024 return s->control;
3025
3026 case 0x08: /* SR1 */
3027 return s->setup[0];
3028 case 0x0c: /* SR2 */
3029 return s->setup[1];
3030 case 0x10: /* SR3 */
3031 return s->setup[2];
3032 case 0x14: /* SR4 */
3033 return s->setup[3];
3034 case 0x18: /* SR5 */
3035 return s->setup[4];
3036 }
3037
3038 OMAP_BAD_REG(addr);
3039 return 0;
3040}
3041
3042static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
3043 uint32_t value)
3044{
3045 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 3046 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 3047
3048 switch (offset) {
3049 case 0x00: /* TDR */
3050 s->txbuf = value; /* TD */
d951f6ff
AZ		 3051 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3052 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
cf965d24
AZ		 3053 (s->control & (1 << 12)))) { /* CS_CMD */
3054 s->control |= 1 << 14; /* CSRB */
d951f6ff 3055 omap_uwire_transfer_start(s);
cf965d24 3056 }
d951f6ff
AZ		 3057 break;
3058
3059 case 0x04: /* CSR */
3060 s->control = value & 0x1fff;
3061 if (value & (1 << 13)) /* START */
3062 omap_uwire_transfer_start(s);
3063 break;
3064
3065 case 0x08: /* SR1 */
3066 s->setup[0] = value & 0x003f;
3067 break;
3068
3069 case 0x0c: /* SR2 */
3070 s->setup[1] = value & 0x0fc0;
3071 break;
3072
3073 case 0x10: /* SR3 */
3074 s->setup[2] = value & 0x0003;
3075 break;
3076
3077 case 0x14: /* SR4 */
3078 s->setup[3] = value & 0x0001;
3079 break;
3080
3081 case 0x18: /* SR5 */
3082 s->setup[4] = value & 0x000f;
3083 break;
3084
3085 default:
3086 OMAP_BAD_REG(addr);
3087 return;
3088 }
3089}
3090
3091static CPUReadMemoryFunc *omap_uwire_readfn[] = {
3092 omap_badwidth_read16,
3093 omap_uwire_read,
3094 omap_badwidth_read16,
3095};
3096
3097static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
3098 omap_badwidth_write16,
3099 omap_uwire_write,
3100 omap_badwidth_write16,
3101};
3102
9596ebb7 3103static void omap_uwire_reset(struct omap_uwire_s *s)
d951f6ff 3104{
66450b15 3105 s->control = 0;
d951f6ff
AZ		 3106 s->setup[0] = 0;
3107 s->setup[1] = 0;
3108 s->setup[2] = 0;
3109 s->setup[3] = 0;
3110 s->setup[4] = 0;
3111}
3112
3113struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
3114 qemu_irq *irq, qemu_irq dma, omap_clk clk)
3115{
3116 int iomemtype;
3117 struct omap_uwire_s *s = (struct omap_uwire_s *)
3118 qemu_mallocz(sizeof(struct omap_uwire_s));
3119
3120 s->base = base;
3121 s->txirq = irq[0];
3122 s->rxirq = irq[1];
3123 s->txdrq = dma;
3124 omap_uwire_reset(s);
3125
3126 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
3127 omap_uwire_writefn, s);
3128 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3129
3130 return s;
3131}
3132
3133void omap_uwire_attach(struct omap_uwire_s *s,
3134 struct uwire_slave_s *slave, int chipselect)
3135{
827df9f3
AZ		 3136 if (chipselect < 0 || chipselect > 3) {
3137 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
3138 exit(-1);
3139 }
d951f6ff
AZ		 3140
3141 s->chip[chipselect] = slave;
3142}
3143
66450b15 3144/* Pseudonoise Pulse-Width Light Modulator */
9596ebb7 3145static void omap_pwl_update(struct omap_mpu_state_s *s)
66450b15
AZ		 3146{
3147 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
3148
3149 if (output != s->pwl.output) {
3150 s->pwl.output = output;
3151 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
3152 }
3153}
3154
3155static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
3156{
3157 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3158 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 3159
3160 switch (offset) {
3161 case 0x00: /* PWL_LEVEL */
3162 return s->pwl.level;
3163 case 0x04: /* PWL_CTRL */
3164 return s->pwl.enable;
3165 }
3166 OMAP_BAD_REG(addr);
3167 return 0;
3168}
3169
3170static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
3171 uint32_t value)
3172{
3173 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3174 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 3175
3176 switch (offset) {
3177 case 0x00: /* PWL_LEVEL */
3178 s->pwl.level = value;
3179 omap_pwl_update(s);
3180 break;
3181 case 0x04: /* PWL_CTRL */
3182 s->pwl.enable = value & 1;
3183 omap_pwl_update(s);
3184 break;
3185 default:
3186 OMAP_BAD_REG(addr);
3187 return;
3188 }
3189}
3190
3191static CPUReadMemoryFunc *omap_pwl_readfn[] = {
02645926 3192 omap_pwl_read,
66450b15
AZ		 3193 omap_badwidth_read8,
3194 omap_badwidth_read8,
66450b15
AZ		 3195};
3196
3197static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
02645926 3198 omap_pwl_write,
66450b15
AZ		 3199 omap_badwidth_write8,
3200 omap_badwidth_write8,
66450b15
AZ		 3201};
3202
9596ebb7 3203static void omap_pwl_reset(struct omap_mpu_state_s *s)
66450b15
AZ		 3204{
3205 s->pwl.output = 0;
3206 s->pwl.level = 0;
3207 s->pwl.enable = 0;
3208 s->pwl.clk = 1;
3209 omap_pwl_update(s);
3210}
3211
3212static void omap_pwl_clk_update(void *opaque, int line, int on)
3213{
3214 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3215
3216 s->pwl.clk = on;
3217 omap_pwl_update(s);
3218}
3219
3220static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3221 omap_clk clk)
3222{
3223 int iomemtype;
3224
66450b15
AZ		 3225 omap_pwl_reset(s);
3226
3227 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
3228 omap_pwl_writefn, s);
b854bc19 3229 cpu_register_physical_memory(base, 0x800, iomemtype);
66450b15
AZ		 3230
3231 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3232}
3233
f34c417b
AZ		 3234/* Pulse-Width Tone module */
3235static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
3236{
3237 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3238 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 3239
3240 switch (offset) {
3241 case 0x00: /* FRC */
3242 return s->pwt.frc;
3243 case 0x04: /* VCR */
3244 return s->pwt.vrc;
3245 case 0x08: /* GCR */
3246 return s->pwt.gcr;
3247 }
3248 OMAP_BAD_REG(addr);
3249 return 0;
3250}
3251
3252static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
3253 uint32_t value)
3254{
3255 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3256 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 3257
3258 switch (offset) {
3259 case 0x00: /* FRC */
3260 s->pwt.frc = value & 0x3f;
3261 break;
3262 case 0x04: /* VRC */
3263 if ((value ^ s->pwt.vrc) & 1) {
3264 if (value & 1)
3265 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3266 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3267 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3268 /* Pre-multiplexer divider */
3269 ((s->pwt.gcr & 2) ? 1 : 154) /
3270 /* Octave multiplexer */
3271 (2 << (value & 3)) *
3272 /* 101/107 divider */
3273 ((value & (1 << 2)) ? 101 : 107) *
3274 /* 49/55 divider */
3275 ((value & (1 << 3)) ? 49 : 55) *
3276 /* 50/63 divider */
3277 ((value & (1 << 4)) ? 50 : 63) *
3278 /* 80/127 divider */
3279 ((value & (1 << 5)) ? 80 : 127) /
3280 (107 * 55 * 63 * 127)));
3281 else
3282 printf("%s: silence!\n", __FUNCTION__);
3283 }
3284 s->pwt.vrc = value & 0x7f;
3285 break;
3286 case 0x08: /* GCR */
3287 s->pwt.gcr = value & 3;
3288 break;
3289 default:
3290 OMAP_BAD_REG(addr);
3291 return;
3292 }
3293}
3294
3295static CPUReadMemoryFunc *omap_pwt_readfn[] = {
02645926 3296 omap_pwt_read,
f34c417b
AZ		 3297 omap_badwidth_read8,
3298 omap_badwidth_read8,
f34c417b
AZ		 3299};
3300
3301static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
02645926 3302 omap_pwt_write,
f34c417b
AZ		 3303 omap_badwidth_write8,
3304 omap_badwidth_write8,
f34c417b
AZ		 3305};
3306
9596ebb7 3307static void omap_pwt_reset(struct omap_mpu_state_s *s)
f34c417b
AZ		 3308{
3309 s->pwt.frc = 0;
3310 s->pwt.vrc = 0;
3311 s->pwt.gcr = 0;
3312}
3313
3314static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3315 omap_clk clk)
3316{
3317 int iomemtype;
3318
f34c417b
AZ		 3319 s->pwt.clk = clk;
3320 omap_pwt_reset(s);
3321
3322 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
3323 omap_pwt_writefn, s);
b854bc19 3324 cpu_register_physical_memory(base, 0x800, iomemtype);
f34c417b
AZ		 3325}
3326
5c1c390f
AZ		 3327/* Real-time Clock module */
3328struct omap_rtc_s {
3329 target_phys_addr_t base;
3330 qemu_irq irq;
3331 qemu_irq alarm;
3332 QEMUTimer *clk;
3333
3334 uint8_t interrupts;
3335 uint8_t status;
3336 int16_t comp_reg;
3337 int running;
3338 int pm_am;
3339 int auto_comp;
3340 int round;
5c1c390f
AZ		 3341 struct tm alarm_tm;
3342 time_t alarm_ti;
3343
3344 struct tm current_tm;
3345 time_t ti;
3346 uint64_t tick;
3347};
3348
3349static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3350{
106627d0 3351 /* s->alarm is level-triggered */
5c1c390f
AZ		 3352 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3353}
3354
3355static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3356{
3357 s->alarm_ti = mktime(&s->alarm_tm);
3358 if (s->alarm_ti == -1)
3359 printf("%s: conversion failed\n", __FUNCTION__);
3360}
3361
3362static inline uint8_t omap_rtc_bcd(int num)
3363{
3364 return ((num / 10) << 4) | (num % 10);
3365}
3366
3367static inline int omap_rtc_bin(uint8_t num)
3368{
3369 return (num & 15) + 10 * (num >> 4);
3370}
3371
3372static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
3373{
3374 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 3375 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 3376 uint8_t i;
3377
3378 switch (offset) {
3379 case 0x00: /* SECONDS_REG */
3380 return omap_rtc_bcd(s->current_tm.tm_sec);
3381
3382 case 0x04: /* MINUTES_REG */
3383 return omap_rtc_bcd(s->current_tm.tm_min);
3384
3385 case 0x08: /* HOURS_REG */
3386 if (s->pm_am)
3387 return ((s->current_tm.tm_hour > 11) << 7) |
3388 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
3389 else
3390 return omap_rtc_bcd(s->current_tm.tm_hour);
3391
3392 case 0x0c: /* DAYS_REG */
3393 return omap_rtc_bcd(s->current_tm.tm_mday);
3394
3395 case 0x10: /* MONTHS_REG */
3396 return omap_rtc_bcd(s->current_tm.tm_mon + 1);
3397
3398 case 0x14: /* YEARS_REG */
3399 return omap_rtc_bcd(s->current_tm.tm_year % 100);
3400
3401 case 0x18: /* WEEK_REG */
3402 return s->current_tm.tm_wday;
3403
3404 case 0x20: /* ALARM_SECONDS_REG */
3405 return omap_rtc_bcd(s->alarm_tm.tm_sec);
3406
3407 case 0x24: /* ALARM_MINUTES_REG */
3408 return omap_rtc_bcd(s->alarm_tm.tm_min);
3409
3410 case 0x28: /* ALARM_HOURS_REG */
3411 if (s->pm_am)
3412 return ((s->alarm_tm.tm_hour > 11) << 7) |
3413 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
3414 else
3415 return omap_rtc_bcd(s->alarm_tm.tm_hour);
3416
3417 case 0x2c: /* ALARM_DAYS_REG */
3418 return omap_rtc_bcd(s->alarm_tm.tm_mday);
3419
3420 case 0x30: /* ALARM_MONTHS_REG */
3421 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1);
3422
3423 case 0x34: /* ALARM_YEARS_REG */
3424 return omap_rtc_bcd(s->alarm_tm.tm_year % 100);
3425
3426 case 0x40: /* RTC_CTRL_REG */
3427 return (s->pm_am << 3) | (s->auto_comp << 2) |
3428 (s->round << 1) | s->running;
3429
3430 case 0x44: /* RTC_STATUS_REG */
3431 i = s->status;
3432 s->status &= ~0x3d;
3433 return i;
3434
3435 case 0x48: /* RTC_INTERRUPTS_REG */
3436 return s->interrupts;
3437
3438 case 0x4c: /* RTC_COMP_LSB_REG */
3439 return ((uint16_t) s->comp_reg) & 0xff;
3440
3441 case 0x50: /* RTC_COMP_MSB_REG */
3442 return ((uint16_t) s->comp_reg) >> 8;
3443 }
3444
3445 OMAP_BAD_REG(addr);
3446 return 0;
3447}
3448
3449static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
3450 uint32_t value)
3451{
3452 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 3453 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 3454 struct tm new_tm;
3455 time_t ti[2];
3456
3457 switch (offset) {
3458 case 0x00: /* SECONDS_REG */
3459#if ALMDEBUG
3460 printf("RTC SEC_REG <-- %02x\n", value);
3461#endif
3462 s->ti -= s->current_tm.tm_sec;
3463 s->ti += omap_rtc_bin(value);
3464 return;
3465
3466 case 0x04: /* MINUTES_REG */
3467#if ALMDEBUG
3468 printf("RTC MIN_REG <-- %02x\n", value);
3469#endif
3470 s->ti -= s->current_tm.tm_min * 60;
3471 s->ti += omap_rtc_bin(value) * 60;
3472 return;
3473
3474 case 0x08: /* HOURS_REG */
3475#if ALMDEBUG
3476 printf("RTC HRS_REG <-- %02x\n", value);
3477#endif
3478 s->ti -= s->current_tm.tm_hour * 3600;
3479 if (s->pm_am) {
3480 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600;
3481 s->ti += ((value >> 7) & 1) * 43200;
3482 } else
3483 s->ti += omap_rtc_bin(value & 0x3f) * 3600;
3484 return;
3485
3486 case 0x0c: /* DAYS_REG */
3487#if ALMDEBUG
3488 printf("RTC DAY_REG <-- %02x\n", value);
3489#endif
3490 s->ti -= s->current_tm.tm_mday * 86400;
3491 s->ti += omap_rtc_bin(value) * 86400;
3492 return;
3493
3494 case 0x10: /* MONTHS_REG */
3495#if ALMDEBUG
3496 printf("RTC MTH_REG <-- %02x\n", value);
3497#endif
3498 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3499 new_tm.tm_mon = omap_rtc_bin(value);
3500 ti[0] = mktime(&s->current_tm);
3501 ti[1] = mktime(&new_tm);
3502
3503 if (ti[0] != -1 && ti[1] != -1) {
3504 s->ti -= ti[0];
3505 s->ti += ti[1];
3506 } else {
3507 /* A less accurate version */
3508 s->ti -= s->current_tm.tm_mon * 2592000;
3509 s->ti += omap_rtc_bin(value) * 2592000;
3510 }
3511 return;
3512
3513 case 0x14: /* YEARS_REG */
3514#if ALMDEBUG
3515 printf("RTC YRS_REG <-- %02x\n", value);
3516#endif
3517 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3518 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
3519 ti[0] = mktime(&s->current_tm);
3520 ti[1] = mktime(&new_tm);
3521
3522 if (ti[0] != -1 && ti[1] != -1) {
3523 s->ti -= ti[0];
3524 s->ti += ti[1];
3525 } else {
3526 /* A less accurate version */
3527 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
3528 s->ti += omap_rtc_bin(value) * 31536000;
3529 }
3530 return;
3531
3532 case 0x18: /* WEEK_REG */
3533 return; /* Ignored */
3534
3535 case 0x20: /* ALARM_SECONDS_REG */
3536#if ALMDEBUG
3537 printf("ALM SEC_REG <-- %02x\n", value);
3538#endif
3539 s->alarm_tm.tm_sec = omap_rtc_bin(value);
3540 omap_rtc_alarm_update(s);
3541 return;
3542
3543 case 0x24: /* ALARM_MINUTES_REG */
3544#if ALMDEBUG
3545 printf("ALM MIN_REG <-- %02x\n", value);
3546#endif
3547 s->alarm_tm.tm_min = omap_rtc_bin(value);
3548 omap_rtc_alarm_update(s);
3549 return;
3550
3551 case 0x28: /* ALARM_HOURS_REG */
3552#if ALMDEBUG
3553 printf("ALM HRS_REG <-- %02x\n", value);
3554#endif
3555 if (s->pm_am)
3556 s->alarm_tm.tm_hour =
3557 ((omap_rtc_bin(value & 0x3f)) % 12) +
3558 ((value >> 7) & 1) * 12;
3559 else
3560 s->alarm_tm.tm_hour = omap_rtc_bin(value);
3561 omap_rtc_alarm_update(s);
3562 return;
3563
3564 case 0x2c: /* ALARM_DAYS_REG */
3565#if ALMDEBUG
3566 printf("ALM DAY_REG <-- %02x\n", value);
3567#endif
3568 s->alarm_tm.tm_mday = omap_rtc_bin(value);
3569 omap_rtc_alarm_update(s);
3570 return;
3571
3572 case 0x30: /* ALARM_MONTHS_REG */
3573#if ALMDEBUG
3574 printf("ALM MON_REG <-- %02x\n", value);
3575#endif
3576 s->alarm_tm.tm_mon = omap_rtc_bin(value);
3577 omap_rtc_alarm_update(s);
3578 return;
3579
3580 case 0x34: /* ALARM_YEARS_REG */
3581#if ALMDEBUG
3582 printf("ALM YRS_REG <-- %02x\n", value);
3583#endif
3584 s->alarm_tm.tm_year = omap_rtc_bin(value);
3585 omap_rtc_alarm_update(s);
3586 return;
3587
3588 case 0x40: /* RTC_CTRL_REG */
3589#if ALMDEBUG
3590 printf("RTC CONTROL <-- %02x\n", value);
3591#endif
3592 s->pm_am = (value >> 3) & 1;
3593 s->auto_comp = (value >> 2) & 1;
3594 s->round = (value >> 1) & 1;
3595 s->running = value & 1;
3596 s->status &= 0xfd;
3597 s->status |= s->running << 1;
3598 return;
3599
3600 case 0x44: /* RTC_STATUS_REG */
3601#if ALMDEBUG
3602 printf("RTC STATUSL <-- %02x\n", value);
3603#endif
3604 s->status &= ~((value & 0xc0) ^ 0x80);
3605 omap_rtc_interrupts_update(s);
3606 return;
3607
3608 case 0x48: /* RTC_INTERRUPTS_REG */
3609#if ALMDEBUG
3610 printf("RTC INTRS <-- %02x\n", value);
3611#endif
3612 s->interrupts = value;
3613 return;
3614
3615 case 0x4c: /* RTC_COMP_LSB_REG */
3616#if ALMDEBUG
3617 printf("RTC COMPLSB <-- %02x\n", value);
3618#endif
3619 s->comp_reg &= 0xff00;
3620 s->comp_reg |= 0x00ff & value;
3621 return;
3622
3623 case 0x50: /* RTC_COMP_MSB_REG */
3624#if ALMDEBUG
3625 printf("RTC COMPMSB <-- %02x\n", value);
3626#endif
3627 s->comp_reg &= 0x00ff;
3628 s->comp_reg |= 0xff00 & (value << 8);
3629 return;
3630
3631 default:
3632 OMAP_BAD_REG(addr);
3633 return;
3634 }
3635}
3636
3637static CPUReadMemoryFunc *omap_rtc_readfn[] = {
3638 omap_rtc_read,
3639 omap_badwidth_read8,
3640 omap_badwidth_read8,
3641};
3642
3643static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
3644 omap_rtc_write,
3645 omap_badwidth_write8,
3646 omap_badwidth_write8,
3647};
3648
3649static void omap_rtc_tick(void *opaque)
3650{
3651 struct omap_rtc_s *s = opaque;
3652
3653 if (s->round) {
3654 /* Round to nearest full minute. */
3655 if (s->current_tm.tm_sec < 30)
3656 s->ti -= s->current_tm.tm_sec;
3657 else
3658 s->ti += 60 - s->current_tm.tm_sec;
3659
3660 s->round = 0;
3661 }
3662
f6503059 3663 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
5c1c390f
AZ		 3664
3665 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3666 s->status |= 0x40;
3667 omap_rtc_interrupts_update(s);
3668 }
3669
3670 if (s->interrupts & 0x04)
3671 switch (s->interrupts & 3) {
3672 case 0:
3673 s->status |= 0x04;
106627d0 3674 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3675 break;
3676 case 1:
3677 if (s->current_tm.tm_sec)
3678 break;
3679 s->status |= 0x08;
106627d0 3680 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3681 break;
3682 case 2:
3683 if (s->current_tm.tm_sec || s->current_tm.tm_min)
3684 break;
3685 s->status |= 0x10;
106627d0 3686 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3687 break;
3688 case 3:
3689 if (s->current_tm.tm_sec ||
3690 s->current_tm.tm_min || s->current_tm.tm_hour)
3691 break;
3692 s->status |= 0x20;
106627d0 3693 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3694 break;
3695 }
3696
3697 /* Move on */
3698 if (s->running)
3699 s->ti ++;
3700 s->tick += 1000;
3701
3702 /*
3703 * Every full hour add a rough approximation of the compensation
3704 * register to the 32kHz Timer (which drives the RTC) value.
3705 */
3706 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
3707 s->tick += s->comp_reg * 1000 / 32768;
3708
3709 qemu_mod_timer(s->clk, s->tick);
3710}
3711
9596ebb7 3712static void omap_rtc_reset(struct omap_rtc_s *s)
5c1c390f 3713{
f6503059
AZ		 3714 struct tm tm;
3715
5c1c390f
AZ		 3716 s->interrupts = 0;
3717 s->comp_reg = 0;
3718 s->running = 0;
3719 s->pm_am = 0;
3720 s->auto_comp = 0;
3721 s->round = 0;
3722 s->tick = qemu_get_clock(rt_clock);
3723 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
3724 s->alarm_tm.tm_mday = 0x01;
3725 s->status = 1 << 7;
f6503059
AZ		 3726 qemu_get_timedate(&tm, 0);
3727 s->ti = mktime(&tm);
5c1c390f
AZ		 3728
3729 omap_rtc_alarm_update(s);
3730 omap_rtc_tick(s);
3731}
3732
3733struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
3734 qemu_irq *irq, omap_clk clk)
3735{
3736 int iomemtype;
3737 struct omap_rtc_s *s = (struct omap_rtc_s *)
3738 qemu_mallocz(sizeof(struct omap_rtc_s));
3739
3740 s->base = base;
3741 s->irq = irq[0];
3742 s->alarm = irq[1];
3743 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
5c1c390f
AZ		 3744
3745 omap_rtc_reset(s);
3746
3747 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
3748 omap_rtc_writefn, s);
3749 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3750
3751 return s;
3752}
3753
d8f699cb
AZ		 3754/* Multi-channel Buffered Serial Port interfaces */
3755struct omap_mcbsp_s {
3756 target_phys_addr_t base;
3757 qemu_irq txirq;
3758 qemu_irq rxirq;
3759 qemu_irq txdrq;
3760 qemu_irq rxdrq;
3761
3762 uint16_t spcr[2];
3763 uint16_t rcr[2];
3764 uint16_t xcr[2];
3765 uint16_t srgr[2];
3766 uint16_t mcr[2];
3767 uint16_t pcr;
3768 uint16_t rcer[8];
3769 uint16_t xcer[8];
3770 int tx_rate;
3771 int rx_rate;
3772 int tx_req;
73560bc8 3773 int rx_req;
d8f699cb
AZ		 3774
3775 struct i2s_codec_s *codec;
73560bc8
AZ		 3776 QEMUTimer *source_timer;
3777 QEMUTimer *sink_timer;
d8f699cb
AZ		 3778};
3779
3780static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
3781{
3782 int irq;
3783
3784 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
3785 case 0:
3786 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
3787 break;
3788 case 3:
3789 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3790 break;
3791 default:
3792 irq = 0;
3793 break;
3794 }
3795
106627d0
AZ		 3796 if (irq)
3797 qemu_irq_pulse(s->rxirq);
d8f699cb
AZ		 3798
3799 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3800 case 0:
3801 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3802 break;
3803 case 3:
3804 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3805 break;
3806 default:
3807 irq = 0;
3808 break;
3809 }
3810
106627d0
AZ		 3811 if (irq)
3812 qemu_irq_pulse(s->txirq);
d8f699cb
AZ		 3813}
3814
73560bc8 3815static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
d8f699cb 3816{
73560bc8
AZ		 3817 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3818 s->spcr[0] |= 1 << 2; /* RFULL */
3819 s->spcr[0] |= 1 << 1; /* RRDY */
3820 qemu_irq_raise(s->rxdrq);
3821 omap_mcbsp_intr_update(s);
d8f699cb
AZ		 3822}
3823
73560bc8 3824static void omap_mcbsp_source_tick(void *opaque)
d8f699cb 3825{
73560bc8
AZ		 3826 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3827 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3828
3829 if (!s->rx_rate)
d8f699cb 3830 return;
73560bc8
AZ		 3831 if (s->rx_req)
3832 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
d8f699cb 3833
73560bc8 3834 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
d8f699cb 3835
73560bc8
AZ		 3836 omap_mcbsp_rx_newdata(s);
3837 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
d8f699cb
AZ		 3838}
3839
3840static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3841{
73560bc8
AZ		 3842 if (!s->codec || !s->codec->rts)
3843 omap_mcbsp_source_tick(s);
3844 else if (s->codec->in.len) {
3845 s->rx_req = s->codec->in.len;
3846 omap_mcbsp_rx_newdata(s);
d8f699cb 3847 }
d8f699cb
AZ		 3848}
3849
3850static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
73560bc8
AZ		 3851{
3852 qemu_del_timer(s->source_timer);
3853}
3854
3855static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
d8f699cb
AZ		 3856{
3857 s->spcr[0] &= ~(1 << 1); /* RRDY */
3858 qemu_irq_lower(s->rxdrq);
3859 omap_mcbsp_intr_update(s);
3860}
3861
73560bc8
AZ		 3862static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3863{
3864 s->spcr[1] |= 1 << 1; /* XRDY */
3865 qemu_irq_raise(s->txdrq);
3866 omap_mcbsp_intr_update(s);
3867}
3868
3869static void omap_mcbsp_sink_tick(void *opaque)
d8f699cb 3870{
73560bc8
AZ		 3871 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3872 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3873
3874 if (!s->tx_rate)
d8f699cb 3875 return;
73560bc8
AZ		 3876 if (s->tx_req)
3877 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3878
3879 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3880
3881 omap_mcbsp_tx_newdata(s);
3882 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3883}
3884
3885static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3886{
3887 if (!s->codec || !s->codec->cts)
3888 omap_mcbsp_sink_tick(s);
3889 else if (s->codec->out.size) {
3890 s->tx_req = s->codec->out.size;
3891 omap_mcbsp_tx_newdata(s);
3892 }
3893}
3894
3895static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3896{
3897 s->spcr[1] &= ~(1 << 1); /* XRDY */
3898 qemu_irq_lower(s->txdrq);
3899 omap_mcbsp_intr_update(s);
3900 if (s->codec && s->codec->cts)
3901 s->codec->tx_swallow(s->codec->opaque);
d8f699cb
AZ		 3902}
3903
3904static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3905{
73560bc8
AZ		 3906 s->tx_req = 0;
3907 omap_mcbsp_tx_done(s);
3908 qemu_del_timer(s->sink_timer);
3909}
3910
3911static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3912{
3913 int prev_rx_rate, prev_tx_rate;
3914 int rx_rate = 0, tx_rate = 0;
3915 int cpu_rate = 1500000; /* XXX */
3916
3917 /* TODO: check CLKSTP bit */
3918 if (s->spcr[1] & (1 << 6)) { /* GRST */
3919 if (s->spcr[0] & (1 << 0)) { /* RRST */
3920 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3921 (s->pcr & (1 << 8))) { /* CLKRM */
3922 if (~s->pcr & (1 << 7)) /* SCLKME */
3923 rx_rate = cpu_rate /
3924 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3925 } else
3926 if (s->codec)
3927 rx_rate = s->codec->rx_rate;
3928 }
3929
3930 if (s->spcr[1] & (1 << 0)) { /* XRST */
3931 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3932 (s->pcr & (1 << 9))) { /* CLKXM */
3933 if (~s->pcr & (1 << 7)) /* SCLKME */
3934 tx_rate = cpu_rate /
3935 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3936 } else
3937 if (s->codec)
3938 tx_rate = s->codec->tx_rate;
3939 }
3940 }
3941 prev_tx_rate = s->tx_rate;
3942 prev_rx_rate = s->rx_rate;
3943 s->tx_rate = tx_rate;
3944 s->rx_rate = rx_rate;
3945
3946 if (s->codec)
3947 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3948
3949 if (!prev_tx_rate && tx_rate)
3950 omap_mcbsp_tx_start(s);
3951 else if (s->tx_rate && !tx_rate)
3952 omap_mcbsp_tx_stop(s);
3953
3954 if (!prev_rx_rate && rx_rate)
3955 omap_mcbsp_rx_start(s);
3956 else if (prev_tx_rate && !tx_rate)
3957 omap_mcbsp_rx_stop(s);
d8f699cb
AZ		 3958}
3959
3960static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
3961{
3962 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3963 int offset = addr & OMAP_MPUI_REG_MASK;
3964 uint16_t ret;
3965
3966 switch (offset) {
3967 case 0x00: /* DRR2 */
3968 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3969 return 0x0000;
3970 /* Fall through. */
3971 case 0x02: /* DRR1 */
73560bc8 3972 if (s->rx_req < 2) {
d8f699cb 3973 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
73560bc8 3974 omap_mcbsp_rx_done(s);
d8f699cb 3975 } else {
73560bc8
AZ		 3976 s->tx_req -= 2;
3977 if (s->codec && s->codec->in.len >= 2) {
3978 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3979 ret |= s->codec->in.fifo[s->codec->in.start ++];
3980 s->codec->in.len -= 2;
3981 } else
3982 ret = 0x0000;
3983 if (!s->tx_req)
3984 omap_mcbsp_rx_done(s);
d8f699cb
AZ		 3985 return ret;
3986 }
3987 return 0x0000;
3988
3989 case 0x04: /* DXR2 */
3990 case 0x06: /* DXR1 */
3991 return 0x0000;
3992
3993 case 0x08: /* SPCR2 */
3994 return s->spcr[1];
3995 case 0x0a: /* SPCR1 */
3996 return s->spcr[0];
3997 case 0x0c: /* RCR2 */
3998 return s->rcr[1];
3999 case 0x0e: /* RCR1 */
4000 return s->rcr[0];
4001 case 0x10: /* XCR2 */
4002 return s->xcr[1];
4003 case 0x12: /* XCR1 */
4004 return s->xcr[0];
4005 case 0x14: /* SRGR2 */
4006 return s->srgr[1];
4007 case 0x16: /* SRGR1 */
4008 return s->srgr[0];
4009 case 0x18: /* MCR2 */
4010 return s->mcr[1];
4011 case 0x1a: /* MCR1 */
4012 return s->mcr[0];
4013 case 0x1c: /* RCERA */
4014 return s->rcer[0];
4015 case 0x1e: /* RCERB */
4016 return s->rcer[1];
4017 case 0x20: /* XCERA */
4018 return s->xcer[0];
4019 case 0x22: /* XCERB */
4020 return s->xcer[1];
4021 case 0x24: /* PCR0 */
4022 return s->pcr;
4023 case 0x26: /* RCERC */
4024 return s->rcer[2];
4025 case 0x28: /* RCERD */
4026 return s->rcer[3];
4027 case 0x2a: /* XCERC */
4028 return s->xcer[2];
4029 case 0x2c: /* XCERD */
4030 return s->xcer[3];
4031 case 0x2e: /* RCERE */
4032 return s->rcer[4];
4033 case 0x30: /* RCERF */
4034 return s->rcer[5];
4035 case 0x32: /* XCERE */
4036 return s->xcer[4];
4037 case 0x34: /* XCERF */
4038 return s->xcer[5];
4039 case 0x36: /* RCERG */
4040 return s->rcer[6];
4041 case 0x38: /* RCERH */
4042 return s->rcer[7];
4043 case 0x3a: /* XCERG */
4044 return s->xcer[6];
4045 case 0x3c: /* XCERH */
4046 return s->xcer[7];
4047 }
4048
4049 OMAP_BAD_REG(addr);
4050 return 0;
4051}
4052
73560bc8 4053static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
d8f699cb
AZ		 4054 uint32_t value)
4055{
4056 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4057 int offset = addr & OMAP_MPUI_REG_MASK;
4058
4059 switch (offset) {
4060 case 0x00: /* DRR2 */
4061 case 0x02: /* DRR1 */
4062 OMAP_RO_REG(addr);
4063 return;
4064
4065 case 0x04: /* DXR2 */
4066 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4067 return;
4068 /* Fall through. */
4069 case 0x06: /* DXR1 */
73560bc8
AZ		 4070 if (s->tx_req > 1) {
4071 s->tx_req -= 2;
4072 if (s->codec && s->codec->cts) {
d8f699cb
AZ		 4073 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
4074 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
d8f699cb 4075 }
73560bc8
AZ		 4076 if (s->tx_req < 2)
4077 omap_mcbsp_tx_done(s);
d8f699cb
AZ		 4078 } else
4079 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4080 return;
4081
4082 case 0x08: /* SPCR2 */
4083 s->spcr[1] &= 0x0002;
4084 s->spcr[1] |= 0x03f9 & value;
4085 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
73560bc8 4086 if (~value & 1) /* XRST */
d8f699cb 4087 s->spcr[1] &= ~6;
d8f699cb
AZ		 4088 omap_mcbsp_req_update(s);
4089 return;
4090 case 0x0a: /* SPCR1 */
4091 s->spcr[0] &= 0x0006;
4092 s->spcr[0] |= 0xf8f9 & value;
4093 if (value & (1 << 15)) /* DLB */
4094 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
4095 if (~value & 1) { /* RRST */
4096 s->spcr[0] &= ~6;
73560bc8
AZ		 4097 s->rx_req = 0;
4098 omap_mcbsp_rx_done(s);
d8f699cb 4099 }
d8f699cb
AZ		 4100 omap_mcbsp_req_update(s);
4101 return;
4102
4103 case 0x0c: /* RCR2 */
4104 s->rcr[1] = value & 0xffff;
4105 return;
4106 case 0x0e: /* RCR1 */
4107 s->rcr[0] = value & 0x7fe0;
4108 return;
4109 case 0x10: /* XCR2 */
4110 s->xcr[1] = value & 0xffff;
4111 return;
4112 case 0x12: /* XCR1 */
4113 s->xcr[0] = value & 0x7fe0;
4114 return;
4115 case 0x14: /* SRGR2 */
4116 s->srgr[1] = value & 0xffff;
73560bc8 4117 omap_mcbsp_req_update(s);
d8f699cb
AZ		 4118 return;
4119 case 0x16: /* SRGR1 */
4120 s->srgr[0] = value & 0xffff;
73560bc8 4121 omap_mcbsp_req_update(s);
d8f699cb
AZ		 4122 return;
4123 case 0x18: /* MCR2 */
4124 s->mcr[1] = value & 0x03e3;
4125 if (value & 3) /* XMCM */
4126 printf("%s: Tx channel selection mode enable attempt\n",
4127 __FUNCTION__);
4128 return;
4129 case 0x1a: /* MCR1 */
4130 s->mcr[0] = value & 0x03e1;
4131 if (value & 1) /* RMCM */
4132 printf("%s: Rx channel selection mode enable attempt\n",
4133 __FUNCTION__);
4134 return;
4135 case 0x1c: /* RCERA */
4136 s->rcer[0] = value & 0xffff;
4137 return;
4138 case 0x1e: /* RCERB */
4139 s->rcer[1] = value & 0xffff;
4140 return;
4141 case 0x20: /* XCERA */
4142 s->xcer[0] = value & 0xffff;
4143 return;
4144 case 0x22: /* XCERB */
4145 s->xcer[1] = value & 0xffff;
4146 return;
4147 case 0x24: /* PCR0 */
4148 s->pcr = value & 0x7faf;
4149 return;
4150 case 0x26: /* RCERC */
4151 s->rcer[2] = value & 0xffff;
4152 return;
4153 case 0x28: /* RCERD */
4154 s->rcer[3] = value & 0xffff;
4155 return;
4156 case 0x2a: /* XCERC */
4157 s->xcer[2] = value & 0xffff;
4158 return;
4159 case 0x2c: /* XCERD */
4160 s->xcer[3] = value & 0xffff;
4161 return;
4162 case 0x2e: /* RCERE */
4163 s->rcer[4] = value & 0xffff;
4164 return;
4165 case 0x30: /* RCERF */
4166 s->rcer[5] = value & 0xffff;
4167 return;
4168 case 0x32: /* XCERE */
4169 s->xcer[4] = value & 0xffff;
4170 return;
4171 case 0x34: /* XCERF */
4172 s->xcer[5] = value & 0xffff;
4173 return;
4174 case 0x36: /* RCERG */
4175 s->rcer[6] = value & 0xffff;
4176 return;
4177 case 0x38: /* RCERH */
4178 s->rcer[7] = value & 0xffff;
4179 return;
4180 case 0x3a: /* XCERG */
4181 s->xcer[6] = value & 0xffff;
4182 return;
4183 case 0x3c: /* XCERH */
4184 s->xcer[7] = value & 0xffff;
4185 return;
4186 }
4187
4188 OMAP_BAD_REG(addr);
4189}
4190
73560bc8
AZ		 4191static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
4192 uint32_t value)
4193{
4194 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4195 int offset = addr & OMAP_MPUI_REG_MASK;
4196
4197 if (offset == 0x04) { /* DXR */
4198 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4199 return;
4200 if (s->tx_req > 3) {
4201 s->tx_req -= 4;
4202 if (s->codec && s->codec->cts) {
4203 s->codec->out.fifo[s->codec->out.len ++] =
4204 (value >> 24) & 0xff;
4205 s->codec->out.fifo[s->codec->out.len ++] =
4206 (value >> 16) & 0xff;
4207 s->codec->out.fifo[s->codec->out.len ++] =
4208 (value >> 8) & 0xff;
4209 s->codec->out.fifo[s->codec->out.len ++] =
4210 (value >> 0) & 0xff;
4211 }
4212 if (s->tx_req < 4)
4213 omap_mcbsp_tx_done(s);
4214 } else
4215 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4216 return;
4217 }
4218
4219 omap_badwidth_write16(opaque, addr, value);
4220}
4221
d8f699cb
AZ		 4222static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
4223 omap_badwidth_read16,
4224 omap_mcbsp_read,
4225 omap_badwidth_read16,
4226};
4227
4228static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
4229 omap_badwidth_write16,
73560bc8
AZ		 4230 omap_mcbsp_writeh,
4231 omap_mcbsp_writew,
d8f699cb
AZ		 4232};
4233
4234static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4235{
4236 memset(&s->spcr, 0, sizeof(s->spcr));
4237 memset(&s->rcr, 0, sizeof(s->rcr));
4238 memset(&s->xcr, 0, sizeof(s->xcr));
4239 s->srgr[0] = 0x0001;
4240 s->srgr[1] = 0x2000;
4241 memset(&s->mcr, 0, sizeof(s->mcr));
4242 memset(&s->pcr, 0, sizeof(s->pcr));
4243 memset(&s->rcer, 0, sizeof(s->rcer));
4244 memset(&s->xcer, 0, sizeof(s->xcer));
4245 s->tx_req = 0;
73560bc8 4246 s->rx_req = 0;
d8f699cb
AZ		 4247 s->tx_rate = 0;
4248 s->rx_rate = 0;
73560bc8
AZ		 4249 qemu_del_timer(s->source_timer);
4250 qemu_del_timer(s->sink_timer);
d8f699cb
AZ		 4251}
4252
4253struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
4254 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4255{
4256 int iomemtype;
4257 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4258 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4259
4260 s->base = base;
4261 s->txirq = irq[0];
4262 s->rxirq = irq[1];
4263 s->txdrq = dma[0];
4264 s->rxdrq = dma[1];
73560bc8
AZ		 4265 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
4266 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
d8f699cb
AZ		 4267 omap_mcbsp_reset(s);
4268
4269 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
4270 omap_mcbsp_writefn, s);
4271 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4272
4273 return s;
4274}
4275
9596ebb7 4276static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
d8f699cb
AZ		 4277{
4278 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4279
73560bc8
AZ		 4280 if (s->rx_rate) {
4281 s->rx_req = s->codec->in.len;
4282 omap_mcbsp_rx_newdata(s);
4283 }
d8f699cb
AZ		 4284}
4285
9596ebb7 4286static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
d8f699cb
AZ		 4287{
4288 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4289
73560bc8
AZ		 4290 if (s->tx_rate) {
4291 s->tx_req = s->codec->out.size;
4292 omap_mcbsp_tx_newdata(s);
4293 }
d8f699cb
AZ		 4294}
4295
4296void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
4297{
4298 s->codec = slave;
4299 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4300 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4301}
4302
f9d43072
AZ		 4303/* LED Pulse Generators */
4304struct omap_lpg_s {
4305 target_phys_addr_t base;
4306 QEMUTimer *tm;
4307
4308 uint8_t control;
4309 uint8_t power;
4310 int64_t on;
4311 int64_t period;
4312 int clk;
4313 int cycle;
4314};
4315
4316static void omap_lpg_tick(void *opaque)
4317{
4318 struct omap_lpg_s *s = opaque;
4319
4320 if (s->cycle)
4321 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
4322 else
4323 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
4324
4325 s->cycle = !s->cycle;
4326 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
4327}
4328
4329static void omap_lpg_update(struct omap_lpg_s *s)
4330{
4331 int64_t on, period = 1, ticks = 1000;
4332 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4333
4334 if (~s->control & (1 << 6)) /* LPGRES */
4335 on = 0;
4336 else if (s->control & (1 << 7)) /* PERM_ON */
4337 on = period;
4338 else {
4339 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
4340 256 / 32);
4341 on = (s->clk && s->power) ? muldiv64(ticks,
4342 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
4343 }
4344
4345 qemu_del_timer(s->tm);
4346 if (on == period && s->on < s->period)
4347 printf("%s: LED is on\n", __FUNCTION__);
4348 else if (on == 0 && s->on)
4349 printf("%s: LED is off\n", __FUNCTION__);
4350 else if (on && (on != s->on || period != s->period)) {
4351 s->cycle = 0;
4352 s->on = on;
4353 s->period = period;
4354 omap_lpg_tick(s);
4355 return;
4356 }
4357
4358 s->on = on;
4359 s->period = period;
4360}
4361
4362static void omap_lpg_reset(struct omap_lpg_s *s)
4363{
4364 s->control = 0x00;
4365 s->power = 0x00;
4366 s->clk = 1;
4367 omap_lpg_update(s);
4368}
4369
4370static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
4371{
4372 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4373 int offset = addr & OMAP_MPUI_REG_MASK;
4374
4375 switch (offset) {
4376 case 0x00: /* LCR */
4377 return s->control;
4378
4379 case 0x04: /* PMR */
4380 return s->power;
4381 }
4382
4383 OMAP_BAD_REG(addr);
4384 return 0;
4385}
4386
4387static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
4388 uint32_t value)
4389{
4390 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4391 int offset = addr & OMAP_MPUI_REG_MASK;
4392
4393 switch (offset) {
4394 case 0x00: /* LCR */
4395 if (~value & (1 << 6)) /* LPGRES */
4396 omap_lpg_reset(s);
4397 s->control = value & 0xff;
4398 omap_lpg_update(s);
4399 return;
4400
4401 case 0x04: /* PMR */
4402 s->power = value & 0x01;
4403 omap_lpg_update(s);
4404 return;
4405
4406 default:
4407 OMAP_BAD_REG(addr);
4408 return;
4409 }
4410}
4411
4412static CPUReadMemoryFunc *omap_lpg_readfn[] = {
4413 omap_lpg_read,
4414 omap_badwidth_read8,
4415 omap_badwidth_read8,
4416};
4417
4418static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
4419 omap_lpg_write,
4420 omap_badwidth_write8,
4421 omap_badwidth_write8,
4422};
4423
4424static void omap_lpg_clk_update(void *opaque, int line, int on)
4425{
4426 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4427
4428 s->clk = on;
4429 omap_lpg_update(s);
4430}
4431
4432struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
4433{
4434 int iomemtype;
4435 struct omap_lpg_s *s = (struct omap_lpg_s *)
4436 qemu_mallocz(sizeof(struct omap_lpg_s));
4437
4438 s->base = base;
4439 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
4440
4441 omap_lpg_reset(s);
4442
4443 iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
4444 omap_lpg_writefn, s);
4445 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4446
4447 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
4448
4449 return s;
4450}
4451
4452/* MPUI Peripheral Bridge configuration */
4453static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
4454{
4455 if (addr == OMAP_MPUI_BASE) /* CMR */
4456 return 0xfe4d;
4457
4458 OMAP_BAD_REG(addr);
4459 return 0;
4460}
4461
4462static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
4463 omap_badwidth_read16,
4464 omap_mpui_io_read,
4465 omap_badwidth_read16,
4466};
4467
4468static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
4469 omap_badwidth_write16,
4470 omap_badwidth_write16,
4471 omap_badwidth_write16,
4472};
4473
4474static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
4475{
4476 int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
4477 omap_mpui_io_writefn, mpu);
4478 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
4479}
4480
c3d2689d 4481/* General chip reset */
827df9f3 4482static void omap1_mpu_reset(void *opaque)
c3d2689d
AZ		 4483{
4484 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4485
c3d2689d
AZ		 4486 omap_inth_reset(mpu->ih[0]);
4487 omap_inth_reset(mpu->ih[1]);
4488 omap_dma_reset(mpu->dma);
4489 omap_mpu_timer_reset(mpu->timer[0]);
4490 omap_mpu_timer_reset(mpu->timer[1]);
4491 omap_mpu_timer_reset(mpu->timer[2]);
4492 omap_wd_timer_reset(mpu->wdt);
4493 omap_os_timer_reset(mpu->os_timer);
4494 omap_lcdc_reset(mpu->lcd);
4495 omap_ulpd_pm_reset(mpu);
4496 omap_pin_cfg_reset(mpu);
4497 omap_mpui_reset(mpu);
4498 omap_tipb_bridge_reset(mpu->private_tipb);
4499 omap_tipb_bridge_reset(mpu->public_tipb);
4500 omap_dpll_reset(&mpu->dpll[0]);
4501 omap_dpll_reset(&mpu->dpll[1]);
4502 omap_dpll_reset(&mpu->dpll[2]);
d951f6ff
AZ		 4503 omap_uart_reset(mpu->uart[0]);
4504 omap_uart_reset(mpu->uart[1]);
4505 omap_uart_reset(mpu->uart[2]);
b30bb3a2 4506 omap_mmc_reset(mpu->mmc);
fe71e81a 4507 omap_mpuio_reset(mpu->mpuio);
64330148 4508 omap_gpio_reset(mpu->gpio);
d951f6ff 4509 omap_uwire_reset(mpu->microwire);
66450b15 4510 omap_pwl_reset(mpu);
4a2c8ac2 4511 omap_pwt_reset(mpu);
827df9f3 4512 omap_i2c_reset(mpu->i2c[0]);
5c1c390f 4513 omap_rtc_reset(mpu->rtc);
d8f699cb
AZ		 4514 omap_mcbsp_reset(mpu->mcbsp1);
4515 omap_mcbsp_reset(mpu->mcbsp2);
4516 omap_mcbsp_reset(mpu->mcbsp3);
f9d43072
AZ		 4517 omap_lpg_reset(mpu->led[0]);
4518 omap_lpg_reset(mpu->led[1]);
8ef6367e 4519 omap_clkm_reset(mpu);
c3d2689d
AZ		 4520 cpu_reset(mpu->env);
4521}
4522
cf965d24
AZ		 4523static const struct omap_map_s {
4524 target_phys_addr_t phys_dsp;
4525 target_phys_addr_t phys_mpu;
4526 uint32_t size;
4527 const char *name;
4528} omap15xx_dsp_mm[] = {
4529 /* Strobe 0 */
4530 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4531 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4532 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4533 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4534 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4535 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4536 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4537 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4538 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4539 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4540 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4541 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4542 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4543 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4544 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4545 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4546 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4547 /* Strobe 1 */
4548 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4549
4550 { 0 }
4551};
4552
4553static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4554{
4555 int io;
4556
4557 for (; map->phys_dsp; map ++) {
4558 io = cpu_get_physical_page_desc(map->phys_mpu);
4559
4560 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4561 }
4562}
4563
827df9f3 4564void omap_mpu_wakeup(void *opaque, int irq, int req)
c3d2689d
AZ		 4565{
4566 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4567
fe71e81a
AZ		 4568 if (mpu->env->halted)
4569 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
c3d2689d
AZ		 4570}
4571
827df9f3 4572static const struct dma_irq_map omap1_dma_irq_map[] = {
089b7c0a
AZ		 4573 { 0, OMAP_INT_DMA_CH0_6 },
4574 { 0, OMAP_INT_DMA_CH1_7 },
4575 { 0, OMAP_INT_DMA_CH2_8 },
4576 { 0, OMAP_INT_DMA_CH3 },
4577 { 0, OMAP_INT_DMA_CH4 },
4578 { 0, OMAP_INT_DMA_CH5 },
4579 { 1, OMAP_INT_1610_DMA_CH6 },
4580 { 1, OMAP_INT_1610_DMA_CH7 },
4581 { 1, OMAP_INT_1610_DMA_CH8 },
4582 { 1, OMAP_INT_1610_DMA_CH9 },
4583 { 1, OMAP_INT_1610_DMA_CH10 },
4584 { 1, OMAP_INT_1610_DMA_CH11 },
4585 { 1, OMAP_INT_1610_DMA_CH12 },
4586 { 1, OMAP_INT_1610_DMA_CH13 },
4587 { 1, OMAP_INT_1610_DMA_CH14 },
4588 { 1, OMAP_INT_1610_DMA_CH15 }
4589};
4590
b4e3104b
AZ		 4591/* DMA ports for OMAP1 */
4592static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
4593 target_phys_addr_t addr)
4594{
4595 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
4596}
4597
4598static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
4599 target_phys_addr_t addr)
4600{
4601 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
4602}
4603
4604static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
4605 target_phys_addr_t addr)
4606{
4607 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
4608}
4609
4610static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
4611 target_phys_addr_t addr)
4612{
4613 return addr >= 0xfffb0000 && addr < 0xffff0000;
4614}
4615
4616static int omap_validate_local_addr(struct omap_mpu_state_s *s,
4617 target_phys_addr_t addr)
4618{
4619 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
4620}
4621
4622static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
4623 target_phys_addr_t addr)
4624{
4625 return addr >= 0xe1010000 && addr < 0xe1020004;
4626}
4627
c3d2689d
AZ		 4628struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4629 DisplayState *ds, const char *core)
4630{
089b7c0a 4631 int i;
c3d2689d
AZ		 4632 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4633 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4634 ram_addr_t imif_base, emiff_base;
106627d0 4635 qemu_irq *cpu_irq;
089b7c0a 4636 qemu_irq dma_irqs[6];
9d413d1d 4637 int sdindex;
106627d0 4638
aaed909a
FB		 4639 if (!core)
4640 core = "ti925t";
c3d2689d
AZ		 4641
4642 /* Core */
4643 s->mpu_model = omap310;
aaed909a
FB		 4644 s->env = cpu_init(core);
4645 if (!s->env) {
4646 fprintf(stderr, "Unable to find CPU definition\n");
4647 exit(1);
4648 }
c3d2689d
AZ		 4649 s->sdram_size = sdram_size;
4650 s->sram_size = OMAP15XX_SRAM_SIZE;
4651
fe71e81a
AZ		 4652 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4653
c3d2689d
AZ		 4654 /* Clocks */
4655 omap_clk_init(s);
4656
4657 /* Memory-mapped stuff */
4658 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4659 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4660 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4661 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4662
4663 omap_clkm_init(0xfffece00, 0xe1008000, s);
4664
106627d0 4665 cpu_irq = arm_pic_init_cpu(s->env);
827df9f3 4666 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
106627d0 4667 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
c3d2689d 4668 omap_findclk(s, "arminth_ck"));
827df9f3 4669 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
106627d0 4670 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
c3d2689d 4671 omap_findclk(s, "arminth_ck"));
c3d2689d 4672
089b7c0a 4673 for (i = 0; i < 6; i ++)
827df9f3
AZ		 4674 dma_irqs[i] =
4675 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
089b7c0a
AZ		 4676 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
4677 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
4678
c3d2689d
AZ		 4679 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4680 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4681 s->port[imif ].addr_valid = omap_validate_imif_addr;
4682 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4683 s->port[local ].addr_valid = omap_validate_local_addr;
4684 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4685
4686 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4687 s->irq[0][OMAP_INT_TIMER1],
4688 omap_findclk(s, "mputim_ck"));
4689 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4690 s->irq[0][OMAP_INT_TIMER2],
4691 omap_findclk(s, "mputim_ck"));
4692 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4693 s->irq[0][OMAP_INT_TIMER3],
4694 omap_findclk(s, "mputim_ck"));
4695
4696 s->wdt = omap_wd_timer_init(0xfffec800,
4697 s->irq[0][OMAP_INT_WD_TIMER],
4698 omap_findclk(s, "armwdt_ck"));
4699
4700 s->os_timer = omap_os_timer_init(0xfffb9000,
4701 s->irq[1][OMAP_INT_OS_TIMER],
4702 omap_findclk(s, "clk32-kHz"));
4703
4704 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
b4e3104b 4705 omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base,
c3d2689d
AZ		 4706 omap_findclk(s, "lcd_ck"));
4707
4708 omap_ulpd_pm_init(0xfffe0800, s);
4709 omap_pin_cfg_init(0xfffe1000, s);
4710 omap_id_init(s);
4711
4712 omap_mpui_init(0xfffec900, s);
4713
4714 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4715 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4716 omap_findclk(s, "tipb_ck"));
4717 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4718 s->irq[0][OMAP_INT_BRIDGE_PUB],
4719 omap_findclk(s, "tipb_ck"));
4720
4721 omap_tcmi_init(0xfffecc00, s);
4722
d951f6ff 4723 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
c3d2689d 4724 omap_findclk(s, "uart1_ck"),
827df9f3
AZ		 4725 omap_findclk(s, "uart1_ck"),
4726 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
c3d2689d 4727 serial_hds[0]);
d951f6ff 4728 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
c3d2689d 4729 omap_findclk(s, "uart2_ck"),
827df9f3
AZ		 4730 omap_findclk(s, "uart2_ck"),
4731 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
c3d2689d 4732 serial_hds[0] ? serial_hds[1] : 0);
d951f6ff 4733 s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
c3d2689d 4734 omap_findclk(s, "uart3_ck"),
827df9f3
AZ		 4735 omap_findclk(s, "uart3_ck"),
4736 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
c3d2689d
AZ		 4737 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4738
4739 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4740 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4741 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4742
9d413d1d
AZ		 4743 sdindex = drive_get_index(IF_SD, 0, 0);
4744 if (sdindex == -1) {
e4bcb14c
TS		 4745 fprintf(stderr, "qemu: missing SecureDigital device\n");
4746 exit(1);
4747 }
9d413d1d
AZ		 4748 s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
4749 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
4750 omap_findclk(s, "mmc_ck"));
b30bb3a2 4751
fe71e81a
AZ		 4752 s->mpuio = omap_mpuio_init(0xfffb5000,
4753 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4754 s->wakeup, omap_findclk(s, "clk32-kHz"));
4755
3efda49d 4756 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
66450b15 4757 omap_findclk(s, "arm_gpio_ck"));
64330148 4758
d951f6ff
AZ		 4759 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4760 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4761
d8f699cb
AZ		 4762 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4763 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
66450b15 4764
827df9f3 4765 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4a2c8ac2
AZ		 4766 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4767
5c1c390f
AZ		 4768 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4769 omap_findclk(s, "clk32-kHz"));
02645926 4770
d8f699cb
AZ		 4771 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4772 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4773 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4774 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4775 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4776 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4777
f9d43072
AZ		 4778 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
4779 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
4780
02645926 4781 /* Register mappings not currenlty implemented:
02645926
AZ		 4782 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4783 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4784 * USB W2FC fffb4000 - fffb47ff
4785 * Camera Interface fffb6800 - fffb6fff
02645926
AZ		 4786 * USB Host fffba000 - fffba7ff
4787 * FAC fffba800 - fffbafff
4788 * HDQ/1-Wire fffbc000 - fffbc7ff
b854bc19 4789 * TIPB switches fffbc800 - fffbcfff
02645926
AZ		 4790 * Mailbox fffcf000 - fffcf7ff
4791 * Local bus IF fffec100 - fffec1ff
4792 * Local bus MMU fffec200 - fffec2ff
4793 * DSP MMU fffed200 - fffed2ff
4794 */
4795
cf965d24 4796 omap_setup_dsp_mapping(omap15xx_dsp_mm);
f9d43072 4797 omap_setup_mpui_io(s);
cf965d24 4798
827df9f3 4799 qemu_register_reset(omap1_mpu_reset, s);
c3d2689d
AZ		 4800
4801 return s;
4802}
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