[qemu.git] / hw / sh_intc.h

#ifndef __SH_INTC_H__
#define __SH_INTC_H__

typedef unsigned char intc_enum;

struct intc_vect {
    intc_enum enum_id;
    unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }

struct intc_group {
    intc_enum enum_id;
    intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }

struct intc_mask_reg {
    unsigned long set_reg, clr_reg, reg_width;
    intc_enum enum_ids[32];
    unsigned long value;
};

struct intc_prio_reg {
    unsigned long set_reg, clr_reg, reg_width, field_width;
    intc_enum enum_ids[16];
    unsigned long value;
};

#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)

struct intc_source {
    unsigned short vect;
    intc_enum next_enum_id;

    int asserted; /* emulates the interrupt signal line from device to intc */
    int enable_count;
    int enable_max;
    int pending; /* emulates the result of signal and masking */
    struct intc_desc *parent;
};

struct intc_desc {
    struct intc_source *sources;
    int nr_sources;
    struct intc_mask_reg *mask_regs;
    int nr_mask_regs;
    struct intc_prio_reg *prio_regs;
    int nr_prio_regs;

    int iomemtype;
    int pending; /* number of interrupt sources that has pending set */
};

int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
void sh_intc_toggle_source(struct intc_source *source,
			   int enable_adj, int assert_adj);

void sh_intc_register_sources(struct intc_desc *desc,
			      struct intc_vect *vectors,
			      int nr_vectors,
			      struct intc_group *groups,
			      int nr_groups);

int sh_intc_init(struct intc_desc *desc,
		 int nr_sources,
		 struct intc_mask_reg *mask_regs,
		 int nr_mask_regs,
		 struct intc_prio_reg *prio_regs,
		 int nr_prio_regs);

#endif /* __SH_INTC_H__ */
Commit	Line	Data
80f515e6 AZ	1	#ifndef __SH_INTC_H__
	2	#define __SH_INTC_H__
	3
	4	typedef unsigned char intc_enum;
	5
	6	struct intc_vect {
	7	intc_enum enum_id;
	8	unsigned short vect;
	9	};
	10
	11	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	12
	13	struct intc_group {
	14	intc_enum enum_id;
	15	intc_enum enum_ids[32];
	16	};
	17
	18	#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
	19
	20	struct intc_mask_reg {
	21	unsigned long set_reg, clr_reg, reg_width;
	22	intc_enum enum_ids[32];
	23	unsigned long value;
	24	};
	25
	26	struct intc_prio_reg {
	27	unsigned long set_reg, clr_reg, reg_width, field_width;
	28	intc_enum enum_ids[16];
	29	unsigned long value;
	30	};
	31
	32	#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
	33
	34	struct intc_source {
	35	unsigned short vect;
	36	intc_enum next_enum_id;
	37
e96e2044	38	int asserted; /* emulates the interrupt signal line from device to intc */
80f515e6 AZ	39	int enable_count;
80f515e6 AZ	40	int enable_max;
e96e2044 TS	41	int pending; /* emulates the result of signal and masking */
e96e2044 TS	42	struct intc_desc *parent;
80f515e6 AZ	43	};
	44
	45	struct intc_desc {
	46	struct intc_source *sources;
	47	int nr_sources;
	48	struct intc_mask_reg *mask_regs;
	49	int nr_mask_regs;
	50	struct intc_prio_reg *prio_regs;
	51	int nr_prio_regs;
	52
	53	int iomemtype;
e96e2044	54	int pending; /* number of interrupt sources that has pending set */
80f515e6 AZ	55	};
80f515e6 AZ	56
e96e2044	57	int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
80f515e6	58	struct intc_source sh_intc_source(struct intc_desc desc, intc_enum id);
e96e2044 TS	59	void sh_intc_toggle_source(struct intc_source *source,
e96e2044 TS	60	int enable_adj, int assert_adj);
80f515e6 AZ	61
	62	void sh_intc_register_sources(struct intc_desc *desc,
	63	struct intc_vect *vectors,
	64	int nr_vectors,
	65	struct intc_group *groups,
	66	int nr_groups);
	67
	68	int sh_intc_init(struct intc_desc *desc,
	69	int nr_sources,
	70	struct intc_mask_reg *mask_regs,
	71	int nr_mask_regs,
	72	struct intc_prio_reg *prio_regs,
	73	int nr_prio_regs);
	74
	75	#endif /* __SH_INTC_H__ */