[qemu.git] / hw / mst_fpga.c

/*
 * PXA270-based Intel Mainstone platforms.
 * FPGA driver
 *
 * Copyright (c) 2007 by Armin Kuster <[email protected]> or
 *                                    <[email protected]>
 *
 * This code is licensed under the GNU GPL v2.
 */
#include "hw.h"
#include "mainstone.h"

/* Mainstone FPGA for extern irqs */
#define FPGA_GPIO_PIN	0
#define MST_NUM_IRQS	16
#define MST_LEDDAT1		0x10
#define MST_LEDDAT2		0x14
#define MST_LEDCTRL		0x40
#define MST_GPSWR		0x60
#define MST_MSCWR1		0x80
#define MST_MSCWR2		0x84
#define MST_MSCWR3		0x88
#define MST_MSCRD		0x90
#define MST_INTMSKENA	0xc0
#define MST_INTSETCLR	0xd0
#define MST_PCMCIA0		0xe0
#define MST_PCMCIA1		0xe4

typedef struct mst_irq_state{
	qemu_irq parent;
	qemu_irq *pins;

	uint32_t prev_level;
	uint32_t leddat1;
	uint32_t leddat2;
	uint32_t ledctrl;
	uint32_t gpswr;
	uint32_t mscwr1;
	uint32_t mscwr2;
	uint32_t mscwr3;
	uint32_t mscrd;
	uint32_t intmskena;
	uint32_t intsetclr;
	uint32_t pcmcia0;
	uint32_t pcmcia1;
}mst_irq_state;

static void
mst_fpga_update_gpio(mst_irq_state *s)
{
	uint32_t level, diff;
	int bit;
	level = s->prev_level ^ s->intsetclr;

	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
		bit = ffs(diff) - 1;
		qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
	}
	s->prev_level = level;
}

static void
mst_fpga_set_irq(void *opaque, int irq, int level)
{
	mst_irq_state *s = (mst_irq_state *)opaque;

	if (level)
		s->prev_level |= 1u << irq;
	else
		s->prev_level &= ~(1u << irq);

	if(s->intmskena & (1u << irq)) {
		s->intsetclr = 1u << irq;
		qemu_set_irq(s->parent, level);
	}
}


static uint32_t
mst_fpga_readb(void *opaque, target_phys_addr_t addr)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	switch (addr) {
	case MST_LEDDAT1:
		return s->leddat1;
	case MST_LEDDAT2:
		return s->leddat2;
	case MST_LEDCTRL:
		return s->ledctrl;
	case MST_GPSWR:
		return s->gpswr;
	case MST_MSCWR1:
		return s->mscwr1;
	case MST_MSCWR2:
		return s->mscwr2;
	case MST_MSCWR3:
		return s->mscwr3;
	case MST_MSCRD:
		return s->mscrd;
	case MST_INTMSKENA:
		return s->intmskena;
	case MST_INTSETCLR:
		return s->intsetclr;
	case MST_PCMCIA0:
		return s->pcmcia0;
	case MST_PCMCIA1:
		return s->pcmcia1;
	default:
		printf("Mainstone - mst_fpga_readb: Bad register offset "
			"0x" TARGET_FMT_plx " \n", addr);
	}
	return 0;
}

static void
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
	mst_irq_state *s = (mst_irq_state *) opaque;
	value &= 0xffffffff;

	switch (addr) {
	case MST_LEDDAT1:
		s->leddat1 = value;
		break;
	case MST_LEDDAT2:
		s->leddat2 = value;
		break;
	case MST_LEDCTRL:
		s->ledctrl = value;
		break;
	case MST_GPSWR:
		s->gpswr = value;
		break;
	case MST_MSCWR1:
		s->mscwr1 = value;
		break;
	case MST_MSCWR2:
		s->mscwr2 = value;
		break;
	case MST_MSCWR3:
		s->mscwr3 = value;
		break;
	case MST_MSCRD:
		s->mscrd =  value;
		break;
	case MST_INTMSKENA:	/* Mask interupt */
		s->intmskena = (value & 0xFEEFF);
		mst_fpga_update_gpio(s);
		break;
	case MST_INTSETCLR:	/* clear or set interrupt */
		s->intsetclr = (value & 0xFEEFF);
		break;
	case MST_PCMCIA0:
		s->pcmcia0 = value;
		break;
	case MST_PCMCIA1:
		s->pcmcia1 = value;
		break;
	default:
		printf("Mainstone - mst_fpga_writeb: Bad register offset "
			"0x" TARGET_FMT_plx " \n", addr);
	}
}

static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
	mst_fpga_readb,
	mst_fpga_readb,
	mst_fpga_readb,
};
static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
	mst_fpga_writeb,
	mst_fpga_writeb,
	mst_fpga_writeb,
};

static void
mst_fpga_save(QEMUFile *f, void *opaque)
{
	struct mst_irq_state *s = (mst_irq_state *) opaque;

	qemu_put_be32s(f, &s->prev_level);
	qemu_put_be32s(f, &s->leddat1);
	qemu_put_be32s(f, &s->leddat2);
	qemu_put_be32s(f, &s->ledctrl);
	qemu_put_be32s(f, &s->gpswr);
	qemu_put_be32s(f, &s->mscwr1);
	qemu_put_be32s(f, &s->mscwr2);
	qemu_put_be32s(f, &s->mscwr3);
	qemu_put_be32s(f, &s->mscrd);
	qemu_put_be32s(f, &s->intmskena);
	qemu_put_be32s(f, &s->intsetclr);
	qemu_put_be32s(f, &s->pcmcia0);
	qemu_put_be32s(f, &s->pcmcia1);
}

static int
mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	qemu_get_be32s(f, &s->prev_level);
	qemu_get_be32s(f, &s->leddat1);
	qemu_get_be32s(f, &s->leddat2);
	qemu_get_be32s(f, &s->ledctrl);
	qemu_get_be32s(f, &s->gpswr);
	qemu_get_be32s(f, &s->mscwr1);
	qemu_get_be32s(f, &s->mscwr2);
	qemu_get_be32s(f, &s->mscwr3);
	qemu_get_be32s(f, &s->mscrd);
	qemu_get_be32s(f, &s->intmskena);
	qemu_get_be32s(f, &s->intsetclr);
	qemu_get_be32s(f, &s->pcmcia0);
	qemu_get_be32s(f, &s->pcmcia1);
	return 0;
}

qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)
{
	mst_irq_state *s;
	int iomemtype;
	qemu_irq *qi;

	s = (mst_irq_state  *)
		qemu_mallocz(sizeof(mst_irq_state));

	s->parent = irq;

	/* alloc the external 16 irqs */
	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
	s->pins = qi;

	iomemtype = cpu_register_io_memory(mst_fpga_readfn,
		mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
	cpu_register_physical_memory(base, 0x00100000, iomemtype);
	register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
                        mst_fpga_load, s);
	return qi;
}
Commit	Line	Data
7233b355 TS	1	/*
	2	* PXA270-based Intel Mainstone platforms.
	3	* FPGA driver
	4	*
	5	* Copyright (c) 2007 by Armin Kuster <[email protected]> or
	6	* <[email protected]>
	7	*
	8	* This code is licensed under the GNU GPL v2.
	9	*/
	10	#include "hw.h"
7233b355 TS	11	#include "mainstone.h"
	12
	13	/* Mainstone FPGA for extern irqs */
	14	#define FPGA_GPIO_PIN 0
	15	#define MST_NUM_IRQS 16
7233b355 TS	16	#define MST_LEDDAT1 0x10
	17	#define MST_LEDDAT2 0x14
	18	#define MST_LEDCTRL 0x40
	19	#define MST_GPSWR 0x60
	20	#define MST_MSCWR1 0x80
	21	#define MST_MSCWR2 0x84
	22	#define MST_MSCWR3 0x88
	23	#define MST_MSCRD 0x90
	24	#define MST_INTMSKENA 0xc0
	25	#define MST_INTSETCLR 0xd0
	26	#define MST_PCMCIA0 0xe0
	27	#define MST_PCMCIA1 0xe4
	28
	29	typedef struct mst_irq_state{
bb70651e	30	qemu_irq parent;
7233b355 TS	31	qemu_irq *pins;
	32
	33	uint32_t prev_level;
	34	uint32_t leddat1;
	35	uint32_t leddat2;
	36	uint32_t ledctrl;
	37	uint32_t gpswr;
	38	uint32_t mscwr1;
	39	uint32_t mscwr2;
	40	uint32_t mscwr3;
	41	uint32_t mscrd;
	42	uint32_t intmskena;
	43	uint32_t intsetclr;
	44	uint32_t pcmcia0;
	45	uint32_t pcmcia1;
	46	}mst_irq_state;
	47
	48	static void
	49	mst_fpga_update_gpio(mst_irq_state *s)
	50	{
	51	uint32_t level, diff;
	52	int bit;
	53	level = s->prev_level ^ s->intsetclr;
	54
	55	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
	56	bit = ffs(diff) - 1;
	57	qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
	58	}
	59	s->prev_level = level;
	60	}
	61
	62	static void
	63	mst_fpga_set_irq(void *opaque, int irq, int level)
	64	{
	65	mst_irq_state s = (mst_irq_state )opaque;
	66
	67	if (level)
	68	s->prev_level \|= 1u << irq;
	69	else
	70	s->prev_level &= ~(1u << irq);
	71
	72	if(s->intmskena & (1u << irq)) {
	73	s->intsetclr = 1u << irq;
bb70651e	74	qemu_set_irq(s->parent, level);
7233b355 TS	75	}
	76	}
	77
	78
	79	static uint32_t
c227f099	80	mst_fpga_readb(void *opaque, target_phys_addr_t addr)
7233b355 TS	81	{
7233b355 TS	82	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	83
	84	switch (addr) {
	85	case MST_LEDDAT1:
	86	return s->leddat1;
	87	case MST_LEDDAT2:
	88	return s->leddat2;
	89	case MST_LEDCTRL:
	90	return s->ledctrl;
	91	case MST_GPSWR:
	92	return s->gpswr;
	93	case MST_MSCWR1:
	94	return s->mscwr1;
	95	case MST_MSCWR2:
	96	return s->mscwr2;
	97	case MST_MSCWR3:
	98	return s->mscwr3;
	99	case MST_MSCRD:
	100	return s->mscrd;
	101	case MST_INTMSKENA:
	102	return s->intmskena;
	103	case MST_INTSETCLR:
	104	return s->intsetclr;
	105	case MST_PCMCIA0:
	106	return s->pcmcia0;
	107	case MST_PCMCIA1:
	108	return s->pcmcia1;
	109	default:
	110	printf("Mainstone - mst_fpga_readb: Bad register offset "
bb70651e	111	"0x" TARGET_FMT_plx " \n", addr);
7233b355 TS	112	}
	113	return 0;
	114	}
	115
	116	static void
c227f099	117	mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
7233b355 TS	118	{
7233b355 TS	119	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	120	value &= 0xffffffff;
	121
	122	switch (addr) {
	123	case MST_LEDDAT1:
	124	s->leddat1 = value;
	125	break;
	126	case MST_LEDDAT2:
	127	s->leddat2 = value;
	128	break;
	129	case MST_LEDCTRL:
	130	s->ledctrl = value;
	131	break;
	132	case MST_GPSWR:
	133	s->gpswr = value;
	134	break;
	135	case MST_MSCWR1:
	136	s->mscwr1 = value;
	137	break;
	138	case MST_MSCWR2:
	139	s->mscwr2 = value;
	140	break;
	141	case MST_MSCWR3:
	142	s->mscwr3 = value;
	143	break;
	144	case MST_MSCRD:
	145	s->mscrd = value;
	146	break;
	147	case MST_INTMSKENA: /* Mask interupt */
	148	s->intmskena = (value & 0xFEEFF);
	149	mst_fpga_update_gpio(s);
	150	break;
	151	case MST_INTSETCLR: /* clear or set interrupt */
	152	s->intsetclr = (value & 0xFEEFF);
	153	break;
	154	case MST_PCMCIA0:
	155	s->pcmcia0 = value;
	156	break;
	157	case MST_PCMCIA1:
	158	s->pcmcia1 = value;
	159	break;
	160	default:
	161	printf("Mainstone - mst_fpga_writeb: Bad register offset "
bb70651e	162	"0x" TARGET_FMT_plx " \n", addr);
7233b355 TS	163	}
	164	}
	165
d60efc6b	166	static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
7233b355 TS	167	mst_fpga_readb,
	168	mst_fpga_readb,
	169	mst_fpga_readb,
	170	};
d60efc6b	171	static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
7233b355 TS	172	mst_fpga_writeb,
	173	mst_fpga_writeb,
	174	mst_fpga_writeb,
	175	};
	176
	177	static void
	178	mst_fpga_save(QEMUFile f, void opaque)
	179	{
	180	struct mst_irq_state s = (mst_irq_state ) opaque;
	181
	182	qemu_put_be32s(f, &s->prev_level);
	183	qemu_put_be32s(f, &s->leddat1);
	184	qemu_put_be32s(f, &s->leddat2);
	185	qemu_put_be32s(f, &s->ledctrl);
	186	qemu_put_be32s(f, &s->gpswr);
	187	qemu_put_be32s(f, &s->mscwr1);
	188	qemu_put_be32s(f, &s->mscwr2);
	189	qemu_put_be32s(f, &s->mscwr3);
	190	qemu_put_be32s(f, &s->mscrd);
	191	qemu_put_be32s(f, &s->intmskena);
	192	qemu_put_be32s(f, &s->intsetclr);
	193	qemu_put_be32s(f, &s->pcmcia0);
	194	qemu_put_be32s(f, &s->pcmcia1);
	195	}
	196
	197	static int
	198	mst_fpga_load(QEMUFile f, void opaque, int version_id)
	199	{
	200	mst_irq_state s = (mst_irq_state ) opaque;
	201
	202	qemu_get_be32s(f, &s->prev_level);
	203	qemu_get_be32s(f, &s->leddat1);
	204	qemu_get_be32s(f, &s->leddat2);
	205	qemu_get_be32s(f, &s->ledctrl);
	206	qemu_get_be32s(f, &s->gpswr);
	207	qemu_get_be32s(f, &s->mscwr1);
	208	qemu_get_be32s(f, &s->mscwr2);
	209	qemu_get_be32s(f, &s->mscwr3);
	210	qemu_get_be32s(f, &s->mscrd);
	211	qemu_get_be32s(f, &s->intmskena);
	212	qemu_get_be32s(f, &s->intsetclr);
	213	qemu_get_be32s(f, &s->pcmcia0);
	214	qemu_get_be32s(f, &s->pcmcia1);
	215	return 0;
	216	}
	217
bb70651e	218	qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)
7233b355 TS	219	{
	220	mst_irq_state *s;
	221	int iomemtype;
	222	qemu_irq *qi;
	223
	224	s = (mst_irq_state *)
	225	qemu_mallocz(sizeof(mst_irq_state));
	226
bb70651e	227	s->parent = irq;
7233b355 TS	228
	229	/* alloc the external 16 irqs */
	230	qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
	231	s->pins = qi;
	232
1eed09cb	233	iomemtype = cpu_register_io_memory(mst_fpga_readfn,
2507c12a	234	mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
8da3ff18	235	cpu_register_physical_memory(base, 0x00100000, iomemtype);
0be71e32 AW	236	register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
0be71e32 AW	237	mst_fpga_load, s);
7233b355 TS	238	return qi;
7233b355 TS	239	}