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Commit | Line | Data |
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244ab90e AL |
1 | /* |
2 | * DMA helper functions | |
3 | * | |
4 | * Copyright (c) 2009 Red Hat | |
5 | * | |
6 | * This work is licensed under the terms of the GNU General Public License | |
7 | * (GNU GPL), version 2 or later. | |
8 | */ | |
9 | ||
4be74634 | 10 | #include "sysemu/block-backend.h" |
9c17d615 | 11 | #include "sysemu/dma.h" |
c57c4658 | 12 | #include "trace.h" |
1de7afc9 PB |
13 | #include "qemu/range.h" |
14 | #include "qemu/thread.h" | |
6a1751b7 | 15 | #include "qemu/main-loop.h" |
244ab90e | 16 | |
e5332e63 DG |
17 | /* #define DEBUG_IOMMU */ |
18 | ||
df32fd1c | 19 | int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) |
d86a77f8 | 20 | { |
df32fd1c | 21 | dma_barrier(as, DMA_DIRECTION_FROM_DEVICE); |
24addbc7 | 22 | |
d86a77f8 DG |
23 | #define FILLBUF_SIZE 512 |
24 | uint8_t fillbuf[FILLBUF_SIZE]; | |
25 | int l; | |
24addbc7 | 26 | bool error = false; |
d86a77f8 DG |
27 | |
28 | memset(fillbuf, c, FILLBUF_SIZE); | |
29 | while (len > 0) { | |
30 | l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; | |
5c9eb028 PM |
31 | error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, |
32 | fillbuf, l, true); | |
bc9b78de BH |
33 | len -= l; |
34 | addr += l; | |
d86a77f8 | 35 | } |
e5332e63 | 36 | |
24addbc7 | 37 | return error; |
d86a77f8 DG |
38 | } |
39 | ||
f487b677 PB |
40 | void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint, |
41 | AddressSpace *as) | |
244ab90e | 42 | { |
7267c094 | 43 | qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry)); |
244ab90e AL |
44 | qsg->nsg = 0; |
45 | qsg->nalloc = alloc_hint; | |
46 | qsg->size = 0; | |
df32fd1c | 47 | qsg->as = as; |
f487b677 PB |
48 | qsg->dev = dev; |
49 | object_ref(OBJECT(dev)); | |
244ab90e AL |
50 | } |
51 | ||
d3231181 | 52 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len) |
244ab90e AL |
53 | { |
54 | if (qsg->nsg == qsg->nalloc) { | |
55 | qsg->nalloc = 2 * qsg->nalloc + 1; | |
7267c094 | 56 | qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry)); |
244ab90e AL |
57 | } |
58 | qsg->sg[qsg->nsg].base = base; | |
59 | qsg->sg[qsg->nsg].len = len; | |
60 | qsg->size += len; | |
61 | ++qsg->nsg; | |
62 | } | |
63 | ||
64 | void qemu_sglist_destroy(QEMUSGList *qsg) | |
65 | { | |
f487b677 | 66 | object_unref(OBJECT(qsg->dev)); |
7267c094 | 67 | g_free(qsg->sg); |
ea8d82a1 | 68 | memset(qsg, 0, sizeof(*qsg)); |
244ab90e AL |
69 | } |
70 | ||
59a703eb | 71 | typedef struct { |
7c84b1b8 | 72 | BlockAIOCB common; |
4be74634 | 73 | BlockBackend *blk; |
7c84b1b8 | 74 | BlockAIOCB *acb; |
59a703eb AL |
75 | QEMUSGList *sg; |
76 | uint64_t sector_num; | |
43cf8ae6 | 77 | DMADirection dir; |
59a703eb | 78 | int sg_cur_index; |
d3231181 | 79 | dma_addr_t sg_cur_byte; |
59a703eb AL |
80 | QEMUIOVector iov; |
81 | QEMUBH *bh; | |
cb144ccb | 82 | DMAIOFunc *io_func; |
37b7842c | 83 | } DMAAIOCB; |
59a703eb | 84 | |
4be74634 | 85 | static void dma_blk_cb(void *opaque, int ret); |
59a703eb AL |
86 | |
87 | static void reschedule_dma(void *opaque) | |
88 | { | |
37b7842c | 89 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; |
59a703eb AL |
90 | |
91 | qemu_bh_delete(dbs->bh); | |
92 | dbs->bh = NULL; | |
4be74634 | 93 | dma_blk_cb(dbs, 0); |
59a703eb AL |
94 | } |
95 | ||
96 | static void continue_after_map_failure(void *opaque) | |
97 | { | |
37b7842c | 98 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; |
59a703eb AL |
99 | |
100 | dbs->bh = qemu_bh_new(reschedule_dma, dbs); | |
101 | qemu_bh_schedule(dbs->bh); | |
102 | } | |
103 | ||
4be74634 | 104 | static void dma_blk_unmap(DMAAIOCB *dbs) |
59a703eb | 105 | { |
59a703eb AL |
106 | int i; |
107 | ||
59a703eb | 108 | for (i = 0; i < dbs->iov.niov; ++i) { |
df32fd1c | 109 | dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base, |
c65bcef3 DG |
110 | dbs->iov.iov[i].iov_len, dbs->dir, |
111 | dbs->iov.iov[i].iov_len); | |
59a703eb | 112 | } |
c3adb5b9 PB |
113 | qemu_iovec_reset(&dbs->iov); |
114 | } | |
115 | ||
116 | static void dma_complete(DMAAIOCB *dbs, int ret) | |
117 | { | |
c57c4658 KW |
118 | trace_dma_complete(dbs, ret, dbs->common.cb); |
119 | ||
4be74634 | 120 | dma_blk_unmap(dbs); |
c3adb5b9 PB |
121 | if (dbs->common.cb) { |
122 | dbs->common.cb(dbs->common.opaque, ret); | |
123 | } | |
124 | qemu_iovec_destroy(&dbs->iov); | |
125 | if (dbs->bh) { | |
126 | qemu_bh_delete(dbs->bh); | |
127 | dbs->bh = NULL; | |
128 | } | |
8007429a | 129 | qemu_aio_unref(dbs); |
7403b14e AL |
130 | } |
131 | ||
4be74634 | 132 | static void dma_blk_cb(void *opaque, int ret) |
7403b14e AL |
133 | { |
134 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; | |
c65bcef3 | 135 | dma_addr_t cur_addr, cur_len; |
7403b14e AL |
136 | void *mem; |
137 | ||
4be74634 | 138 | trace_dma_blk_cb(dbs, ret); |
c57c4658 | 139 | |
7403b14e AL |
140 | dbs->acb = NULL; |
141 | dbs->sector_num += dbs->iov.size / 512; | |
59a703eb AL |
142 | |
143 | if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) { | |
c3adb5b9 | 144 | dma_complete(dbs, ret); |
59a703eb AL |
145 | return; |
146 | } | |
4be74634 | 147 | dma_blk_unmap(dbs); |
59a703eb AL |
148 | |
149 | while (dbs->sg_cur_index < dbs->sg->nsg) { | |
150 | cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte; | |
151 | cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte; | |
df32fd1c | 152 | mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir); |
59a703eb AL |
153 | if (!mem) |
154 | break; | |
155 | qemu_iovec_add(&dbs->iov, mem, cur_len); | |
156 | dbs->sg_cur_byte += cur_len; | |
157 | if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) { | |
158 | dbs->sg_cur_byte = 0; | |
159 | ++dbs->sg_cur_index; | |
160 | } | |
161 | } | |
162 | ||
163 | if (dbs->iov.size == 0) { | |
c57c4658 | 164 | trace_dma_map_wait(dbs); |
59a703eb AL |
165 | cpu_register_map_client(dbs, continue_after_map_failure); |
166 | return; | |
167 | } | |
168 | ||
58f423fb KW |
169 | if (dbs->iov.size & ~BDRV_SECTOR_MASK) { |
170 | qemu_iovec_discard_back(&dbs->iov, dbs->iov.size & ~BDRV_SECTOR_MASK); | |
171 | } | |
172 | ||
4be74634 MA |
173 | dbs->acb = dbs->io_func(dbs->blk, dbs->sector_num, &dbs->iov, |
174 | dbs->iov.size / 512, dma_blk_cb, dbs); | |
6bee44ea | 175 | assert(dbs->acb); |
59a703eb AL |
176 | } |
177 | ||
7c84b1b8 | 178 | static void dma_aio_cancel(BlockAIOCB *acb) |
c16b5a2c CH |
179 | { |
180 | DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common); | |
181 | ||
c57c4658 KW |
182 | trace_dma_aio_cancel(dbs); |
183 | ||
c16b5a2c | 184 | if (dbs->acb) { |
4be74634 | 185 | blk_aio_cancel_async(dbs->acb); |
c16b5a2c CH |
186 | } |
187 | } | |
188 | ||
9bb9da46 | 189 | |
d7331bed | 190 | static const AIOCBInfo dma_aiocb_info = { |
c16b5a2c | 191 | .aiocb_size = sizeof(DMAAIOCB), |
9bb9da46 | 192 | .cancel_async = dma_aio_cancel, |
c16b5a2c CH |
193 | }; |
194 | ||
4be74634 MA |
195 | BlockAIOCB *dma_blk_io( |
196 | BlockBackend *blk, QEMUSGList *sg, uint64_t sector_num, | |
097310b5 | 197 | DMAIOFunc *io_func, BlockCompletionFunc *cb, |
43cf8ae6 | 198 | void *opaque, DMADirection dir) |
59a703eb | 199 | { |
4be74634 | 200 | DMAAIOCB *dbs = blk_aio_get(&dma_aiocb_info, blk, cb, opaque); |
59a703eb | 201 | |
4be74634 | 202 | trace_dma_blk_io(dbs, blk, sector_num, (dir == DMA_DIRECTION_TO_DEVICE)); |
c57c4658 | 203 | |
37b7842c | 204 | dbs->acb = NULL; |
4be74634 | 205 | dbs->blk = blk; |
59a703eb AL |
206 | dbs->sg = sg; |
207 | dbs->sector_num = sector_num; | |
208 | dbs->sg_cur_index = 0; | |
209 | dbs->sg_cur_byte = 0; | |
43cf8ae6 | 210 | dbs->dir = dir; |
cb144ccb | 211 | dbs->io_func = io_func; |
59a703eb AL |
212 | dbs->bh = NULL; |
213 | qemu_iovec_init(&dbs->iov, sg->nsg); | |
4be74634 | 214 | dma_blk_cb(dbs, 0); |
37b7842c | 215 | return &dbs->common; |
59a703eb AL |
216 | } |
217 | ||
218 | ||
4be74634 MA |
219 | BlockAIOCB *dma_blk_read(BlockBackend *blk, |
220 | QEMUSGList *sg, uint64_t sector, | |
221 | void (*cb)(void *opaque, int ret), void *opaque) | |
59a703eb | 222 | { |
4be74634 MA |
223 | return dma_blk_io(blk, sg, sector, blk_aio_readv, cb, opaque, |
224 | DMA_DIRECTION_FROM_DEVICE); | |
59a703eb AL |
225 | } |
226 | ||
4be74634 MA |
227 | BlockAIOCB *dma_blk_write(BlockBackend *blk, |
228 | QEMUSGList *sg, uint64_t sector, | |
229 | void (*cb)(void *opaque, int ret), void *opaque) | |
59a703eb | 230 | { |
4be74634 MA |
231 | return dma_blk_io(blk, sg, sector, blk_aio_writev, cb, opaque, |
232 | DMA_DIRECTION_TO_DEVICE); | |
59a703eb | 233 | } |
8171ee35 PB |
234 | |
235 | ||
c65bcef3 DG |
236 | static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg, |
237 | DMADirection dir) | |
8171ee35 PB |
238 | { |
239 | uint64_t resid; | |
240 | int sg_cur_index; | |
241 | ||
242 | resid = sg->size; | |
243 | sg_cur_index = 0; | |
244 | len = MIN(len, resid); | |
245 | while (len > 0) { | |
246 | ScatterGatherEntry entry = sg->sg[sg_cur_index++]; | |
247 | int32_t xfer = MIN(len, entry.len); | |
df32fd1c | 248 | dma_memory_rw(sg->as, entry.base, ptr, xfer, dir); |
8171ee35 PB |
249 | ptr += xfer; |
250 | len -= xfer; | |
251 | resid -= xfer; | |
252 | } | |
253 | ||
254 | return resid; | |
255 | } | |
256 | ||
257 | uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg) | |
258 | { | |
c65bcef3 | 259 | return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE); |
8171ee35 PB |
260 | } |
261 | ||
262 | uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg) | |
263 | { | |
c65bcef3 | 264 | return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE); |
8171ee35 | 265 | } |
84a69356 | 266 | |
4be74634 | 267 | void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie, |
84a69356 PB |
268 | QEMUSGList *sg, enum BlockAcctType type) |
269 | { | |
4be74634 | 270 | block_acct_start(blk_get_stats(blk), cookie, sg->size, type); |
84a69356 | 271 | } |