[qemu.git] / target-xtensa / cpu.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H

#define ALIGNED_ONLY
#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA

#define CPUArchState struct CPUXtensaState

#include "config.h"
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"

#define TARGET_HAS_ICE 1

#define NB_MMU_MODES 4

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_PAGE_BITS 12

enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,
    XTENSA_OPTION_LOOP,
    XTENSA_OPTION_EXTENDED_L32R,
    XTENSA_OPTION_16_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL_HIGH,
    XTENSA_OPTION_32_BIT_IDIV,
    XTENSA_OPTION_MAC16,
    XTENSA_OPTION_MISC_OP_NSA,
    XTENSA_OPTION_MISC_OP_MINMAX,
    XTENSA_OPTION_MISC_OP_SEXT,
    XTENSA_OPTION_MISC_OP_CLAMPS,
    XTENSA_OPTION_COPROCESSOR,
    XTENSA_OPTION_BOOLEAN,
    XTENSA_OPTION_FP_COPROCESSOR,
    XTENSA_OPTION_MP_SYNCHRO,
    XTENSA_OPTION_CONDITIONAL_STORE,
    XTENSA_OPTION_ATOMCTL,

    /* Interrupts and exceptions */
    XTENSA_OPTION_EXCEPTION,
    XTENSA_OPTION_RELOCATABLE_VECTOR,
    XTENSA_OPTION_UNALIGNED_EXCEPTION,
    XTENSA_OPTION_INTERRUPT,
    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
    XTENSA_OPTION_TIMER_INTERRUPT,

    /* Local memory */
    XTENSA_OPTION_ICACHE,
    XTENSA_OPTION_ICACHE_TEST,
    XTENSA_OPTION_ICACHE_INDEX_LOCK,
    XTENSA_OPTION_DCACHE,
    XTENSA_OPTION_DCACHE_TEST,
    XTENSA_OPTION_DCACHE_INDEX_LOCK,
    XTENSA_OPTION_IRAM,
    XTENSA_OPTION_IROM,
    XTENSA_OPTION_DRAM,
    XTENSA_OPTION_DROM,
    XTENSA_OPTION_XLMI,
    XTENSA_OPTION_HW_ALIGNMENT,
    XTENSA_OPTION_MEMORY_ECC_PARITY,

    /* Memory protection and translation */
    XTENSA_OPTION_REGION_PROTECTION,
    XTENSA_OPTION_REGION_TRANSLATION,
    XTENSA_OPTION_MMU,
    XTENSA_OPTION_CACHEATTR,

    /* Other */
    XTENSA_OPTION_WINDOWED_REGISTER,
    XTENSA_OPTION_PROCESSOR_INTERFACE,
    XTENSA_OPTION_MISC_SR,
    XTENSA_OPTION_THREAD_POINTER,
    XTENSA_OPTION_PROCESSOR_ID,
    XTENSA_OPTION_DEBUG,
    XTENSA_OPTION_TRACE_PORT,
};

enum {
    THREADPTR = 231,
    FCR = 232,
    FSR = 233,
};

enum {
    LBEG = 0,
    LEND = 1,
    LCOUNT = 2,
    SAR = 3,
    BR = 4,
    LITBASE = 5,
    SCOMPARE1 = 12,
    ACCLO = 16,
    ACCHI = 17,
    MR = 32,
    WINDOW_BASE = 72,
    WINDOW_START = 73,
    PTEVADDR = 83,
    RASID = 90,
    ITLBCFG = 91,
    DTLBCFG = 92,
    IBREAKENABLE = 96,
    CACHEATTR = 98,
    ATOMCTL = 99,
    IBREAKA = 128,
    DBREAKA = 144,
    DBREAKC = 160,
    CONFIGID0 = 176,
    EPC1 = 177,
    DEPC = 192,
    EPS2 = 194,
    CONFIGID1 = 208,
    EXCSAVE1 = 209,
    CPENABLE = 224,
    INTSET = 226,
    INTCLEAR = 227,
    INTENABLE = 228,
    PS = 230,
    VECBASE = 231,
    EXCCAUSE = 232,
    DEBUGCAUSE = 233,
    CCOUNT = 234,
    PRID = 235,
    ICOUNT = 236,
    ICOUNTLEVEL = 237,
    EXCVADDR = 238,
    CCOMPARE = 240,
    MISC = 244,
};

#define PS_INTLEVEL 0xf
#define PS_INTLEVEL_SHIFT 0

#define PS_EXCM 0x10
#define PS_UM 0x20

#define PS_RING 0xc0
#define PS_RING_SHIFT 6

#define PS_OWB 0xf00
#define PS_OWB_SHIFT 8

#define PS_CALLINC 0x30000
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_LEN 2

#define PS_WOE 0x40000

#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8

#define DBREAKC_SB 0x80000000
#define DBREAKC_LB 0x40000000
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
#define DBREAKC_MASK 0x3f

#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
#define MAX_NNMI 1
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2

#define REGION_PAGE_MASK 0xe0000000

#define PAGE_CACHE_MASK    0x700
#define PAGE_CACHE_SHIFT   8
#define PAGE_CACHE_INVALID 0x000
#define PAGE_CACHE_BYPASS  0x100
#define PAGE_CACHE_WT      0x200
#define PAGE_CACHE_WB      0x400
#define PAGE_CACHE_ISOLATE 0x600

enum {
    /* Static vectors */
    EXC_RESET,
    EXC_MEMORY_ERROR,

    /* Dynamic vectors */
    EXC_WINDOW_OVERFLOW4,
    EXC_WINDOW_UNDERFLOW4,
    EXC_WINDOW_OVERFLOW8,
    EXC_WINDOW_UNDERFLOW8,
    EXC_WINDOW_OVERFLOW12,
    EXC_WINDOW_UNDERFLOW12,
    EXC_IRQ,
    EXC_KERNEL,
    EXC_USER,
    EXC_DOUBLE,
    EXC_DEBUG,
    EXC_MAX
};

enum {
    ILLEGAL_INSTRUCTION_CAUSE = 0,
    SYSCALL_CAUSE,
    INSTRUCTION_FETCH_ERROR_CAUSE,
    LOAD_STORE_ERROR_CAUSE,
    LEVEL1_INTERRUPT_CAUSE,
    ALLOCA_CAUSE,
    INTEGER_DIVIDE_BY_ZERO_CAUSE,
    PRIVILEGED_CAUSE = 8,
    LOAD_STORE_ALIGNMENT_CAUSE,

    INSTR_PIF_DATA_ERROR_CAUSE = 12,
    LOAD_STORE_PIF_DATA_ERROR_CAUSE,
    INSTR_PIF_ADDR_ERROR_CAUSE,
    LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

    INST_TLB_MISS_CAUSE,
    INST_TLB_MULTI_HIT_CAUSE,
    INST_FETCH_PRIVILEGE_CAUSE,
    INST_FETCH_PROHIBITED_CAUSE = 20,
    LOAD_STORE_TLB_MISS_CAUSE = 24,
    LOAD_STORE_TLB_MULTI_HIT_CAUSE,
    LOAD_STORE_PRIVILEGE_CAUSE,
    LOAD_PROHIBITED_CAUSE = 28,
    STORE_PROHIBITED_CAUSE,

    COPROCESSOR0_DISABLED = 32,
};

typedef enum {
    INTTYPE_LEVEL,
    INTTYPE_EDGE,
    INTTYPE_NMI,
    INTTYPE_SOFTWARE,
    INTTYPE_TIMER,
    INTTYPE_DEBUG,
    INTTYPE_WRITE_ERR,
    INTTYPE_MAX
} interrupt_type;

typedef struct xtensa_tlb_entry {
    uint32_t vaddr;
    uint32_t paddr;
    uint8_t asid;
    uint8_t attr;
    bool variable;
} xtensa_tlb_entry;

typedef struct xtensa_tlb {
    unsigned nways;
    const unsigned way_size[10];
    bool varway56;
    unsigned nrefillentries;
} xtensa_tlb;

typedef struct XtensaGdbReg {
    int targno;
    int type;
    int group;
} XtensaGdbReg;

typedef struct XtensaGdbRegmap {
    int num_regs;
    int num_core_regs;
    /* PC + a + ar + sr + ur */
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
} XtensaGdbRegmap;

typedef struct XtensaConfig {
    const char *name;
    uint64_t options;
    XtensaGdbRegmap gdb_regmap;
    unsigned nareg;
    int excm_level;
    int ndepc;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
    unsigned nlevel;
    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t inttype_mask[INTTYPE_MAX];
    struct {
        uint32_t level;
        interrupt_type inttype;
    } interrupt[MAX_NINTERRUPT];
    unsigned nccompare;
    uint32_t timerint[MAX_NCCOMPARE];
    unsigned nextint;
    unsigned extint[MAX_NINTERRUPT];

    unsigned debug_level;
    unsigned nibreak;
    unsigned ndbreak;

    uint32_t configid[2];

    uint32_t clock_freq_khz;

    xtensa_tlb itlb;
    xtensa_tlb dtlb;
} XtensaConfig;

typedef struct XtensaConfigList {
    const XtensaConfig *config;
    struct XtensaConfigList *next;
} XtensaConfigList;

typedef struct CPUXtensaState {
    const XtensaConfig *config;
    uint32_t regs[16];
    uint32_t pc;
    uint32_t sregs[256];
    uint32_t uregs[256];
    uint32_t phys_regs[MAX_NAREG];
    float32 fregs[16];
    float_status fp_status;

    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
    unsigned autorefill_idx;

    int pending_irq_level; /* level of last raised IRQ */
    void **irq_inputs;
    QEMUTimer *ccompare_timer;
    uint32_t wake_ccount;
    int64_t halt_clock;

    int exception_taken;

    /* Watchpoints for DBREAK registers */
    struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

    CPU_COMMON
} CPUXtensaState;

#include "cpu-qom.h"

#define cpu_exec cpu_xtensa_exec
#define cpu_gen_code cpu_xtensa_gen_code
#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list

#ifdef TARGET_WORDS_BIGENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
#else
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
#endif

XtensaCPU *cpu_xtensa_init(const char *cpu_model);

static inline CPUXtensaState *cpu_init(const char *cpu_model)
{
    XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUXtensaState *env);
int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
        uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
        uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
        xtensa_tlb_entry *entry, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
        uint32_t vaddr, int is_write, int mmu_idx,
        uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);


#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
#define XTENSA_OPTION_ALL (~(uint64_t)0)

static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
        uint64_t opt)
{
    return (config->options & opt) != 0;
}

static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
{
    return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}

static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
    int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
    if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
        level = env->config->excm_level;
    }
    return level;
}

static inline int xtensa_get_ring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline int xtensa_get_cring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
            (env->sregs[PS] & PS_EXCM) == 0) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
        bool dtlb, unsigned wi, unsigned ei)
{
    return dtlb ?
        env->dtlb[wi] + ei :
        env->itlb[wi] + ei;
}

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ring0
#define MMU_MODE1_SUFFIX _ring1
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3

static inline int cpu_mmu_index(CPUXtensaState *env)
{
    return xtensa_get_cring(env);
}

#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
#define XTENSA_TBFLAG_EXCEPTION 0x4000

static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
        target_ulong *cs_base, int *flags)
{
    CPUState *cs = CPU(xtensa_env_get_cpu(env));

    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
    *flags |= xtensa_get_ring(env);
    if (env->sregs[PS] & PS_EXCM) {
        *flags |= XTENSA_TBFLAG_EXCM;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
            (env->sregs[LITBASE] & 1)) {
        *flags |= XTENSA_TBFLAG_LITBASE;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
            *flags |= XTENSA_TBFLAG_DEBUG;
        }
        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
            *flags |= XTENSA_TBFLAG_ICOUNT;
        }
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
    }
    if (cs->singlestep_enabled && env->exception_taken) {
        *flags |= XTENSA_TBFLAG_EXCEPTION;
    }
}

#include "exec/cpu-all.h"
#include "exec/exec-all.h"

#endif
Commit	Line	Data
2328826b MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#ifndef CPU_XTENSA_H
	29	#define CPU_XTENSA_H
	30
d94f0a8e	31	#define ALIGNED_ONLY
2328826b MF	32	#define TARGET_LONG_BITS 32
	33	#define ELF_MACHINE EM_XTENSA
	34
9349b4f9	35	#define CPUArchState struct CPUXtensaState
2328826b MF	36
	37	#include "config.h"
	38	#include "qemu-common.h"
022c62cb	39	#include "exec/cpu-defs.h"
dd519cbe	40	#include "fpu/softfloat.h"
2328826b MF	41
	42	#define TARGET_HAS_ICE 1
	43
	44	#define NB_MMU_MODES 4
	45
	46	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	47	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	48	#define TARGET_PAGE_BITS 12
	49
dedc5eae MF	50	enum {
	51	/* Additional instructions */
	52	XTENSA_OPTION_CODE_DENSITY,
	53	XTENSA_OPTION_LOOP,
	54	XTENSA_OPTION_EXTENDED_L32R,
	55	XTENSA_OPTION_16_BIT_IMUL,
	56	XTENSA_OPTION_32_BIT_IMUL,
7f65f4b0	57	XTENSA_OPTION_32_BIT_IMUL_HIGH,
dedc5eae MF	58	XTENSA_OPTION_32_BIT_IDIV,
dedc5eae MF	59	XTENSA_OPTION_MAC16,
7f65f4b0 MF	60	XTENSA_OPTION_MISC_OP_NSA,
	61	XTENSA_OPTION_MISC_OP_MINMAX,
	62	XTENSA_OPTION_MISC_OP_SEXT,
	63	XTENSA_OPTION_MISC_OP_CLAMPS,
dedc5eae MF	64	XTENSA_OPTION_COPROCESSOR,
	65	XTENSA_OPTION_BOOLEAN,
	66	XTENSA_OPTION_FP_COPROCESSOR,
	67	XTENSA_OPTION_MP_SYNCHRO,
	68	XTENSA_OPTION_CONDITIONAL_STORE,
fcc803d1	69	XTENSA_OPTION_ATOMCTL,
dedc5eae MF	70
	71	/* Interrupts and exceptions */
	72	XTENSA_OPTION_EXCEPTION,
	73	XTENSA_OPTION_RELOCATABLE_VECTOR,
	74	XTENSA_OPTION_UNALIGNED_EXCEPTION,
	75	XTENSA_OPTION_INTERRUPT,
	76	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
	77	XTENSA_OPTION_TIMER_INTERRUPT,
	78
	79	/* Local memory */
	80	XTENSA_OPTION_ICACHE,
	81	XTENSA_OPTION_ICACHE_TEST,
	82	XTENSA_OPTION_ICACHE_INDEX_LOCK,
	83	XTENSA_OPTION_DCACHE,
	84	XTENSA_OPTION_DCACHE_TEST,
	85	XTENSA_OPTION_DCACHE_INDEX_LOCK,
	86	XTENSA_OPTION_IRAM,
	87	XTENSA_OPTION_IROM,
	88	XTENSA_OPTION_DRAM,
	89	XTENSA_OPTION_DROM,
	90	XTENSA_OPTION_XLMI,
	91	XTENSA_OPTION_HW_ALIGNMENT,
	92	XTENSA_OPTION_MEMORY_ECC_PARITY,
	93
	94	/* Memory protection and translation */
	95	XTENSA_OPTION_REGION_PROTECTION,
	96	XTENSA_OPTION_REGION_TRANSLATION,
	97	XTENSA_OPTION_MMU,
4e41d2f5	98	XTENSA_OPTION_CACHEATTR,
dedc5eae MF	99
	100	/* Other */
	101	XTENSA_OPTION_WINDOWED_REGISTER,
	102	XTENSA_OPTION_PROCESSOR_INTERFACE,
	103	XTENSA_OPTION_MISC_SR,
	104	XTENSA_OPTION_THREAD_POINTER,
	105	XTENSA_OPTION_PROCESSOR_ID,
	106	XTENSA_OPTION_DEBUG,
	107	XTENSA_OPTION_TRACE_PORT,
	108	};
	109
2af3da91 MF	110	enum {
	111	THREADPTR = 231,
	112	FCR = 232,
	113	FSR = 233,
	114	};
	115
3580ecad	116	enum {
797d780b MF	117	LBEG = 0,
	118	LEND = 1,
	119	LCOUNT = 2,
3580ecad	120	SAR = 3,
4dd85b6b	121	BR = 4,
6ad6dbf7	122	LITBASE = 5,
809377aa	123	SCOMPARE1 = 12,
6825b6c3 MF	124	ACCLO = 16,
	125	ACCHI = 17,
	126	MR = 32,
553e44f9 MF	127	WINDOW_BASE = 72,
553e44f9 MF	128	WINDOW_START = 73,
b67ea0cd MF	129	PTEVADDR = 83,
	130	RASID = 90,
	131	ITLBCFG = 91,
	132	DTLBCFG = 92,
e61dc8f7	133	IBREAKENABLE = 96,
4e41d2f5	134	CACHEATTR = 98,
fcc803d1	135	ATOMCTL = 99,
e61dc8f7	136	IBREAKA = 128,
f14c4b5f MF	137	DBREAKA = 144,
f14c4b5f MF	138	DBREAKC = 160,
604e1f9c	139	CONFIGID0 = 176,
40643d7c MF	140	EPC1 = 177,
40643d7c MF	141	DEPC = 192,
b994e91b	142	EPS2 = 194,
604e1f9c	143	CONFIGID1 = 208,
40643d7c	144	EXCSAVE1 = 209,
f3df4c04	145	CPENABLE = 224,
b994e91b MF	146	INTSET = 226,
	147	INTCLEAR = 227,
	148	INTENABLE = 228,
f0a548b9	149	PS = 230,
97836cee	150	VECBASE = 231,
40643d7c	151	EXCCAUSE = 232,
ab58c5b4	152	DEBUGCAUSE = 233,
b994e91b	153	CCOUNT = 234,
f3df4c04	154	PRID = 235,
35b5c044 MF	155	ICOUNT = 236,
35b5c044 MF	156	ICOUNTLEVEL = 237,
40643d7c	157	EXCVADDR = 238,
b994e91b	158	CCOMPARE = 240,
b7909d81	159	MISC = 244,
3580ecad MF	160	};
3580ecad MF	161
f0a548b9 MF	162	#define PS_INTLEVEL 0xf
	163	#define PS_INTLEVEL_SHIFT 0
	164
	165	#define PS_EXCM 0x10
	166	#define PS_UM 0x20
	167
	168	#define PS_RING 0xc0
	169	#define PS_RING_SHIFT 6
	170
	171	#define PS_OWB 0xf00
	172	#define PS_OWB_SHIFT 8
	173
	174	#define PS_CALLINC 0x30000
	175	#define PS_CALLINC_SHIFT 16
	176	#define PS_CALLINC_LEN 2
	177
	178	#define PS_WOE 0x40000
	179
ab58c5b4 MF	180	#define DEBUGCAUSE_IC 0x1
	181	#define DEBUGCAUSE_IB 0x2
	182	#define DEBUGCAUSE_DB 0x4
	183	#define DEBUGCAUSE_BI 0x8
	184	#define DEBUGCAUSE_BN 0x10
	185	#define DEBUGCAUSE_DI 0x20
	186	#define DEBUGCAUSE_DBNUM 0xf00
	187	#define DEBUGCAUSE_DBNUM_SHIFT 8
	188
f14c4b5f MF	189	#define DBREAKC_SB 0x80000000
	190	#define DBREAKC_LB 0x40000000
	191	#define DBREAKC_SB_LB (DBREAKC_SB \| DBREAKC_LB)
	192	#define DBREAKC_MASK 0x3f
	193
553e44f9	194	#define MAX_NAREG 64
b994e91b MF	195	#define MAX_NINTERRUPT 32
	196	#define MAX_NLEVEL 6
	197	#define MAX_NNMI 1
	198	#define MAX_NCCOMPARE 3
b67ea0cd	199	#define MAX_TLB_WAY_SIZE 8
f14c4b5f	200	#define MAX_NDBREAK 2
b67ea0cd MF	201
b67ea0cd MF	202	#define REGION_PAGE_MASK 0xe0000000
553e44f9	203
fcc803d1 MF	204	#define PAGE_CACHE_MASK 0x700
	205	#define PAGE_CACHE_SHIFT 8
	206	#define PAGE_CACHE_INVALID 0x000
	207	#define PAGE_CACHE_BYPASS 0x100
	208	#define PAGE_CACHE_WT 0x200
	209	#define PAGE_CACHE_WB 0x400
	210	#define PAGE_CACHE_ISOLATE 0x600
	211
40643d7c MF	212	enum {
	213	/* Static vectors */
	214	EXC_RESET,
	215	EXC_MEMORY_ERROR,
	216
	217	/* Dynamic vectors */
	218	EXC_WINDOW_OVERFLOW4,
	219	EXC_WINDOW_UNDERFLOW4,
	220	EXC_WINDOW_OVERFLOW8,
	221	EXC_WINDOW_UNDERFLOW8,
	222	EXC_WINDOW_OVERFLOW12,
	223	EXC_WINDOW_UNDERFLOW12,
	224	EXC_IRQ,
	225	EXC_KERNEL,
	226	EXC_USER,
	227	EXC_DOUBLE,
e61dc8f7	228	EXC_DEBUG,
40643d7c MF	229	EXC_MAX
	230	};
	231
	232	enum {
	233	ILLEGAL_INSTRUCTION_CAUSE = 0,
	234	SYSCALL_CAUSE,
	235	INSTRUCTION_FETCH_ERROR_CAUSE,
	236	LOAD_STORE_ERROR_CAUSE,
	237	LEVEL1_INTERRUPT_CAUSE,
	238	ALLOCA_CAUSE,
	239	INTEGER_DIVIDE_BY_ZERO_CAUSE,
	240	PRIVILEGED_CAUSE = 8,
	241	LOAD_STORE_ALIGNMENT_CAUSE,
	242
	243	INSTR_PIF_DATA_ERROR_CAUSE = 12,
	244	LOAD_STORE_PIF_DATA_ERROR_CAUSE,
	245	INSTR_PIF_ADDR_ERROR_CAUSE,
	246	LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
	247
	248	INST_TLB_MISS_CAUSE,
	249	INST_TLB_MULTI_HIT_CAUSE,
	250	INST_FETCH_PRIVILEGE_CAUSE,
	251	INST_FETCH_PROHIBITED_CAUSE = 20,
	252	LOAD_STORE_TLB_MISS_CAUSE = 24,
	253	LOAD_STORE_TLB_MULTI_HIT_CAUSE,
	254	LOAD_STORE_PRIVILEGE_CAUSE,
	255	LOAD_PROHIBITED_CAUSE = 28,
	256	STORE_PROHIBITED_CAUSE,
	257
	258	COPROCESSOR0_DISABLED = 32,
	259	};
	260
b994e91b MF	261	typedef enum {
	262	INTTYPE_LEVEL,
	263	INTTYPE_EDGE,
	264	INTTYPE_NMI,
	265	INTTYPE_SOFTWARE,
	266	INTTYPE_TIMER,
	267	INTTYPE_DEBUG,
	268	INTTYPE_WRITE_ERR,
	269	INTTYPE_MAX
	270	} interrupt_type;
	271
b67ea0cd MF	272	typedef struct xtensa_tlb_entry {
	273	uint32_t vaddr;
	274	uint32_t paddr;
	275	uint8_t asid;
	276	uint8_t attr;
	277	bool variable;
	278	} xtensa_tlb_entry;
	279
	280	typedef struct xtensa_tlb {
	281	unsigned nways;
	282	const unsigned way_size[10];
	283	bool varway56;
	284	unsigned nrefillentries;
	285	} xtensa_tlb;
	286
ccfcaba6 MF	287	typedef struct XtensaGdbReg {
	288	int targno;
	289	int type;
	290	int group;
	291	} XtensaGdbReg;
	292
	293	typedef struct XtensaGdbRegmap {
	294	int num_regs;
	295	int num_core_regs;
	296	/* PC + a + ar + sr + ur */
	297	XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
	298	} XtensaGdbRegmap;
	299
dedc5eae MF	300	typedef struct XtensaConfig {
	301	const char *name;
	302	uint64_t options;
ccfcaba6	303	XtensaGdbRegmap gdb_regmap;
553e44f9	304	unsigned nareg;
40643d7c MF	305	int excm_level;
40643d7c MF	306	int ndepc;
97836cee	307	uint32_t vecbase;
40643d7c	308	uint32_t exception_vector[EXC_MAX];
b994e91b MF	309	unsigned ninterrupt;
	310	unsigned nlevel;
	311	uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
	312	uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
	313	uint32_t inttype_mask[INTTYPE_MAX];
	314	struct {
	315	uint32_t level;
	316	interrupt_type inttype;
	317	} interrupt[MAX_NINTERRUPT];
	318	unsigned nccompare;
	319	uint32_t timerint[MAX_NCCOMPARE];
b8929a54 MF	320	unsigned nextint;
b8929a54 MF	321	unsigned extint[MAX_NINTERRUPT];
ab58c5b4 MF	322
	323	unsigned debug_level;
	324	unsigned nibreak;
	325	unsigned ndbreak;
	326
604e1f9c MF	327	uint32_t configid[2];
604e1f9c MF	328
b994e91b	329	uint32_t clock_freq_khz;
b67ea0cd MF	330
	331	xtensa_tlb itlb;
	332	xtensa_tlb dtlb;
dedc5eae MF	333	} XtensaConfig;
dedc5eae MF	334
ac8b7db4 MF	335	typedef struct XtensaConfigList {
	336	const XtensaConfig *config;
	337	struct XtensaConfigList *next;
	338	} XtensaConfigList;
	339
2328826b	340	typedef struct CPUXtensaState {
dedc5eae	341	const XtensaConfig *config;
2328826b MF	342	uint32_t regs[16];
	343	uint32_t pc;
	344	uint32_t sregs[256];
2af3da91	345	uint32_t uregs[256];
553e44f9	346	uint32_t phys_regs[MAX_NAREG];
dd519cbe MF	347	float32 fregs[16];
dd519cbe MF	348	float_status fp_status;
2328826b	349
b67ea0cd MF	350	xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
	351	xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
	352	unsigned autorefill_idx;
	353
b994e91b MF	354	int pending_irq_level; /* level of last raised IRQ */
	355	void **irq_inputs;
	356	QEMUTimer *ccompare_timer;
	357	uint32_t wake_ccount;
	358	int64_t halt_clock;
	359
40643d7c MF	360	int exception_taken;
40643d7c MF	361
f14c4b5f	362	/* Watchpoints for DBREAK registers */
ff4700b0	363	struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
f14c4b5f	364
2328826b MF	365	CPU_COMMON
	366	} CPUXtensaState;
	367
15be3171 AF	368	#include "cpu-qom.h"
15be3171 AF	369
2328826b MF	370	#define cpu_exec cpu_xtensa_exec
	371	#define cpu_gen_code cpu_xtensa_gen_code
	372	#define cpu_signal_handler cpu_xtensa_signal_handler
	373	#define cpu_list xtensa_cpu_list
	374
e38077ff MF	375	#ifdef TARGET_WORDS_BIGENDIAN
	376	#define XTENSA_DEFAULT_CPU_MODEL "fsf"
	377	#else
	378	#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
	379	#endif
	380
15be3171 AF	381	XtensaCPU cpu_xtensa_init(const char cpu_model);
	382
	383	static inline CPUXtensaState cpu_init(const char cpu_model)
	384	{
	385	XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
	386	if (cpu == NULL) {
	387	return NULL;
	388	}
	389	return &cpu->env;
	390	}
	391
2328826b	392	void xtensa_translate_init(void);
25733ead	393	void xtensa_breakpoint_handler(CPUXtensaState *env);
2328826b	394	int cpu_xtensa_exec(CPUXtensaState *s);
ac8b7db4	395	void xtensa_register_core(XtensaConfigList *node);
b994e91b	396	void check_interrupts(CPUXtensaState *s);
97129ac8 AF	397	void xtensa_irq_init(CPUXtensaState *env);
	398	void xtensa_get_extint(CPUXtensaState env, unsigned extint);
	399	void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
	400	void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
	401	void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
2328826b MF	402	int cpu_xtensa_signal_handler(int host_signum, void pinfo, void puc);
2328826b MF	403	void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
97129ac8 AF	404	void xtensa_sync_window_from_phys(CPUXtensaState *env);
	405	void xtensa_sync_phys_from_window(CPUXtensaState *env);
	406	uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
	407	void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
b67ea0cd	408	uint32_t vpn, uint32_t wi, uint32_t ei);
97129ac8	409	int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
b67ea0cd	410	uint32_t pwi, uint32_t pei, uint8_t *pring);
16bde77a MF	411	void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
	412	xtensa_tlb_entry *entry, bool dtlb,
	413	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
97129ac8	414	void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
b67ea0cd	415	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
ae4e7982	416	int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
b67ea0cd MF	417	uint32_t vaddr, int is_write, int mmu_idx,
b67ea0cd MF	418	uint32_t paddr, uint32_t page_size, unsigned *access);
5087a72c	419	void reset_mmu(CPUXtensaState *env);
97129ac8 AF	420	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUXtensaState env);
97129ac8 AF	421	void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
b67ea0cd	422
2328826b	423
dedc5eae	424	#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
fe0bd475	425	#define XTENSA_OPTION_ALL (~(uint64_t)0)
dedc5eae	426
b67ea0cd MF	427	static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
	428	uint64_t opt)
	429	{
	430	return (config->options & opt) != 0;
	431	}
	432
dedc5eae MF	433	static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
dedc5eae MF	434	{
b67ea0cd	435	return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
dedc5eae MF	436	}
dedc5eae MF	437
97129ac8	438	static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
40643d7c MF	439	{
	440	int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
	441	if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
	442	level = env->config->excm_level;
	443	}
	444	return level;
	445	}
	446
97129ac8	447	static inline int xtensa_get_ring(const CPUXtensaState *env)
f0a548b9 MF	448	{
	449	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
	450	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	451	} else {
	452	return 0;
	453	}
	454	}
	455
97129ac8	456	static inline int xtensa_get_cring(const CPUXtensaState *env)
f0a548b9 MF	457	{
	458	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
	459	(env->sregs[PS] & PS_EXCM) == 0) {
	460	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	461	} else {
	462	return 0;
	463	}
	464	}
	465
97129ac8	466	static inline xtensa_tlb_entry xtensa_tlb_get_entry(CPUXtensaState env,
b67ea0cd MF	467	bool dtlb, unsigned wi, unsigned ei)
	468	{
	469	return dtlb ?
	470	env->dtlb[wi] + ei :
	471	env->itlb[wi] + ei;
	472	}
	473
f0a548b9 MF	474	/* MMU modes definitions */
	475	#define MMU_MODE0_SUFFIX _ring0
	476	#define MMU_MODE1_SUFFIX _ring1
	477	#define MMU_MODE2_SUFFIX _ring2
	478	#define MMU_MODE3_SUFFIX _ring3
	479
97129ac8	480	static inline int cpu_mmu_index(CPUXtensaState *env)
2328826b	481	{
f0a548b9	482	return xtensa_get_cring(env);
2328826b MF	483	}
2328826b MF	484
f0a548b9 MF	485	#define XTENSA_TBFLAG_RING_MASK 0x3
f0a548b9 MF	486	#define XTENSA_TBFLAG_EXCM 0x4
6ad6dbf7	487	#define XTENSA_TBFLAG_LITBASE 0x8
e61dc8f7	488	#define XTENSA_TBFLAG_DEBUG 0x10
35b5c044	489	#define XTENSA_TBFLAG_ICOUNT 0x20
ef04a846 MF	490	#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
ef04a846 MF	491	#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
a00817cc	492	#define XTENSA_TBFLAG_EXCEPTION 0x4000
f0a548b9	493
97129ac8	494	static inline void cpu_get_tb_cpu_state(CPUXtensaState env, target_ulong pc,
2328826b MF	495	target_ulong cs_base, int flags)
2328826b MF	496	{
1cf5ccbc AF	497	CPUState *cs = CPU(xtensa_env_get_cpu(env));
1cf5ccbc AF	498
2328826b MF	499	*pc = env->pc;
	500	*cs_base = 0;
	501	*flags = 0;
f0a548b9 MF	502	*flags \|= xtensa_get_ring(env);
	503	if (env->sregs[PS] & PS_EXCM) {
	504	*flags \|= XTENSA_TBFLAG_EXCM;
	505	}
6ad6dbf7 MF	506	if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
	507	(env->sregs[LITBASE] & 1)) {
	508	*flags \|= XTENSA_TBFLAG_LITBASE;
	509	}
e61dc8f7 MF	510	if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
	511	if (xtensa_get_cintlevel(env) < env->config->debug_level) {
	512	*flags \|= XTENSA_TBFLAG_DEBUG;
	513	}
35b5c044 MF	514	if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
	515	*flags \|= XTENSA_TBFLAG_ICOUNT;
	516	}
e61dc8f7	517	}
ef04a846 MF	518	if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
	519	*flags \|= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
	520	}
1cf5ccbc	521	if (cs->singlestep_enabled && env->exception_taken) {
a00817cc MF	522	*flags \|= XTENSA_TBFLAG_EXCEPTION;
a00817cc MF	523	}
2328826b MF	524	}
2328826b MF	525
022c62cb PB	526	#include "exec/cpu-all.h"
022c62cb PB	527	#include "exec/exec-all.h"
2328826b	528
2328826b	529	#endif