[qemu.git] / hw / usb / hcd-ehci.h

/*
 * QEMU USB EHCI Emulation
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or(at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef HW_USB_EHCI_H
#define HW_USB_EHCI_H 1

#include "hw/hw.h"
#include "qemu/timer.h"
#include "hw/usb.h"
#include "monitor/monitor.h"
#include "trace.h"
#include "sysemu/dma.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"
#include "hw/sysbus.h"

#ifndef EHCI_DEBUG
#define EHCI_DEBUG   0
#endif

#if EHCI_DEBUG
#define DPRINTF printf
#else
#define DPRINTF(...)
#endif

#define MMIO_SIZE        0x1000
#define CAPA_SIZE        0x10

#define PORTSC               0x0044
#define PORTSC_BEGIN         PORTSC
#define PORTSC_END           (PORTSC + 4 * NB_PORTS)

#define NB_PORTS         6        /* Number of downstream ports */

typedef struct EHCIPacket EHCIPacket;
typedef struct EHCIQueue EHCIQueue;
typedef struct EHCIState EHCIState;

/*  EHCI spec version 1.0 Section 3.3
 */
typedef struct EHCIitd {
    uint32_t next;

    uint32_t transact[8];
#define ITD_XACT_ACTIVE          (1 << 31)
#define ITD_XACT_DBERROR         (1 << 30)
#define ITD_XACT_BABBLE          (1 << 29)
#define ITD_XACT_XACTERR         (1 << 28)
#define ITD_XACT_LENGTH_MASK     0x0fff0000
#define ITD_XACT_LENGTH_SH       16
#define ITD_XACT_IOC             (1 << 15)
#define ITD_XACT_PGSEL_MASK      0x00007000
#define ITD_XACT_PGSEL_SH        12
#define ITD_XACT_OFFSET_MASK     0x00000fff

    uint32_t bufptr[7];
#define ITD_BUFPTR_MASK          0xfffff000
#define ITD_BUFPTR_SH            12
#define ITD_BUFPTR_EP_MASK       0x00000f00
#define ITD_BUFPTR_EP_SH         8
#define ITD_BUFPTR_DEVADDR_MASK  0x0000007f
#define ITD_BUFPTR_DEVADDR_SH    0
#define ITD_BUFPTR_DIRECTION     (1 << 11)
#define ITD_BUFPTR_MAXPKT_MASK   0x000007ff
#define ITD_BUFPTR_MAXPKT_SH     0
#define ITD_BUFPTR_MULT_MASK     0x00000003
#define ITD_BUFPTR_MULT_SH       0
} EHCIitd;

/*  EHCI spec version 1.0 Section 3.4
 */
typedef struct EHCIsitd {
    uint32_t next;                  /* Standard next link pointer */
    uint32_t epchar;
#define SITD_EPCHAR_IO              (1 << 31)
#define SITD_EPCHAR_PORTNUM_MASK    0x7f000000
#define SITD_EPCHAR_PORTNUM_SH      24
#define SITD_EPCHAR_HUBADD_MASK     0x007f0000
#define SITD_EPCHAR_HUBADDR_SH      16
#define SITD_EPCHAR_EPNUM_MASK      0x00000f00
#define SITD_EPCHAR_EPNUM_SH        8
#define SITD_EPCHAR_DEVADDR_MASK    0x0000007f

    uint32_t uframe;
#define SITD_UFRAME_CMASK_MASK      0x0000ff00
#define SITD_UFRAME_CMASK_SH        8
#define SITD_UFRAME_SMASK_MASK      0x000000ff

    uint32_t results;
#define SITD_RESULTS_IOC              (1 << 31)
#define SITD_RESULTS_PGSEL            (1 << 30)
#define SITD_RESULTS_TBYTES_MASK      0x03ff0000
#define SITD_RESULTS_TYBYTES_SH       16
#define SITD_RESULTS_CPROGMASK_MASK   0x0000ff00
#define SITD_RESULTS_CPROGMASK_SH     8
#define SITD_RESULTS_ACTIVE           (1 << 7)
#define SITD_RESULTS_ERR              (1 << 6)
#define SITD_RESULTS_DBERR            (1 << 5)
#define SITD_RESULTS_BABBLE           (1 << 4)
#define SITD_RESULTS_XACTERR          (1 << 3)
#define SITD_RESULTS_MISSEDUF         (1 << 2)
#define SITD_RESULTS_SPLITXSTATE      (1 << 1)

    uint32_t bufptr[2];
#define SITD_BUFPTR_MASK              0xfffff000
#define SITD_BUFPTR_CURROFF_MASK      0x00000fff
#define SITD_BUFPTR_TPOS_MASK         0x00000018
#define SITD_BUFPTR_TPOS_SH           3
#define SITD_BUFPTR_TCNT_MASK         0x00000007

    uint32_t backptr;                 /* Standard next link pointer */
} EHCIsitd;

/*  EHCI spec version 1.0 Section 3.5
 */
typedef struct EHCIqtd {
    uint32_t next;                    /* Standard next link pointer */
    uint32_t altnext;                 /* Standard next link pointer */
    uint32_t token;
#define QTD_TOKEN_DTOGGLE             (1 << 31)
#define QTD_TOKEN_TBYTES_MASK         0x7fff0000
#define QTD_TOKEN_TBYTES_SH           16
#define QTD_TOKEN_IOC                 (1 << 15)
#define QTD_TOKEN_CPAGE_MASK          0x00007000
#define QTD_TOKEN_CPAGE_SH            12
#define QTD_TOKEN_CERR_MASK           0x00000c00
#define QTD_TOKEN_CERR_SH             10
#define QTD_TOKEN_PID_MASK            0x00000300
#define QTD_TOKEN_PID_SH              8
#define QTD_TOKEN_ACTIVE              (1 << 7)
#define QTD_TOKEN_HALT                (1 << 6)
#define QTD_TOKEN_DBERR               (1 << 5)
#define QTD_TOKEN_BABBLE              (1 << 4)
#define QTD_TOKEN_XACTERR             (1 << 3)
#define QTD_TOKEN_MISSEDUF            (1 << 2)
#define QTD_TOKEN_SPLITXSTATE         (1 << 1)
#define QTD_TOKEN_PING                (1 << 0)

    uint32_t bufptr[5];               /* Standard buffer pointer */
#define QTD_BUFPTR_MASK               0xfffff000
#define QTD_BUFPTR_SH                 12
} EHCIqtd;

/*  EHCI spec version 1.0 Section 3.6
 */
typedef struct EHCIqh {
    uint32_t next;                    /* Standard next link pointer */

    /* endpoint characteristics */
    uint32_t epchar;
#define QH_EPCHAR_RL_MASK             0xf0000000
#define QH_EPCHAR_RL_SH               28
#define QH_EPCHAR_C                   (1 << 27)
#define QH_EPCHAR_MPLEN_MASK          0x07FF0000
#define QH_EPCHAR_MPLEN_SH            16
#define QH_EPCHAR_H                   (1 << 15)
#define QH_EPCHAR_DTC                 (1 << 14)
#define QH_EPCHAR_EPS_MASK            0x00003000
#define QH_EPCHAR_EPS_SH              12
#define EHCI_QH_EPS_FULL              0
#define EHCI_QH_EPS_LOW               1
#define EHCI_QH_EPS_HIGH              2
#define EHCI_QH_EPS_RESERVED          3

#define QH_EPCHAR_EP_MASK             0x00000f00
#define QH_EPCHAR_EP_SH               8
#define QH_EPCHAR_I                   (1 << 7)
#define QH_EPCHAR_DEVADDR_MASK        0x0000007f
#define QH_EPCHAR_DEVADDR_SH          0

    /* endpoint capabilities */
    uint32_t epcap;
#define QH_EPCAP_MULT_MASK            0xc0000000
#define QH_EPCAP_MULT_SH              30
#define QH_EPCAP_PORTNUM_MASK         0x3f800000
#define QH_EPCAP_PORTNUM_SH           23
#define QH_EPCAP_HUBADDR_MASK         0x007f0000
#define QH_EPCAP_HUBADDR_SH           16
#define QH_EPCAP_CMASK_MASK           0x0000ff00
#define QH_EPCAP_CMASK_SH             8
#define QH_EPCAP_SMASK_MASK           0x000000ff
#define QH_EPCAP_SMASK_SH             0

    uint32_t current_qtd;             /* Standard next link pointer */
    uint32_t next_qtd;                /* Standard next link pointer */
    uint32_t altnext_qtd;
#define QH_ALTNEXT_NAKCNT_MASK        0x0000001e
#define QH_ALTNEXT_NAKCNT_SH          1

    uint32_t token;                   /* Same as QTD token */
    uint32_t bufptr[5];               /* Standard buffer pointer */
#define BUFPTR_CPROGMASK_MASK         0x000000ff
#define BUFPTR_FRAMETAG_MASK          0x0000001f
#define BUFPTR_SBYTES_MASK            0x00000fe0
#define BUFPTR_SBYTES_SH              5
} EHCIqh;

/*  EHCI spec version 1.0 Section 3.7
 */
typedef struct EHCIfstn {
    uint32_t next;                    /* Standard next link pointer */
    uint32_t backptr;                 /* Standard next link pointer */
} EHCIfstn;

enum async_state {
    EHCI_ASYNC_NONE = 0,
    EHCI_ASYNC_INITIALIZED,
    EHCI_ASYNC_INFLIGHT,
    EHCI_ASYNC_FINISHED,
};

struct EHCIPacket {
    EHCIQueue *queue;
    QTAILQ_ENTRY(EHCIPacket) next;

    EHCIqtd qtd;           /* copy of current QTD (being worked on) */
    uint32_t qtdaddr;      /* address QTD read from                 */

    USBPacket packet;
    QEMUSGList sgl;
    int pid;
    enum async_state async;
};

struct EHCIQueue {
    EHCIState *ehci;
    QTAILQ_ENTRY(EHCIQueue) next;
    uint32_t seen;
    uint64_t ts;
    int async;
    int transact_ctr;

    /* cached data from guest - needs to be flushed
     * when guest removes an entry (doorbell, handshake sequence)
     */
    EHCIqh qh;             /* copy of current QH (being worked on) */
    uint32_t qhaddr;       /* address QH read from                 */
    uint32_t qtdaddr;      /* address QTD read from                */
    int last_pid;          /* pid of last packet executed          */
    USBDevice *dev;
    QTAILQ_HEAD(pkts_head, EHCIPacket) packets;
};

typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;

struct EHCIState {
    USBBus bus;
    qemu_irq irq;
    MemoryRegion mem;
    DMAContext *dma;
    MemoryRegion mem_caps;
    MemoryRegion mem_opreg;
    MemoryRegion mem_ports;
    int companion_count;
    uint16_t capsbase;
    uint16_t opregbase;

    /* properties */
    uint32_t maxframes;

    /*
     *  EHCI spec version 1.0 Section 2.3
     *  Host Controller Operational Registers
     */
    uint8_t caps[CAPA_SIZE];
    union {
        uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)];
        struct {
            uint32_t usbcmd;
            uint32_t usbsts;
            uint32_t usbintr;
            uint32_t frindex;
            uint32_t ctrldssegment;
            uint32_t periodiclistbase;
            uint32_t asynclistaddr;
            uint32_t notused[9];
            uint32_t configflag;
        };
    };
    uint32_t portsc[NB_PORTS];

    /*
     *  Internal states, shadow registers, etc
     */
    QEMUTimer *frame_timer;
    QEMUBH *async_bh;
    uint32_t astate;         /* Current state in asynchronous schedule */
    uint32_t pstate;         /* Current state in periodic schedule     */
    USBPort ports[NB_PORTS];
    USBPort *companion_ports[NB_PORTS];
    uint32_t usbsts_pending;
    uint32_t usbsts_frindex;
    EHCIQueueHead aqueues;
    EHCIQueueHead pqueues;

    /* which address to look at next */
    uint32_t a_fetch_addr;
    uint32_t p_fetch_addr;

    USBPacket ipacket;
    QEMUSGList isgl;

    uint64_t last_run_ns;
    uint32_t async_stepdown;
    uint32_t periodic_sched_active;
    bool int_req_by_async;
};

extern const VMStateDescription vmstate_ehci;

void usb_ehci_initfn(EHCIState *s, DeviceState *dev);

#define TYPE_PCI_EHCI "pci-ehci-usb"
#define PCI_EHCI(obj) OBJECT_CHECK(EHCIPCIState, (obj), TYPE_PCI_EHCI)

typedef struct EHCIPCIState {
    /*< private >*/
    PCIDevice pcidev;
    /*< public >*/

    EHCIState ehci;
} EHCIPCIState;


#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"

#define SYS_BUS_EHCI(obj) \
    OBJECT_CHECK(EHCISysBusState, (obj), TYPE_SYS_BUS_EHCI)
#define SYS_BUS_EHCI_CLASS(class) \
    OBJECT_CLASS_CHECK(SysBusEHCIClass, (class), TYPE_SYS_BUS_EHCI)
#define SYS_BUS_EHCI_GET_CLASS(obj) \
    OBJECT_GET_CLASS(SysBusEHCIClass, (obj), TYPE_SYS_BUS_EHCI)

typedef struct EHCISysBusState {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    EHCIState ehci;
} EHCISysBusState;

typedef struct SysBusEHCIClass {
    /*< private >*/
    SysBusDeviceClass parent_class;
    /*< public >*/

    uint16_t capsbase;
    uint16_t opregbase;
} SysBusEHCIClass;

#endif
Commit	Line	Data
0bf96f94 GH	1	/*
	2	* QEMU USB EHCI Emulation
	3	*
	4	* This library is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU Lesser General Public
	6	* License as published by the Free Software Foundation; either
	7	* version 2 of the License, or(at your option) any later version.
	8	*
	9	* This library is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* Lesser General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	16	*/
cb9c377f PB	17	#ifndef HW_USB_EHCI_H
cb9c377f PB	18	#define HW_USB_EHCI_H 1
0bf96f94 GH	19
0bf96f94 GH	20	#include "hw/hw.h"
1de7afc9	21	#include "qemu/timer.h"
0bf96f94	22	#include "hw/usb.h"
83c9089e	23	#include "monitor/monitor.h"
0bf96f94	24	#include "trace.h"
9c17d615 PB	25	#include "sysemu/dma.h"
9c17d615 PB	26	#include "sysemu/sysemu.h"
5aa3ca9f AF	27	#include "hw/pci/pci.h"
5aa3ca9f AF	28	#include "hw/sysbus.h"
0bf96f94 GH	29
	30	#ifndef EHCI_DEBUG
	31	#define EHCI_DEBUG 0
	32	#endif
	33
	34	#if EHCI_DEBUG
	35	#define DPRINTF printf
	36	#else
	37	#define DPRINTF(...)
	38	#endif
	39
	40	#define MMIO_SIZE 0x1000
	41	#define CAPA_SIZE 0x10
	42
	43	#define PORTSC 0x0044
	44	#define PORTSC_BEGIN PORTSC
	45	#define PORTSC_END (PORTSC + 4 * NB_PORTS)
	46
	47	#define NB_PORTS 6 /* Number of downstream ports */
	48
	49	typedef struct EHCIPacket EHCIPacket;
	50	typedef struct EHCIQueue EHCIQueue;
	51	typedef struct EHCIState EHCIState;
	52
	53	/* EHCI spec version 1.0 Section 3.3
	54	*/
	55	typedef struct EHCIitd {
	56	uint32_t next;
	57
	58	uint32_t transact[8];
	59	#define ITD_XACT_ACTIVE (1 << 31)
	60	#define ITD_XACT_DBERROR (1 << 30)
	61	#define ITD_XACT_BABBLE (1 << 29)
	62	#define ITD_XACT_XACTERR (1 << 28)
	63	#define ITD_XACT_LENGTH_MASK 0x0fff0000
	64	#define ITD_XACT_LENGTH_SH 16
	65	#define ITD_XACT_IOC (1 << 15)
	66	#define ITD_XACT_PGSEL_MASK 0x00007000
	67	#define ITD_XACT_PGSEL_SH 12
	68	#define ITD_XACT_OFFSET_MASK 0x00000fff
	69
	70	uint32_t bufptr[7];
	71	#define ITD_BUFPTR_MASK 0xfffff000
	72	#define ITD_BUFPTR_SH 12
	73	#define ITD_BUFPTR_EP_MASK 0x00000f00
	74	#define ITD_BUFPTR_EP_SH 8
	75	#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
	76	#define ITD_BUFPTR_DEVADDR_SH 0
	77	#define ITD_BUFPTR_DIRECTION (1 << 11)
	78	#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
	79	#define ITD_BUFPTR_MAXPKT_SH 0
	80	#define ITD_BUFPTR_MULT_MASK 0x00000003
	81	#define ITD_BUFPTR_MULT_SH 0
	82	} EHCIitd;
	83
	84	/* EHCI spec version 1.0 Section 3.4
	85	*/
	86	typedef struct EHCIsitd {
	87	uint32_t next; /* Standard next link pointer */
	88	uint32_t epchar;
	89	#define SITD_EPCHAR_IO (1 << 31)
	90	#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
	91	#define SITD_EPCHAR_PORTNUM_SH 24
	92	#define SITD_EPCHAR_HUBADD_MASK 0x007f0000
93	#define SITD_EPCHAR_HUBADDR_SH 16
94	#define SITD_EPCHAR_EPNUM_MASK 0x00000f00
95	#define SITD_EPCHAR_EPNUM_SH 8
96	#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
97
98	uint32_t uframe;
99	#define SITD_UFRAME_CMASK_MASK 0x0000ff00
100	#define SITD_UFRAME_CMASK_SH 8
101	#define SITD_UFRAME_SMASK_MASK 0x000000ff
102
103	uint32_t results;
104	#define SITD_RESULTS_IOC (1 << 31)
105	#define SITD_RESULTS_PGSEL (1 << 30)
106	#define SITD_RESULTS_TBYTES_MASK 0x03ff0000
107	#define SITD_RESULTS_TYBYTES_SH 16
108	#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
109	#define SITD_RESULTS_CPROGMASK_SH 8
110	#define SITD_RESULTS_ACTIVE (1 << 7)
111	#define SITD_RESULTS_ERR (1 << 6)
112	#define SITD_RESULTS_DBERR (1 << 5)
113	#define SITD_RESULTS_BABBLE (1 << 4)
114	#define SITD_RESULTS_XACTERR (1 << 3)
115	#define SITD_RESULTS_MISSEDUF (1 << 2)
116	#define SITD_RESULTS_SPLITXSTATE (1 << 1)
117
118	uint32_t bufptr[2];
119	#define SITD_BUFPTR_MASK 0xfffff000
120	#define SITD_BUFPTR_CURROFF_MASK 0x00000fff
121	#define SITD_BUFPTR_TPOS_MASK 0x00000018
122	#define SITD_BUFPTR_TPOS_SH 3
123	#define SITD_BUFPTR_TCNT_MASK 0x00000007
124
125	uint32_t backptr; /* Standard next link pointer */
126	} EHCIsitd;
127
128	/* EHCI spec version 1.0 Section 3.5
129	*/
130	typedef struct EHCIqtd {
131	uint32_t next; /* Standard next link pointer */
132	uint32_t altnext; /* Standard next link pointer */
133	uint32_t token;
134	#define QTD_TOKEN_DTOGGLE (1 << 31)
135	#define QTD_TOKEN_TBYTES_MASK 0x7fff0000
136	#define QTD_TOKEN_TBYTES_SH 16
137	#define QTD_TOKEN_IOC (1 << 15)
138	#define QTD_TOKEN_CPAGE_MASK 0x00007000
139	#define QTD_TOKEN_CPAGE_SH 12
140	#define QTD_TOKEN_CERR_MASK 0x00000c00
141	#define QTD_TOKEN_CERR_SH 10
142	#define QTD_TOKEN_PID_MASK 0x00000300
143	#define QTD_TOKEN_PID_SH 8
144	#define QTD_TOKEN_ACTIVE (1 << 7)
145	#define QTD_TOKEN_HALT (1 << 6)
146	#define QTD_TOKEN_DBERR (1 << 5)
147	#define QTD_TOKEN_BABBLE (1 << 4)
148	#define QTD_TOKEN_XACTERR (1 << 3)
149	#define QTD_TOKEN_MISSEDUF (1 << 2)
150	#define QTD_TOKEN_SPLITXSTATE (1 << 1)
151	#define QTD_TOKEN_PING (1 << 0)
152
153	uint32_t bufptr[5]; /* Standard buffer pointer */
154	#define QTD_BUFPTR_MASK 0xfffff000
155	#define QTD_BUFPTR_SH 12
156	} EHCIqtd;
157
158	/* EHCI spec version 1.0 Section 3.6
159	*/
160	typedef struct EHCIqh {
161	uint32_t next; /* Standard next link pointer */
162
163	/* endpoint characteristics */
164	uint32_t epchar;
165	#define QH_EPCHAR_RL_MASK 0xf0000000
166	#define QH_EPCHAR_RL_SH 28
167	#define QH_EPCHAR_C (1 << 27)
168	#define QH_EPCHAR_MPLEN_MASK 0x07FF0000
169	#define QH_EPCHAR_MPLEN_SH 16
170	#define QH_EPCHAR_H (1 << 15)
171	#define QH_EPCHAR_DTC (1 << 14)
172	#define QH_EPCHAR_EPS_MASK 0x00003000
173	#define QH_EPCHAR_EPS_SH 12
174	#define EHCI_QH_EPS_FULL 0
175	#define EHCI_QH_EPS_LOW 1
176	#define EHCI_QH_EPS_HIGH 2
177	#define EHCI_QH_EPS_RESERVED 3
178
179	#define QH_EPCHAR_EP_MASK 0x00000f00
180	#define QH_EPCHAR_EP_SH 8
181	#define QH_EPCHAR_I (1 << 7)
182	#define QH_EPCHAR_DEVADDR_MASK 0x0000007f
183	#define QH_EPCHAR_DEVADDR_SH 0
184
185	/* endpoint capabilities */
186	uint32_t epcap;
187	#define QH_EPCAP_MULT_MASK 0xc0000000
188	#define QH_EPCAP_MULT_SH 30
189	#define QH_EPCAP_PORTNUM_MASK 0x3f800000
190	#define QH_EPCAP_PORTNUM_SH 23
191	#define QH_EPCAP_HUBADDR_MASK 0x007f0000
192	#define QH_EPCAP_HUBADDR_SH 16
193	#define QH_EPCAP_CMASK_MASK 0x0000ff00
194	#define QH_EPCAP_CMASK_SH 8
195	#define QH_EPCAP_SMASK_MASK 0x000000ff
196	#define QH_EPCAP_SMASK_SH 0
197
198	uint32_t current_qtd; /* Standard next link pointer */
199	uint32_t next_qtd; /* Standard next link pointer */
200	uint32_t altnext_qtd;
201	#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
202	#define QH_ALTNEXT_NAKCNT_SH 1
203
204	uint32_t token; /* Same as QTD token */
205	uint32_t bufptr[5]; /* Standard buffer pointer */
206	#define BUFPTR_CPROGMASK_MASK 0x000000ff
207	#define BUFPTR_FRAMETAG_MASK 0x0000001f
208	#define BUFPTR_SBYTES_MASK 0x00000fe0
209	#define BUFPTR_SBYTES_SH 5
210	} EHCIqh;
211
212	/* EHCI spec version 1.0 Section 3.7
213	*/
214	typedef struct EHCIfstn {
215	uint32_t next; /* Standard next link pointer */
216	uint32_t backptr; /* Standard next link pointer */
217	} EHCIfstn;
218
219	enum async_state {
220	EHCI_ASYNC_NONE = 0,
221	EHCI_ASYNC_INITIALIZED,
222	EHCI_ASYNC_INFLIGHT,
223	EHCI_ASYNC_FINISHED,
224	};
225
226	struct EHCIPacket {
227	EHCIQueue *queue;
228	QTAILQ_ENTRY(EHCIPacket) next;
229
230	EHCIqtd qtd; /* copy of current QTD (being worked on) */
231	uint32_t qtdaddr; /* address QTD read from */
232
233	USBPacket packet;
234	QEMUSGList sgl;
235	int pid;
236	enum async_state async;
0bf96f94 GH	237	};
	238
	239	struct EHCIQueue {
	240	EHCIState *ehci;
	241	QTAILQ_ENTRY(EHCIQueue) next;
	242	uint32_t seen;
	243	uint64_t ts;
	244	int async;
	245	int transact_ctr;
	246
	247	/* cached data from guest - needs to be flushed
	248	* when guest removes an entry (doorbell, handshake sequence)
	249	*/
	250	EHCIqh qh; /* copy of current QH (being worked on) */
	251	uint32_t qhaddr; /* address QH read from */
	252	uint32_t qtdaddr; /* address QTD read from */
bbbc39cc	253	int last_pid; /* pid of last packet executed */
0bf96f94 GH	254	USBDevice *dev;
	255	QTAILQ_HEAD(pkts_head, EHCIPacket) packets;
	256	};
	257
	258	typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
	259
	260	struct EHCIState {
	261	USBBus bus;
	262	qemu_irq irq;
	263	MemoryRegion mem;
	264	DMAContext *dma;
	265	MemoryRegion mem_caps;
	266	MemoryRegion mem_opreg;
	267	MemoryRegion mem_ports;
	268	int companion_count;
	269	uint16_t capsbase;
	270	uint16_t opregbase;
	271
	272	/* properties */
	273	uint32_t maxframes;
	274
	275	/*
	276	* EHCI spec version 1.0 Section 2.3
	277	* Host Controller Operational Registers
	278	*/
	279	uint8_t caps[CAPA_SIZE];
	280	union {
	281	uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)];
	282	struct {
	283	uint32_t usbcmd;
	284	uint32_t usbsts;
	285	uint32_t usbintr;
	286	uint32_t frindex;
	287	uint32_t ctrldssegment;
	288	uint32_t periodiclistbase;
	289	uint32_t asynclistaddr;
	290	uint32_t notused[9];
	291	uint32_t configflag;
	292	};
	293	};
	294	uint32_t portsc[NB_PORTS];
	295
	296	/*
	297	* Internal states, shadow registers, etc
	298	*/
	299	QEMUTimer *frame_timer;
	300	QEMUBH *async_bh;
	301	uint32_t astate; /* Current state in asynchronous schedule */
	302	uint32_t pstate; /* Current state in periodic schedule */
	303	USBPort ports[NB_PORTS];
	304	USBPort *companion_ports[NB_PORTS];
	305	uint32_t usbsts_pending;
	306	uint32_t usbsts_frindex;
	307	EHCIQueueHead aqueues;
	308	EHCIQueueHead pqueues;
	309
	310	/* which address to look at next */
	311	uint32_t a_fetch_addr;
	312	uint32_t p_fetch_addr;
	313
	314	USBPacket ipacket;
	315	QEMUSGList isgl;
	316
	317	uint64_t last_run_ns;
318	uint32_t async_stepdown;
80826240	319	uint32_t periodic_sched_active;
0bf96f94 GH	320	bool int_req_by_async;
	321	};
	322
	323	extern const VMStateDescription vmstate_ehci;
	324
	325	void usb_ehci_initfn(EHCIState s, DeviceState dev);
cb9c377f	326
5aa3ca9f AF	327	#define TYPE_PCI_EHCI "pci-ehci-usb"
	328	#define PCI_EHCI(obj) OBJECT_CHECK(EHCIPCIState, (obj), TYPE_PCI_EHCI)
	329
	330	typedef struct EHCIPCIState {
	331	/< private >/
	332	PCIDevice pcidev;
	333	/< public >/
	334
	335	EHCIState ehci;
	336	} EHCIPCIState;
	337
	338
	339	#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
aee7499a AF	340	#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
aee7499a AF	341
5aa3ca9f AF	342	#define SYS_BUS_EHCI(obj) \
5aa3ca9f AF	343	OBJECT_CHECK(EHCISysBusState, (obj), TYPE_SYS_BUS_EHCI)
4a434367 AF	344	#define SYS_BUS_EHCI_CLASS(class) \
	345	OBJECT_CLASS_CHECK(SysBusEHCIClass, (class), TYPE_SYS_BUS_EHCI)
	346	#define SYS_BUS_EHCI_GET_CLASS(obj) \
	347	OBJECT_GET_CLASS(SysBusEHCIClass, (obj), TYPE_SYS_BUS_EHCI)
5aa3ca9f AF	348
	349	typedef struct EHCISysBusState {
	350	/< private >/
	351	SysBusDevice parent_obj;
	352	/< public >/
	353
	354	EHCIState ehci;
	355	} EHCISysBusState;
	356
4a434367 AF	357	typedef struct SysBusEHCIClass {
	358	/< private >/
	359	SysBusDeviceClass parent_class;
	360	/< public >/
	361
	362	uint16_t capsbase;
	363	uint16_t opregbase;
	364	} SysBusEHCIClass;
	365
cb9c377f	366	#endif