[qemu.git] / tests / fdc-test.c

/*
 * Floppy test cases.
 *
 * Copyright (c) 2012 Kevin Wolf <[email protected]>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"


#include "libqtest.h"
#include "qemu-common.h"

#define TEST_IMAGE_SIZE 1440 * 1024

#define FLOPPY_BASE 0x3f0
#define FLOPPY_IRQ 6

enum {
    reg_sra         = 0x0,
    reg_srb         = 0x1,
    reg_dor         = 0x2,
    reg_msr         = 0x4,
    reg_dsr         = 0x4,
    reg_fifo        = 0x5,
    reg_dir         = 0x7,
};

enum {
    CMD_SENSE_INT           = 0x08,
    CMD_READ_ID             = 0x0a,
    CMD_SEEK                = 0x0f,
    CMD_VERIFY              = 0x16,
    CMD_READ                = 0xe6,
    CMD_RELATIVE_SEEK_OUT   = 0x8f,
    CMD_RELATIVE_SEEK_IN    = 0xcf,
};

enum {
    BUSY    = 0x10,
    NONDMA  = 0x20,
    RQM     = 0x80,
    DIO     = 0x40,

    DSKCHG  = 0x80,
};

static char test_image[] = "/tmp/qtest.XXXXXX";

#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)

static uint8_t base = 0x70;

enum {
    CMOS_FLOPPY     = 0x10,
};

static void floppy_send(uint8_t byte)
{
    uint8_t msr;

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, RQM);
    assert_bit_clear(msr, DIO);

    outb(FLOPPY_BASE + reg_fifo, byte);
}

static uint8_t floppy_recv(void)
{
    uint8_t msr;

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, RQM | DIO);

    return inb(FLOPPY_BASE + reg_fifo);
}

/* pcn: Present Cylinder Number */
static void ack_irq(uint8_t *pcn)
{
    uint8_t ret;

    g_assert(get_irq(FLOPPY_IRQ));
    floppy_send(CMD_SENSE_INT);
    floppy_recv();

    ret = floppy_recv();
    if (pcn != NULL) {
        *pcn = ret;
    }

    g_assert(!get_irq(FLOPPY_IRQ));
}

static uint8_t send_read_command(uint8_t cmd)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl = 0;
    uint8_t sect_addr = 1;
    uint8_t sect_size = 2;
    uint8_t eot = 1;
    uint8_t gap = 0x1b;
    uint8_t gpl = 0xff;

    uint8_t msr = 0;
    uint8_t st0;

    uint8_t ret = 0;

    floppy_send(cmd);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    floppy_send(head);
    floppy_send(sect_addr);
    floppy_send(sect_size);
    floppy_send(eot);
    floppy_send(gap);
    floppy_send(gpl);

    uint8_t i = 0;
    uint8_t n = 2;
    for (; i < n; i++) {
        msr = inb(FLOPPY_BASE + reg_msr);
        if (msr == 0xd0) {
            break;
        }
        sleep(1);
    }

    if (i >= n) {
        return 1;
    }

    st0 = floppy_recv();
    if (st0 != 0x40) {
        ret = 1;
    }

    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();

    return ret;
}

static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl = 0;
    uint8_t sect_addr = 1;
    uint8_t sect_size = 2;
    uint8_t eot = nb_sect;
    uint8_t gap = 0x1b;
    uint8_t gpl = 0xff;

    uint8_t msr = 0;
    uint8_t st0;

    uint8_t ret = 0;

    floppy_send(CMD_READ);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    floppy_send(head);
    floppy_send(sect_addr);
    floppy_send(sect_size);
    floppy_send(eot);
    floppy_send(gap);
    floppy_send(gpl);

    uint16_t i = 0;
    uint8_t n = 2;
    for (; i < n; i++) {
        msr = inb(FLOPPY_BASE + reg_msr);
        if (msr == (BUSY | NONDMA | DIO | RQM)) {
            break;
        }
        sleep(1);
    }

    if (i >= n) {
        return 1;
    }

    /* Non-DMA mode */
    for (i = 0; i < 512 * 2 * nb_sect; i++) {
        msr = inb(FLOPPY_BASE + reg_msr);
        assert_bit_set(msr, BUSY | RQM | DIO);
        inb(FLOPPY_BASE + reg_fifo);
    }

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, BUSY | RQM | DIO);
    g_assert(get_irq(FLOPPY_IRQ));

    st0 = floppy_recv();
    if (st0 != expected_st0) {
        ret = 1;
    }

    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    floppy_recv();
    g_assert(get_irq(FLOPPY_IRQ));
    floppy_recv();

    /* Check that we're back in command phase */
    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_clear(msr, BUSY | DIO);
    assert_bit_set(msr, RQM);
    g_assert(!get_irq(FLOPPY_IRQ));

    return ret;
}

static void send_seek(int cyl)
{
    int drive = 0;
    int head = 0;

    floppy_send(CMD_SEEK);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    ack_irq(NULL);
}

static uint8_t cmos_read(uint8_t reg)
{
    outb(base + 0, reg);
    return inb(base + 1);
}

static void test_cmos(void)
{
    uint8_t cmos;

    cmos = cmos_read(CMOS_FLOPPY);
    g_assert(cmos == 0x40 || cmos == 0x50);
}

static void test_no_media_on_start(void)
{
    uint8_t dir;

    /* Media changed bit must be set all time after start if there is
     * no media in drive. */
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    send_seek(1);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
}

static void test_read_without_media(void)
{
    uint8_t ret;

    ret = send_read_command(CMD_READ);
    g_assert(ret == 0);
}

static void test_media_insert(void)
{
    uint8_t dir;

    /* Insert media in drive. DSKCHK should not be reset until a step pulse
     * is sent. */
    qmp_discard_response("{'execute':'change', 'arguments':{"
                         " 'device':'floppy0', 'target': %s, 'arg': 'raw' }}",
                         test_image);

    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    send_seek(0);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    /* Step to next track should clear DSKCHG bit. */
    send_seek(1);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_clear(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_clear(dir, DSKCHG);
}

static void test_media_change(void)
{
    uint8_t dir;

    test_media_insert();

    /* Eject the floppy and check that DSKCHG is set. Reading it out doesn't
     * reset the bit. */
    qmp_discard_response("{'execute':'eject', 'arguments':{"
                         " 'device':'floppy0' }}");

    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    send_seek(0);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);

    send_seek(1);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
    dir = inb(FLOPPY_BASE + reg_dir);
    assert_bit_set(dir, DSKCHG);
}

static void test_sense_interrupt(void)
{
    int drive = 0;
    int head = 0;
    int cyl = 0;
    int ret = 0;

    floppy_send(CMD_SENSE_INT);
    ret = floppy_recv();
    g_assert(ret == 0x80);

    floppy_send(CMD_SEEK);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);

    floppy_send(CMD_SENSE_INT);
    ret = floppy_recv();
    g_assert(ret == 0x20);
    floppy_recv();
}

static void test_relative_seek(void)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl = 1;
    uint8_t pcn;

    /* Send seek to track 0 */
    send_seek(0);

    /* Send relative seek to increase track by 1 */
    floppy_send(CMD_RELATIVE_SEEK_IN);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);

    ack_irq(&pcn);
    g_assert(pcn == 1);

    /* Send relative seek to decrease track by 1 */
    floppy_send(CMD_RELATIVE_SEEK_OUT);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);

    ack_irq(&pcn);
    g_assert(pcn == 0);
}

static void test_read_id(void)
{
    uint8_t drive = 0;
    uint8_t head = 0;
    uint8_t cyl;
    uint8_t st0;
    uint8_t msr;

    /* Seek to track 0 and check with READ ID */
    send_seek(0);

    floppy_send(CMD_READ_ID);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(head << 2 | drive);

    msr = inb(FLOPPY_BASE + reg_msr);
    if (!get_irq(FLOPPY_IRQ)) {
        assert_bit_set(msr, BUSY);
        assert_bit_clear(msr, RQM);
    }

    while (!get_irq(FLOPPY_IRQ)) {
        /* qemu involves a timer with READ ID... */
        clock_step(1000000000LL / 50);
    }

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, BUSY | RQM | DIO);

    st0 = floppy_recv();
    floppy_recv();
    floppy_recv();
    cyl = floppy_recv();
    head = floppy_recv();
    floppy_recv();
    g_assert(get_irq(FLOPPY_IRQ));
    floppy_recv();
    g_assert(!get_irq(FLOPPY_IRQ));

    g_assert_cmpint(cyl, ==, 0);
    g_assert_cmpint(head, ==, 0);
    g_assert_cmpint(st0, ==, head << 2);

    /* Seek to track 8 on head 1 and check with READ ID */
    head = 1;
    cyl = 8;

    floppy_send(CMD_SEEK);
    floppy_send(head << 2 | drive);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(cyl);
    g_assert(get_irq(FLOPPY_IRQ));
    ack_irq(NULL);

    floppy_send(CMD_READ_ID);
    g_assert(!get_irq(FLOPPY_IRQ));
    floppy_send(head << 2 | drive);

    msr = inb(FLOPPY_BASE + reg_msr);
    if (!get_irq(FLOPPY_IRQ)) {
        assert_bit_set(msr, BUSY);
        assert_bit_clear(msr, RQM);
    }

    while (!get_irq(FLOPPY_IRQ)) {
        /* qemu involves a timer with READ ID... */
        clock_step(1000000000LL / 50);
    }

    msr = inb(FLOPPY_BASE + reg_msr);
    assert_bit_set(msr, BUSY | RQM | DIO);

    st0 = floppy_recv();
    floppy_recv();
    floppy_recv();
    cyl = floppy_recv();
    head = floppy_recv();
    floppy_recv();
    g_assert(get_irq(FLOPPY_IRQ));
    floppy_recv();
    g_assert(!get_irq(FLOPPY_IRQ));

    g_assert_cmpint(cyl, ==, 8);
    g_assert_cmpint(head, ==, 1);
    g_assert_cmpint(st0, ==, head << 2);
}

static void test_read_no_dma_1(void)
{
    uint8_t ret;

    outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
    send_seek(0);
    ret = send_read_no_dma_command(1, 0x04);
    g_assert(ret == 0);
}

static void test_read_no_dma_18(void)
{
    uint8_t ret;

    outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
    send_seek(0);
    ret = send_read_no_dma_command(18, 0x04);
    g_assert(ret == 0);
}

static void test_read_no_dma_19(void)
{
    uint8_t ret;

    outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
    send_seek(0);
    ret = send_read_no_dma_command(19, 0x20);
    g_assert(ret == 0);
}

static void test_verify(void)
{
    uint8_t ret;

    ret = send_read_command(CMD_VERIFY);
    g_assert(ret == 0);
}

/* success if no crash or abort */
static void fuzz_registers(void)
{
    unsigned int i;

    for (i = 0; i < 1000; i++) {
        uint8_t reg, val;

        reg = (uint8_t)g_test_rand_int_range(0, 8);
        val = (uint8_t)g_test_rand_int_range(0, 256);

        outb(FLOPPY_BASE + reg, val);
        inb(FLOPPY_BASE + reg);
    }
}

int main(int argc, char **argv)
{
    const char *arch = qtest_get_arch();
    int fd;
    int ret;

    /* Check architecture */
    if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
        g_test_message("Skipping test for non-x86\n");
        return 0;
    }

    /* Create a temporary raw image */
    fd = mkstemp(test_image);
    g_assert(fd >= 0);
    ret = ftruncate(fd, TEST_IMAGE_SIZE);
    g_assert(ret == 0);
    close(fd);

    /* Run the tests */
    g_test_init(&argc, &argv, NULL);

    qtest_start(NULL);
    qtest_irq_intercept_in(global_qtest, "ioapic");
    qtest_add_func("/fdc/cmos", test_cmos);
    qtest_add_func("/fdc/no_media_on_start", test_no_media_on_start);
    qtest_add_func("/fdc/read_without_media", test_read_without_media);
    qtest_add_func("/fdc/media_change", test_media_change);
    qtest_add_func("/fdc/sense_interrupt", test_sense_interrupt);
    qtest_add_func("/fdc/relative_seek", test_relative_seek);
    qtest_add_func("/fdc/read_id", test_read_id);
    qtest_add_func("/fdc/verify", test_verify);
    qtest_add_func("/fdc/media_insert", test_media_insert);
    qtest_add_func("/fdc/read_no_dma_1", test_read_no_dma_1);
    qtest_add_func("/fdc/read_no_dma_18", test_read_no_dma_18);
    qtest_add_func("/fdc/read_no_dma_19", test_read_no_dma_19);
    qtest_add_func("/fdc/fuzz-registers", fuzz_registers);

    ret = g_test_run();

    /* Cleanup */
    qtest_end();
    unlink(test_image);

    return ret;
}
Commit	Line	Data
93e9eb68 KW	1	/*
	2	* Floppy test cases.
	3	*
	4	* Copyright (c) 2012 Kevin Wolf <[email protected]>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
681c28a3	25	#include "qemu/osdep.h"
93e9eb68	26
93e9eb68 KW	27
	28	#include "libqtest.h"
	29	#include "qemu-common.h"
	30
	31	#define TEST_IMAGE_SIZE 1440 * 1024
	32
	33	#define FLOPPY_BASE 0x3f0
	34	#define FLOPPY_IRQ 6
	35
	36	enum {
	37	reg_sra = 0x0,
	38	reg_srb = 0x1,
	39	reg_dor = 0x2,
	40	reg_msr = 0x4,
	41	reg_dsr = 0x4,
	42	reg_fifo = 0x5,
	43	reg_dir = 0x7,
	44	};
	45
	46	enum {
98272dbb	47	CMD_SENSE_INT = 0x08,
67f194bd	48	CMD_READ_ID = 0x0a,
98272dbb	49	CMD_SEEK = 0x0f,
6f442fe8	50	CMD_VERIFY = 0x16,
98272dbb PH	51	CMD_READ = 0xe6,
	52	CMD_RELATIVE_SEEK_OUT = 0x8f,
	53	CMD_RELATIVE_SEEK_IN = 0xcf,
93e9eb68 KW	54	};
	55
	56	enum {
5f8ae8e2 HP	57	BUSY = 0x10,
5f8ae8e2 HP	58	NONDMA = 0x20,
93e9eb68 KW	59	RQM = 0x80,
	60	DIO = 0x40,
	61
	62	DSKCHG = 0x80,
	63	};
	64
748bfb4e	65	static char test_image[] = "/tmp/qtest.XXXXXX";
93e9eb68 KW	66
	67	#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
	68	#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
	69
7cd33161 PH	70	static uint8_t base = 0x70;
	71
	72	enum {
	73	CMOS_FLOPPY = 0x10,
	74	};
	75
93e9eb68 KW	76	static void floppy_send(uint8_t byte)
	77	{
	78	uint8_t msr;
	79
	80	msr = inb(FLOPPY_BASE + reg_msr);
	81	assert_bit_set(msr, RQM);
	82	assert_bit_clear(msr, DIO);
	83
	84	outb(FLOPPY_BASE + reg_fifo, byte);
	85	}
	86
	87	static uint8_t floppy_recv(void)
	88	{
	89	uint8_t msr;
	90
	91	msr = inb(FLOPPY_BASE + reg_msr);
	92	assert_bit_set(msr, RQM \| DIO);
	93
	94	return inb(FLOPPY_BASE + reg_fifo);
	95	}
	96
c3cdc1b0 KW	97	/* pcn: Present Cylinder Number */
c3cdc1b0 KW	98	static void ack_irq(uint8_t *pcn)
93e9eb68	99	{
98272dbb PH	100	uint8_t ret;
98272dbb PH	101
93e9eb68 KW	102	g_assert(get_irq(FLOPPY_IRQ));
	103	floppy_send(CMD_SENSE_INT);
	104	floppy_recv();
c3cdc1b0	105
98272dbb	106	ret = floppy_recv();
c3cdc1b0 KW	107	if (pcn != NULL) {
	108	*pcn = ret;
	109	}
98272dbb	110
c3cdc1b0	111	g_assert(!get_irq(FLOPPY_IRQ));
93e9eb68 KW	112	}
93e9eb68 KW	113
6f442fe8	114	static uint8_t send_read_command(uint8_t cmd)
8b9ef60d PH	115	{
	116	uint8_t drive = 0;
	117	uint8_t head = 0;
	118	uint8_t cyl = 0;
	119	uint8_t sect_addr = 1;
	120	uint8_t sect_size = 2;
	121	uint8_t eot = 1;
	122	uint8_t gap = 0x1b;
	123	uint8_t gpl = 0xff;
	124
	125	uint8_t msr = 0;
	126	uint8_t st0;
	127
	128	uint8_t ret = 0;
	129
6f442fe8	130	floppy_send(cmd);
8b9ef60d PH	131	floppy_send(head << 2 \| drive);
	132	g_assert(!get_irq(FLOPPY_IRQ));
	133	floppy_send(cyl);
	134	floppy_send(head);
	135	floppy_send(sect_addr);
	136	floppy_send(sect_size);
	137	floppy_send(eot);
	138	floppy_send(gap);
	139	floppy_send(gpl);
	140
	141	uint8_t i = 0;
	142	uint8_t n = 2;
	143	for (; i < n; i++) {
	144	msr = inb(FLOPPY_BASE + reg_msr);
	145	if (msr == 0xd0) {
	146	break;
	147	}
	148	sleep(1);
	149	}
	150
	151	if (i >= n) {
	152	return 1;
	153	}
	154
	155	st0 = floppy_recv();
075f5532	156	if (st0 != 0x40) {
8b9ef60d PH	157	ret = 1;
	158	}
	159
	160	floppy_recv();
	161	floppy_recv();
	162	floppy_recv();
	163	floppy_recv();
	164	floppy_recv();
	165	floppy_recv();
	166
	167	return ret;
	168	}
	169
5f8ae8e2 HP	170	static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
	171	{
	172	uint8_t drive = 0;
	173	uint8_t head = 0;
	174	uint8_t cyl = 0;
	175	uint8_t sect_addr = 1;
	176	uint8_t sect_size = 2;
	177	uint8_t eot = nb_sect;
	178	uint8_t gap = 0x1b;
	179	uint8_t gpl = 0xff;
	180
	181	uint8_t msr = 0;
	182	uint8_t st0;
	183
	184	uint8_t ret = 0;
	185
	186	floppy_send(CMD_READ);
	187	floppy_send(head << 2 \| drive);
	188	g_assert(!get_irq(FLOPPY_IRQ));
	189	floppy_send(cyl);
	190	floppy_send(head);
	191	floppy_send(sect_addr);
	192	floppy_send(sect_size);
	193	floppy_send(eot);
	194	floppy_send(gap);
	195	floppy_send(gpl);
	196
	197	uint16_t i = 0;
	198	uint8_t n = 2;
	199	for (; i < n; i++) {
	200	msr = inb(FLOPPY_BASE + reg_msr);
	201	if (msr == (BUSY \| NONDMA \| DIO \| RQM)) {
	202	break;
	203	}
	204	sleep(1);
	205	}
	206
	207	if (i >= n) {
	208	return 1;
	209	}
	210
	211	/* Non-DMA mode */
	212	for (i = 0; i < 512 * 2 * nb_sect; i++) {
	213	msr = inb(FLOPPY_BASE + reg_msr);
	214	assert_bit_set(msr, BUSY \| RQM \| DIO);
	215	inb(FLOPPY_BASE + reg_fifo);
	216	}
	217
4964e18e KW	218	msr = inb(FLOPPY_BASE + reg_msr);
	219	assert_bit_set(msr, BUSY \| RQM \| DIO);
	220	g_assert(get_irq(FLOPPY_IRQ));
	221
5f8ae8e2 HP	222	st0 = floppy_recv();
	223	if (st0 != expected_st0) {
	224	ret = 1;
	225	}
	226
	227	floppy_recv();
	228	floppy_recv();
	229	floppy_recv();
	230	floppy_recv();
	231	floppy_recv();
4964e18e	232	g_assert(get_irq(FLOPPY_IRQ));
5f8ae8e2 HP	233	floppy_recv();
5f8ae8e2 HP	234
4964e18e KW	235	/* Check that we're back in command phase */
	236	msr = inb(FLOPPY_BASE + reg_msr);
	237	assert_bit_clear(msr, BUSY \| DIO);
	238	assert_bit_set(msr, RQM);
	239	g_assert(!get_irq(FLOPPY_IRQ));
	240
5f8ae8e2 HP	241	return ret;
	242	}
	243
c3cdc1b0	244	static void send_seek(int cyl)
93e9eb68 KW	245	{
	246	int drive = 0;
	247	int head = 0;
93e9eb68 KW	248
	249	floppy_send(CMD_SEEK);
	250	floppy_send(head << 2 \| drive);
	251	g_assert(!get_irq(FLOPPY_IRQ));
	252	floppy_send(cyl);
c3cdc1b0	253	ack_irq(NULL);
93e9eb68 KW	254	}
93e9eb68 KW	255
7cd33161	256	static uint8_t cmos_read(uint8_t reg)
93e9eb68	257	{
7cd33161 PH	258	outb(base + 0, reg);
	259	return inb(base + 1);
	260	}
93e9eb68	261
7cd33161 PH	262	static void test_cmos(void)
	263	{
	264	uint8_t cmos;
93e9eb68	265
7cd33161	266	cmos = cmos_read(CMOS_FLOPPY);
62c76250	267	g_assert(cmos == 0x40 \|\| cmos == 0x50);
7cd33161	268	}
93e9eb68	269
7cd33161 PH	270	static void test_no_media_on_start(void)
	271	{
	272	uint8_t dir;
	273
	274	/* Media changed bit must be set all time after start if there is
	275	* no media in drive. */
93e9eb68 KW	276	dir = inb(FLOPPY_BASE + reg_dir);
	277	assert_bit_set(dir, DSKCHG);
	278	dir = inb(FLOPPY_BASE + reg_dir);
	279	assert_bit_set(dir, DSKCHG);
c3cdc1b0	280	send_seek(1);
93e9eb68 KW	281	dir = inb(FLOPPY_BASE + reg_dir);
	282	assert_bit_set(dir, DSKCHG);
	283	dir = inb(FLOPPY_BASE + reg_dir);
	284	assert_bit_set(dir, DSKCHG);
7cd33161 PH	285	}
7cd33161 PH	286
8b9ef60d PH	287	static void test_read_without_media(void)
	288	{
	289	uint8_t ret;
	290
6f442fe8	291	ret = send_read_command(CMD_READ);
8b9ef60d PH	292	g_assert(ret == 0);
	293	}
	294
1f507913	295	static void test_media_insert(void)
7cd33161 PH	296	{
7cd33161 PH	297	uint8_t dir;
93e9eb68	298
7cd33161	299	/* Insert media in drive. DSKCHK should not be reset until a step pulse
93e9eb68	300	* is sent. */
0d1aa05e	301	qmp_discard_response("{'execute':'change', 'arguments':{"
b8e665e4	302	" 'device':'floppy0', 'target': %s, 'arg': 'raw' }}",
0d1aa05e	303	test_image);
93e9eb68 KW	304
	305	dir = inb(FLOPPY_BASE + reg_dir);
	306	assert_bit_set(dir, DSKCHG);
	307	dir = inb(FLOPPY_BASE + reg_dir);
	308	assert_bit_set(dir, DSKCHG);
	309
c3cdc1b0	310	send_seek(0);
59240c34 PH	311	dir = inb(FLOPPY_BASE + reg_dir);
	312	assert_bit_set(dir, DSKCHG);
	313	dir = inb(FLOPPY_BASE + reg_dir);
	314	assert_bit_set(dir, DSKCHG);
	315
	316	/* Step to next track should clear DSKCHG bit. */
c3cdc1b0	317	send_seek(1);
93e9eb68 KW	318	dir = inb(FLOPPY_BASE + reg_dir);
	319	assert_bit_clear(dir, DSKCHG);
	320	dir = inb(FLOPPY_BASE + reg_dir);
	321	assert_bit_clear(dir, DSKCHG);
1f507913 HP	322	}
	323
	324	static void test_media_change(void)
	325	{
	326	uint8_t dir;
	327
	328	test_media_insert();
7cd33161 PH	329
	330	/* Eject the floppy and check that DSKCHG is set. Reading it out doesn't
	331	* reset the bit. */
0d1aa05e SH	332	qmp_discard_response("{'execute':'eject', 'arguments':{"
0d1aa05e SH	333	" 'device':'floppy0' }}");
7cd33161 PH	334
	335	dir = inb(FLOPPY_BASE + reg_dir);
	336	assert_bit_set(dir, DSKCHG);
	337	dir = inb(FLOPPY_BASE + reg_dir);
	338	assert_bit_set(dir, DSKCHG);
	339
c3cdc1b0	340	send_seek(0);
59240c34 PH	341	dir = inb(FLOPPY_BASE + reg_dir);
	342	assert_bit_set(dir, DSKCHG);
	343	dir = inb(FLOPPY_BASE + reg_dir);
	344	assert_bit_set(dir, DSKCHG);
	345
c3cdc1b0	346	send_seek(1);
7cd33161 PH	347	dir = inb(FLOPPY_BASE + reg_dir);
	348	assert_bit_set(dir, DSKCHG);
	349	dir = inb(FLOPPY_BASE + reg_dir);
	350	assert_bit_set(dir, DSKCHG);
93e9eb68 KW	351	}
93e9eb68 KW	352
b3ce604e PH	353	static void test_sense_interrupt(void)
	354	{
	355	int drive = 0;
	356	int head = 0;
	357	int cyl = 0;
	358	int ret = 0;
	359
	360	floppy_send(CMD_SENSE_INT);
	361	ret = floppy_recv();
	362	g_assert(ret == 0x80);
	363
	364	floppy_send(CMD_SEEK);
	365	floppy_send(head << 2 \| drive);
	366	g_assert(!get_irq(FLOPPY_IRQ));
	367	floppy_send(cyl);
	368
	369	floppy_send(CMD_SENSE_INT);
	370	ret = floppy_recv();
	371	g_assert(ret == 0x20);
	372	floppy_recv();
	373	}
	374
98272dbb PH	375	static void test_relative_seek(void)
	376	{
	377	uint8_t drive = 0;
	378	uint8_t head = 0;
	379	uint8_t cyl = 1;
c3cdc1b0	380	uint8_t pcn;
98272dbb PH	381
98272dbb PH	382	/* Send seek to track 0 */
c3cdc1b0	383	send_seek(0);
98272dbb PH	384
	385	/* Send relative seek to increase track by 1 */
	386	floppy_send(CMD_RELATIVE_SEEK_IN);
	387	floppy_send(head << 2 \| drive);
	388	g_assert(!get_irq(FLOPPY_IRQ));
	389	floppy_send(cyl);
	390
c3cdc1b0 KW	391	ack_irq(&pcn);
c3cdc1b0 KW	392	g_assert(pcn == 1);
98272dbb PH	393
	394	/* Send relative seek to decrease track by 1 */
	395	floppy_send(CMD_RELATIVE_SEEK_OUT);
	396	floppy_send(head << 2 \| drive);
	397	g_assert(!get_irq(FLOPPY_IRQ));
	398	floppy_send(cyl);
	399
c3cdc1b0 KW	400	ack_irq(&pcn);
c3cdc1b0 KW	401	g_assert(pcn == 0);
98272dbb PH	402	}
98272dbb PH	403
67f194bd KW	404	static void test_read_id(void)
	405	{
	406	uint8_t drive = 0;
	407	uint8_t head = 0;
	408	uint8_t cyl;
	409	uint8_t st0;
4964e18e	410	uint8_t msr;
67f194bd KW	411
	412	/* Seek to track 0 and check with READ ID */
	413	send_seek(0);
	414
	415	floppy_send(CMD_READ_ID);
	416	g_assert(!get_irq(FLOPPY_IRQ));
	417	floppy_send(head << 2 \| drive);
	418
4964e18e KW	419	msr = inb(FLOPPY_BASE + reg_msr);
	420	if (!get_irq(FLOPPY_IRQ)) {
	421	assert_bit_set(msr, BUSY);
	422	assert_bit_clear(msr, RQM);
	423	}
	424
67f194bd KW	425	while (!get_irq(FLOPPY_IRQ)) {
	426	/* qemu involves a timer with READ ID... */
	427	clock_step(1000000000LL / 50);
	428	}
	429
4964e18e KW	430	msr = inb(FLOPPY_BASE + reg_msr);
	431	assert_bit_set(msr, BUSY \| RQM \| DIO);
	432
67f194bd KW	433	st0 = floppy_recv();
	434	floppy_recv();
	435	floppy_recv();
	436	cyl = floppy_recv();
	437	head = floppy_recv();
	438	floppy_recv();
4964e18e	439	g_assert(get_irq(FLOPPY_IRQ));
67f194bd	440	floppy_recv();
4964e18e	441	g_assert(!get_irq(FLOPPY_IRQ));
67f194bd KW	442
	443	g_assert_cmpint(cyl, ==, 0);
	444	g_assert_cmpint(head, ==, 0);
	445	g_assert_cmpint(st0, ==, head << 2);
	446
	447	/* Seek to track 8 on head 1 and check with READ ID */
	448	head = 1;
	449	cyl = 8;
	450
	451	floppy_send(CMD_SEEK);
	452	floppy_send(head << 2 \| drive);
	453	g_assert(!get_irq(FLOPPY_IRQ));
	454	floppy_send(cyl);
	455	g_assert(get_irq(FLOPPY_IRQ));
	456	ack_irq(NULL);
	457
	458	floppy_send(CMD_READ_ID);
	459	g_assert(!get_irq(FLOPPY_IRQ));
	460	floppy_send(head << 2 \| drive);
	461
4964e18e KW	462	msr = inb(FLOPPY_BASE + reg_msr);
	463	if (!get_irq(FLOPPY_IRQ)) {
	464	assert_bit_set(msr, BUSY);
	465	assert_bit_clear(msr, RQM);
	466	}
	467
67f194bd KW	468	while (!get_irq(FLOPPY_IRQ)) {
	469	/* qemu involves a timer with READ ID... */
	470	clock_step(1000000000LL / 50);
	471	}
	472
4964e18e KW	473	msr = inb(FLOPPY_BASE + reg_msr);
	474	assert_bit_set(msr, BUSY \| RQM \| DIO);
	475
67f194bd KW	476	st0 = floppy_recv();
	477	floppy_recv();
	478	floppy_recv();
	479	cyl = floppy_recv();
	480	head = floppy_recv();
	481	floppy_recv();
4964e18e	482	g_assert(get_irq(FLOPPY_IRQ));
67f194bd	483	floppy_recv();
4964e18e	484	g_assert(!get_irq(FLOPPY_IRQ));
67f194bd KW	485
	486	g_assert_cmpint(cyl, ==, 8);
	487	g_assert_cmpint(head, ==, 1);
	488	g_assert_cmpint(st0, ==, head << 2);
	489	}
	490
5f8ae8e2 HP	491	static void test_read_no_dma_1(void)
	492	{
	493	uint8_t ret;
	494
	495	outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
	496	send_seek(0);
075f5532	497	ret = send_read_no_dma_command(1, 0x04);
5f8ae8e2 HP	498	g_assert(ret == 0);
	499	}
	500
	501	static void test_read_no_dma_18(void)
	502	{
	503	uint8_t ret;
	504
	505	outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
	506	send_seek(0);
075f5532	507	ret = send_read_no_dma_command(18, 0x04);
5f8ae8e2 HP	508	g_assert(ret == 0);
	509	}
	510
	511	static void test_read_no_dma_19(void)
	512	{
	513	uint8_t ret;
	514
	515	outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
	516	send_seek(0);
	517	ret = send_read_no_dma_command(19, 0x20);
	518	g_assert(ret == 0);
	519	}
	520
6f442fe8 HP	521	static void test_verify(void)
	522	{
	523	uint8_t ret;
	524
	525	ret = send_read_command(CMD_VERIFY);
	526	g_assert(ret == 0);
	527	}
	528
3359847e BS	529	/* success if no crash or abort */
	530	static void fuzz_registers(void)
	531	{
	532	unsigned int i;
	533
	534	for (i = 0; i < 1000; i++) {
	535	uint8_t reg, val;
	536
	537	reg = (uint8_t)g_test_rand_int_range(0, 8);
	538	val = (uint8_t)g_test_rand_int_range(0, 256);
	539
	540	outb(FLOPPY_BASE + reg, val);
	541	inb(FLOPPY_BASE + reg);
	542	}
	543	}
	544
93e9eb68 KW	545	int main(int argc, char **argv)
	546	{
	547	const char *arch = qtest_get_arch();
93e9eb68 KW	548	int fd;
	549	int ret;
	550
	551	/* Check architecture */
	552	if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
	553	g_test_message("Skipping test for non-x86\n");
	554	return 0;
	555	}
	556
	557	/* Create a temporary raw image */
	558	fd = mkstemp(test_image);
	559	g_assert(fd >= 0);
	560	ret = ftruncate(fd, TEST_IMAGE_SIZE);
	561	g_assert(ret == 0);
	562	close(fd);
	563
	564	/* Run the tests */
	565	g_test_init(&argc, &argv, NULL);
	566
b7fcff01	567	qtest_start(NULL);
93e9eb68	568	qtest_irq_intercept_in(global_qtest, "ioapic");
7cd33161 PH	569	qtest_add_func("/fdc/cmos", test_cmos);
7cd33161 PH	570	qtest_add_func("/fdc/no_media_on_start", test_no_media_on_start);
8b9ef60d	571	qtest_add_func("/fdc/read_without_media", test_read_without_media);
93e9eb68	572	qtest_add_func("/fdc/media_change", test_media_change);
b3ce604e	573	qtest_add_func("/fdc/sense_interrupt", test_sense_interrupt);
98272dbb	574	qtest_add_func("/fdc/relative_seek", test_relative_seek);
67f194bd	575	qtest_add_func("/fdc/read_id", test_read_id);
6f442fe8	576	qtest_add_func("/fdc/verify", test_verify);
44212dcc	577	qtest_add_func("/fdc/media_insert", test_media_insert);
5f8ae8e2 HP	578	qtest_add_func("/fdc/read_no_dma_1", test_read_no_dma_1);
	579	qtest_add_func("/fdc/read_no_dma_18", test_read_no_dma_18);
	580	qtest_add_func("/fdc/read_no_dma_19", test_read_no_dma_19);
3359847e	581	qtest_add_func("/fdc/fuzz-registers", fuzz_registers);
93e9eb68 KW	582
	583	ret = g_test_run();
	584
	585	/* Cleanup */
1d9358e6	586	qtest_end();
93e9eb68 KW	587	unlink(test_image);
	588
	589	return ret;
	590	}