[qemu.git] / hw / lm32 / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/block/flash.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/block-backend.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec/address-spaces.h"

typedef struct {
    LM32CPU *cpu;
    hwaddr bootstrap_pc;
    hwaddr flash_base;
    hwaddr hwsetup_base;
    hwaddr initrd_base;
    size_t initrd_size;
    hwaddr cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    LM32CPU *cpu = opaque;
    CPUState *cs = CPU(cpu);

    if (level) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(MachineState *machine)
{
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    hwaddr ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    hwaddr timer0_base = 0x80002000;
    hwaddr uart0_base  = 0x80006000;
    hwaddr timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
        exit(1);
    }

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(MachineState *machine)
{
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    hwaddr ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    hwaddr uart0_base   = 0x80000000;
    hwaddr timer0_base  = 0x80002000;
    hwaddr timer1_base  = 0x80010000;
    hwaddr timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    hwaddr hwsetup_base = 0x0bffe000;
    hwaddr cmdline_base = 0x0bfff000;
    hwaddr initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
        exit(1);
    }

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL,
                                         "lm32_uclinux.sdram", ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_evr_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "LatticeMico32 EVR32 eval system";
    mc->init = lm32_evr_init;
    mc->is_default = 1;
}

static const TypeInfo lm32_evr_type = {
    .name = MACHINE_TYPE_NAME("lm32-evr"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_evr_class_init,
};

static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
    mc->init = lm32_uclinux_init;
    mc->is_default = 0;
}

static const TypeInfo lm32_uclinux_type = {
    .name = MACHINE_TYPE_NAME("lm32-uclinux"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_uclinux_class_init,
};

static void lm32_machine_init(void)
{
    type_register_static(&lm32_evr_type);
    type_register_static(&lm32_uclinux_type);
}

type_init(lm32_machine_init)
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <michael@walle.cc>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
ea99dde1	20	#include "qemu/osdep.h"
4771d756 PB	21	#include "qemu-common.h"
4771d756 PB	22	#include "cpu.h"
83c9f4ca PB	23	#include "hw/sysbus.h"
83c9f4ca PB	24	#include "hw/hw.h"
0d09e41a	25	#include "hw/block/flash.h"
bd2be150	26	#include "hw/devices.h"
83c9f4ca PB	27	#include "hw/boards.h"
83c9f4ca PB	28	#include "hw/loader.h"
fa1d36df	29	#include "sysemu/block-backend.h"
d821732a	30	#include "elf.h"
47b43a1f PB	31	#include "lm32_hwsetup.h"
47b43a1f PB	32	#include "lm32.h"
022c62cb	33	#include "exec/address-spaces.h"
d821732a MW	34
d821732a MW	35	typedef struct {
b1435596	36	LM32CPU *cpu;
a8170e5e AK	37	hwaddr bootstrap_pc;
	38	hwaddr flash_base;
	39	hwaddr hwsetup_base;
	40	hwaddr initrd_base;
d821732a	41	size_t initrd_size;
a8170e5e	42	hwaddr cmdline_base;
d821732a MW	43	} ResetInfo;
	44
	45	static void cpu_irq_handler(void *opaque, int irq, int level)
	46	{
d8ed887b	47	LM32CPU *cpu = opaque;
d8ed887b	48	CPUState *cs = CPU(cpu);
d821732a MW	49
d821732a MW	50	if (level) {
c3affe56	51	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a	52	} else {
d8ed887b	53	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a MW	54	}
	55	}
	56
	57	static void main_cpu_reset(void *opaque)
	58	{
	59	ResetInfo *reset_info = opaque;
b1435596	60	CPULM32State *env = &reset_info->cpu->env;
d821732a	61
b1435596	62	cpu_reset(CPU(reset_info->cpu));
d821732a MW	63
	64	/* init defaults */
	65	env->pc = (uint32_t)reset_info->bootstrap_pc;
	66	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	67	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	68	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	69	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	70	reset_info->initrd_size);
	71	env->eba = reset_info->flash_base;
	72	env->deba = reset_info->flash_base;
	73	}
	74
3ef96221	75	static void lm32_evr_init(MachineState *machine)
d821732a	76	{
3ef96221 MA	77	const char *cpu_model = machine->cpu_model;
3ef96221 MA	78	const char *kernel_filename = machine->kernel_filename;
47dc4fa2	79	LM32CPU *cpu;
93a67402	80	CPULM32State *env;
d821732a	81	DriveInfo *dinfo;
88fa8031 AK	82	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	83	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	84	qemu_irq irq[32];
d821732a MW	85	ResetInfo *reset_info;
	86	int i;
	87
	88	/* memory map */
a8170e5e	89	hwaddr flash_base = 0x04000000;
d821732a MW	90	size_t flash_sector_size = 256 * 1024;
d821732a MW	91	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	92	hwaddr ram_base = 0x08000000;
d821732a	93	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	94	hwaddr timer0_base = 0x80002000;
	95	hwaddr uart0_base = 0x80006000;
	96	hwaddr timer1_base = 0x8000a000;
d821732a MW	97	int uart0_irq = 0;
	98	int timer0_irq = 1;
	99	int timer1_irq = 3;
	100
7267c094	101	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	102
	103	if (cpu_model == NULL) {
	104	cpu_model = "lm32-full";
	105	}
47dc4fa2	106	cpu = cpu_lm32_init(cpu_model);
f41152bd MW	107	if (cpu == NULL) {
	108	fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
	109	exit(1);
	110	}
	111
47dc4fa2	112	env = &cpu->env;
b1435596	113	reset_info->cpu = cpu;
d821732a MW	114
	115	reset_info->flash_base = flash_base;
	116
b7ccb83f DM	117	memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
b7ccb83f DM	118	ram_size);
88fa8031	119	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	120
d821732a MW	121	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	122	/* Spansion S29NS128P */
cfe5f011	123	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
4be74634	124	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	125	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	126	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	127
d821732a MW	128	/* create irq lines */
d4ef00af	129	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
d821732a MW	130	for (i = 0; i < 32; i++) {
	131	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	132	}
	133
	134	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	135	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	136	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	137
	138	/* make sure juart isn't the first chardev */
	139	env->juart_state = lm32_juart_init();
	140
	141	reset_info->bootstrap_pc = flash_base;
	142
	143	if (kernel_filename) {
	144	uint64_t entry;
	145	int kernel_size;
	146
	147	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
7ef295ea	148	1, EM_LATTICEMICO32, 0, 0);
d821732a MW	149	reset_info->bootstrap_pc = entry;
	150
	151	if (kernel_size < 0) {
	152	kernel_size = load_image_targphys(kernel_filename, ram_base,
	153	ram_size);
	154	reset_info->bootstrap_pc = ram_base;
	155	}
	156
	157	if (kernel_size < 0) {
	158	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	159	kernel_filename);
	160	exit(1);
	161	}
	162	}
	163
	164	qemu_register_reset(main_cpu_reset, reset_info);
	165	}
	166
3ef96221	167	static void lm32_uclinux_init(MachineState *machine)
d821732a	168	{
3ef96221 MA	169	const char *cpu_model = machine->cpu_model;
	170	const char *kernel_filename = machine->kernel_filename;
	171	const char *kernel_cmdline = machine->kernel_cmdline;
	172	const char *initrd_filename = machine->initrd_filename;
47dc4fa2	173	LM32CPU *cpu;
93a67402	174	CPULM32State *env;
d821732a	175	DriveInfo *dinfo;
88fa8031 AK	176	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	177	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	178	qemu_irq irq[32];
d821732a MW	179	HWSetup *hw;
	180	ResetInfo *reset_info;
	181	int i;
	182
	183	/* memory map */
a8170e5e	184	hwaddr flash_base = 0x04000000;
d821732a MW	185	size_t flash_sector_size = 256 * 1024;
d821732a MW	186	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	187	hwaddr ram_base = 0x08000000;
d821732a	188	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	189	hwaddr uart0_base = 0x80000000;
	190	hwaddr timer0_base = 0x80002000;
	191	hwaddr timer1_base = 0x80010000;
	192	hwaddr timer2_base = 0x80012000;
d821732a MW	193	int uart0_irq = 0;
	194	int timer0_irq = 1;
	195	int timer1_irq = 20;
	196	int timer2_irq = 21;
a8170e5e AK	197	hwaddr hwsetup_base = 0x0bffe000;
	198	hwaddr cmdline_base = 0x0bfff000;
	199	hwaddr initrd_base = 0x08400000;
d821732a MW	200	size_t initrd_max = 0x01000000;
d821732a MW	201
7267c094	202	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	203
	204	if (cpu_model == NULL) {
	205	cpu_model = "lm32-full";
	206	}
47dc4fa2	207	cpu = cpu_lm32_init(cpu_model);
f41152bd MW	208	if (cpu == NULL) {
	209	fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
	210	exit(1);
	211	}
	212
47dc4fa2	213	env = &cpu->env;
b1435596	214	reset_info->cpu = cpu;
d821732a MW	215
	216	reset_info->flash_base = flash_base;
	217
b7ccb83f DM	218	memory_region_allocate_system_memory(phys_ram, NULL,
b7ccb83f DM	219	"lm32_uclinux.sdram", ram_size);
88fa8031	220	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	221
d821732a MW	222	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	223	/* Spansion S29NS128P */
cfe5f011	224	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
4be74634	225	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	226	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	227	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	228
d821732a MW	229	/* create irq lines */
d4ef00af	230	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
d821732a MW	231	for (i = 0; i < 32; i++) {
	232	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	233	}
	234
	235	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	236	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	237	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	238	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	239
	240	/* make sure juart isn't the first chardev */
	241	env->juart_state = lm32_juart_init();
	242
	243	reset_info->bootstrap_pc = flash_base;
	244
	245	if (kernel_filename) {
	246	uint64_t entry;
	247	int kernel_size;
	248
	249	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
7ef295ea	250	1, EM_LATTICEMICO32, 0, 0);
d821732a MW	251	reset_info->bootstrap_pc = entry;
	252
	253	if (kernel_size < 0) {
	254	kernel_size = load_image_targphys(kernel_filename, ram_base,
	255	ram_size);
	256	reset_info->bootstrap_pc = ram_base;
	257	}
	258
	259	if (kernel_size < 0) {
	260	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	261	kernel_filename);
	262	exit(1);
	263	}
	264	}
	265
	266	/* generate a rom with the hardware description */
	267	hw = hwsetup_init();
	268	hwsetup_add_cpu(hw, "LM32", 75000000);
	269	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	270	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	271	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	272	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	273	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	274	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	275	hwsetup_add_trailer(hw);
	276	hwsetup_create_rom(hw, hwsetup_base);
	277	hwsetup_free(hw);
	278
	279	reset_info->hwsetup_base = hwsetup_base;
	280
	281	if (kernel_cmdline && strlen(kernel_cmdline)) {
	282	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	283	kernel_cmdline);
	284	reset_info->cmdline_base = cmdline_base;
	285	}
	286
	287	if (initrd_filename) {
	288	size_t initrd_size;
	289	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	290	initrd_max);
	291	reset_info->initrd_base = initrd_base;
	292	reset_info->initrd_size = initrd_size;
	293	}
	294
	295	qemu_register_reset(main_cpu_reset, reset_info);
	296	}
	297
8a661aea	298	static void lm32_evr_class_init(ObjectClass oc, void data)
d821732a	299	{
8a661aea AF	300	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	301
e264d29d EH	302	mc->desc = "LatticeMico32 EVR32 eval system";
	303	mc->init = lm32_evr_init;
	304	mc->is_default = 1;
d821732a MW	305	}
d821732a MW	306
8a661aea AF	307	static const TypeInfo lm32_evr_type = {
	308	.name = MACHINE_TYPE_NAME("lm32-evr"),
	309	.parent = TYPE_MACHINE,
	310	.class_init = lm32_evr_class_init,
	311	};
e264d29d	312
8a661aea	313	static void lm32_uclinux_class_init(ObjectClass oc, void data)
e264d29d	314	{
8a661aea AF	315	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	316
e264d29d EH	317	mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
	318	mc->init = lm32_uclinux_init;
	319	mc->is_default = 0;
	320	}
	321
8a661aea AF	322	static const TypeInfo lm32_uclinux_type = {
	323	.name = MACHINE_TYPE_NAME("lm32-uclinux"),
	324	.parent = TYPE_MACHINE,
	325	.class_init = lm32_uclinux_class_init,
	326	};
	327
	328	static void lm32_machine_init(void)
	329	{
	330	type_register_static(&lm32_evr_type);
	331	type_register_static(&lm32_uclinux_type);
	332	}
	333
0e6aac87	334	type_init(lm32_machine_init)