[qemu.git] / target / microblaze / cpu.h

/*
 *  MicroBlaze virtual CPU header
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef MICROBLAZE_CPU_H
#define MICROBLAZE_CPU_H

#include "qemu-common.h"
#include "cpu-qom.h"

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUMBState

#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
struct CPUMBState;
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif

#define EXCP_MMU        1
#define EXCP_IRQ        2
#define EXCP_BREAK      3
#define EXCP_HW_BREAK   4
#define EXCP_HW_EXCP    5

/* MicroBlaze-specific interrupt pending bits.  */
#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3

/* Meanings of the MBCPU object's two inbound GPIO lines */
#define MB_CPU_IRQ 0
#define MB_CPU_FIR 1

/* Register aliases. R0 - R15 */
#define R_SP     1
#define SR_PC    0
#define SR_MSR   1
#define SR_EAR   3
#define SR_ESR   5
#define SR_FSR   7
#define SR_BTR   0xb
#define SR_EDR   0xd

/* MSR flags.  */
#define MSR_BE  (1<<0) /* 0x001 */
#define MSR_IE  (1<<1) /* 0x002 */
#define MSR_C   (1<<2) /* 0x004 */
#define MSR_BIP (1<<3) /* 0x008 */
#define MSR_FSL (1<<4) /* 0x010 */
#define MSR_ICE (1<<5) /* 0x020 */
#define MSR_DZ  (1<<6) /* 0x040 */
#define MSR_DCE (1<<7) /* 0x080 */
#define MSR_EE  (1<<8) /* 0x100 */
#define MSR_EIP (1<<9) /* 0x200 */
#define MSR_PVR (1<<10) /* 0x400 */
#define MSR_CC  (1<<31)

/* Machine State Register (MSR) Fields */
#define MSR_UM (1<<11) /* User Mode */
#define MSR_UMS        (1<<12) /* User Mode Save */
#define MSR_VM (1<<13) /* Virtual Mode */
#define MSR_VMS        (1<<14) /* Virtual Mode Save */

#define MSR_KERNEL      MSR_EE|MSR_VM
//#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
#define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE

/* Exception State Register (ESR) Fields */
#define          ESR_DIZ       (1<<11) /* Zone Protection */
#define          ESR_S         (1<<10) /* Store instruction */

#define          ESR_ESS_FSL_OFFSET     5

#define          ESR_EC_FSL             0
#define          ESR_EC_UNALIGNED_DATA  1
#define          ESR_EC_ILLEGAL_OP      2
#define          ESR_EC_INSN_BUS        3
#define          ESR_EC_DATA_BUS        4
#define          ESR_EC_DIVZERO         5
#define          ESR_EC_FPU             6
#define          ESR_EC_PRIVINSN        7
#define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
#define          ESR_EC_DATA_STORAGE    8
#define          ESR_EC_INSN_STORAGE    9
#define          ESR_EC_DATA_TLB        10
#define          ESR_EC_INSN_TLB        11
#define          ESR_EC_MASK            31

/* Floating Point Status Register (FSR) Bits */
#define FSR_IO          (1<<4) /* Invalid operation */
#define FSR_DZ          (1<<3) /* Divide-by-zero */
#define FSR_OF          (1<<2) /* Overflow */
#define FSR_UF          (1<<1) /* Underflow */
#define FSR_DO          (1<<0) /* Denormalized operand error */

/* Version reg.  */
/* Basic PVR mask */
#define PVR0_PVR_FULL_MASK              0x80000000
#define PVR0_USE_BARREL_MASK            0x40000000
#define PVR0_USE_DIV_MASK               0x20000000
#define PVR0_USE_HW_MUL_MASK            0x10000000
#define PVR0_USE_FPU_MASK               0x08000000
#define PVR0_USE_EXC_MASK               0x04000000
#define PVR0_USE_ICACHE_MASK            0x02000000
#define PVR0_USE_DCACHE_MASK            0x01000000
#define PVR0_USE_MMU_MASK               0x00800000
#define PVR0_USE_BTC			0x00400000
#define PVR0_ENDI_MASK                  0x00200000
#define PVR0_FAULT			0x00100000
#define PVR0_VERSION_MASK               0x0000FF00
#define PVR0_USER1_MASK                 0x000000FF
#define PVR0_SPROT_MASK                 0x00000001

#define PVR0_VERSION_SHIFT              8

/* User 2 PVR mask */
#define PVR1_USER2_MASK                 0xFFFFFFFF

/* Configuration PVR masks */
#define PVR2_D_OPB_MASK                 0x80000000
#define PVR2_D_LMB_MASK                 0x40000000
#define PVR2_I_OPB_MASK                 0x20000000
#define PVR2_I_LMB_MASK                 0x10000000
#define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
#define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
#define PVR2_D_PLB_MASK                 0x02000000      /* new */
#define PVR2_I_PLB_MASK                 0x01000000      /* new */
#define PVR2_INTERCONNECT               0x00800000      /* new */
#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
#define PVR2_USE_FSL_EXC                0x00040000      /* new */
#define PVR2_USE_MSR_INSTR              0x00020000
#define PVR2_USE_PCMP_INSTR             0x00010000
#define PVR2_AREA_OPTIMISED             0x00008000
#define PVR2_USE_BARREL_MASK            0x00004000
#define PVR2_USE_DIV_MASK               0x00002000
#define PVR2_USE_HW_MUL_MASK            0x00001000
#define PVR2_USE_FPU_MASK               0x00000800
#define PVR2_USE_MUL64_MASK             0x00000400
#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
#define PVR2_USE_IPLBEXC                0x00000100
#define PVR2_USE_DPLBEXC                0x00000080
#define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
#define PVR2_UNALIGNED_EXC_MASK         0x00000020
#define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
#define PVR2_IOPB_BUS_EXC_MASK          0x00000008
#define PVR2_DOPB_BUS_EXC_MASK          0x00000004
#define PVR2_DIV_ZERO_EXC_MASK          0x00000002
#define PVR2_FPU_EXC_MASK               0x00000001

/* Debug and exception PVR masks */
#define PVR3_DEBUG_ENABLED_MASK         0x80000000
#define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define PVR3_FSL_LINKS_MASK             0x00000380

/* ICache config PVR masks */
#define PVR4_USE_ICACHE_MASK            0x80000000
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000

/* DCache config PVR masks */
#define PVR5_USE_DCACHE_MASK            0x80000000
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
#define PVR5_DCACHE_WRITEBACK_MASK      0x00004000

/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF

/* ICache high address PVR mask */
#define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF

/* DCache base address PVR mask */
#define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF

/* DCache high address PVR mask */
#define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF

/* Target family PVR mask */
#define PVR10_TARGET_FAMILY_MASK        0xFF000000

/* MMU descrtiption */
#define PVR11_USE_MMU                   0xC0000000
#define PVR11_MMU_ITLB_SIZE             0x38000000
#define PVR11_MMU_DTLB_SIZE             0x07000000
#define PVR11_MMU_TLB_ACCESS            0x00C00000
#define PVR11_MMU_ZONES                 0x003E0000
/* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF

#define C_PVR_NONE                      0
#define C_PVR_BASIC                     1
#define C_PVR_FULL                      2

/* CPU flags.  */

/* Condition codes.  */
#define CC_GE  5
#define CC_GT  4
#define CC_LE  3
#define CC_LT  2
#define CC_NE  1
#define CC_EQ  0

#define NB_MMU_MODES    3

#define STREAM_EXCEPTION (1 << 0)
#define STREAM_ATOMIC    (1 << 1)
#define STREAM_TEST      (1 << 2)
#define STREAM_CONTROL   (1 << 3)
#define STREAM_NONBLOCK  (1 << 4)

struct CPUMBState {
    uint32_t debug;
    uint32_t btaken;
    uint32_t btarget;
    uint32_t bimm;

    uint32_t imm;
    uint32_t regs[33];
    uint32_t sregs[24];
    float_status fp_status;
    /* Stack protectors. Yes, it's a hw feature.  */
    uint32_t slr, shr;

    /* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
    uint32_t res_addr;
    uint32_t res_val;

    /* Internal flags.  */
#define IMM_FLAG	4
#define MSR_EE_FLAG     (1 << 8)
#define DRTI_FLAG	(1 << 16)
#define DRTE_FLAG	(1 << 17)
#define DRTB_FLAG	(1 << 18)
#define D_FLAG		(1 << 19)  /* Bit in ESR.  */
/* TB dependent CPUMBState.  */
#define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
    uint32_t iflags;

#if !defined(CONFIG_USER_ONLY)
    /* Unified MMU.  */
    struct microblaze_mmu mmu;
#endif

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    CPU_COMMON

    /* These fields are preserved on reset.  */

    struct {
        uint32_t regs[16];
    } pvr;
};

/**
 * MicroBlazeCPU:
 * @env: #CPUMBState
 *
 * A MicroBlaze CPU.
 */
struct MicroBlazeCPU {
    /*< private >*/
    CPUState parent_obj;

    /*< public >*/

    /* Microblaze Configuration Settings */
    struct {
        bool stackprot;
        uint32_t base_vectors;
        uint8_t use_fpu;
        bool use_barrel;
        bool use_div;
        bool use_mmu;
        bool dcache_writeback;
        bool endi;
        char *version;
        uint8_t pvr;
    } cfg;

    CPUMBState env;
};

static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
{
    return container_of(env, MicroBlazeCPU, env);
}

#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))

#define ENV_OFFSET offsetof(MicroBlazeCPU, env)

void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
                       int flags);
hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void mb_tcg_init(void);
MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_mb_signal_handler(int host_signum, void *pinfo,
                          void *puc);

/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
#define TARGET_PAGE_BITS 12

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))

#define cpu_signal_handler cpu_mb_signal_handler

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _user
#define MMU_NOMMU_IDX   0
#define MMU_KERNEL_IDX  1
#define MMU_USER_IDX    2
/* See NB_MMU_MODES further up the file.  */

static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
{
        /* Are we in nommu mode?.  */
        if (!(env->sregs[SR_MSR] & MSR_VM))
            return MMU_NOMMU_IDX;

	if (env->sregs[SR_MSR] & MSR_UM)
            return MMU_USER_IDX;
        return MMU_KERNEL_IDX;
}

int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
                            int mmu_idx);

#include "exec/cpu-all.h"

static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->sregs[SR_PC];
    *cs_base = 0;
    *flags = (env->iflags & IFLAGS_TB_MASK) |
                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
}

#if !defined(CONFIG_USER_ONLY)
void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size);
#endif

#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze virtual CPU header
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba	18	*/
07f5a258 MA	19
	20	#ifndef MICROBLAZE_CPU_H
	21	#define MICROBLAZE_CPU_H
4acb54ba	22
94598c1d	23	#include "qemu-common.h"
ffa3a3c6	24	#include "cpu-qom.h"
94598c1d	25
4acb54ba EI	26	#define TARGET_LONG_BITS 32
4acb54ba EI	27
9349b4f9	28	#define CPUArchState struct CPUMBState
4acb54ba	29
022c62cb	30	#include "exec/cpu-defs.h"
6b4c305c	31	#include "fpu/softfloat.h"
4acb54ba	32	struct CPUMBState;
9b9a970a	33	typedef struct CPUMBState CPUMBState;
4acb54ba EI	34	#if !defined(CONFIG_USER_ONLY)
	35	#include "mmu.h"
	36	#endif
	37
2161be35 MT	38	#define EXCP_MMU 1
	39	#define EXCP_IRQ 2
	40	#define EXCP_BREAK 3
	41	#define EXCP_HW_BREAK 4
	42	#define EXCP_HW_EXCP 5
4acb54ba	43
85097db6 RH	44	/* MicroBlaze-specific interrupt pending bits. */
	45	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
	46
73c69456 AF	47	/* Meanings of the MBCPU object's two inbound GPIO lines */
	48	#define MB_CPU_IRQ 0
	49	#define MB_CPU_FIR 1
	50
4acb54ba EI	51	/* Register aliases. R0 - R15 */
	52	#define R_SP 1
	53	#define SR_PC 0
	54	#define SR_MSR 1
	55	#define SR_EAR 3
	56	#define SR_ESR 5
	57	#define SR_FSR 7
	58	#define SR_BTR 0xb
	59	#define SR_EDR 0xd
	60
	61	/* MSR flags. */
	62	#define MSR_BE (1<<0) /* 0x001 */
	63	#define MSR_IE (1<<1) /* 0x002 */
	64	#define MSR_C (1<<2) /* 0x004 */
	65	#define MSR_BIP (1<<3) /* 0x008 */
	66	#define MSR_FSL (1<<4) /* 0x010 */
	67	#define MSR_ICE (1<<5) /* 0x020 */
	68	#define MSR_DZ (1<<6) /* 0x040 */
	69	#define MSR_DCE (1<<7) /* 0x080 */
	70	#define MSR_EE (1<<8) /* 0x100 */
	71	#define MSR_EIP (1<<9) /* 0x200 */
8a84fc6b	72	#define MSR_PVR (1<<10) /* 0x400 */
4acb54ba EI	73	#define MSR_CC (1<<31)
	74
	75	/* Machine State Register (MSR) Fields */
	76	#define MSR_UM (1<<11) /* User Mode */
	77	#define MSR_UMS (1<<12) /* User Mode Save */
	78	#define MSR_VM (1<<13) /* Virtual Mode */
	79	#define MSR_VMS (1<<14) /* Virtual Mode Save */
	80
	81	#define MSR_KERNEL MSR_EE\|MSR_VM
	82	//#define MSR_USER MSR_KERNEL\|MSR_UM\|MSR_IE
	83	#define MSR_KERNEL_VMS MSR_EE\|MSR_VMS
	84	//#define MSR_USER_VMS MSR_KERNEL_VMS\|MSR_UMS\|MSR_IE
	85
	86	/* Exception State Register (ESR) Fields */
	87	#define ESR_DIZ (1<<11) /* Zone Protection */
	88	#define ESR_S (1<<10) /* Store instruction */
	89
85453641 EI	90	#define ESR_ESS_FSL_OFFSET 5
85453641 EI	91
cedb936b EI	92	#define ESR_EC_FSL 0
	93	#define ESR_EC_UNALIGNED_DATA 1
	94	#define ESR_EC_ILLEGAL_OP 2
	95	#define ESR_EC_INSN_BUS 3
	96	#define ESR_EC_DATA_BUS 4
	97	#define ESR_EC_DIVZERO 5
	98	#define ESR_EC_FPU 6
	99	#define ESR_EC_PRIVINSN 7
5818dee5	100	#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
cedb936b EI	101	#define ESR_EC_DATA_STORAGE 8
	102	#define ESR_EC_INSN_STORAGE 9
	103	#define ESR_EC_DATA_TLB 10
	104	#define ESR_EC_INSN_TLB 11
3b584046	105	#define ESR_EC_MASK 31
4acb54ba	106
bdc0bf29 EI	107	/* Floating Point Status Register (FSR) Bits */
	108	#define FSR_IO (1<<4) /* Invalid operation */
	109	#define FSR_DZ (1<<3) /* Divide-by-zero */
	110	#define FSR_OF (1<<2) /* Overflow */
	111	#define FSR_UF (1<<1) /* Underflow */
	112	#define FSR_DO (1<<0) /* Denormalized operand error */
	113
4acb54ba EI	114	/* Version reg. */
	115	/* Basic PVR mask */
	116	#define PVR0_PVR_FULL_MASK 0x80000000
	117	#define PVR0_USE_BARREL_MASK 0x40000000
	118	#define PVR0_USE_DIV_MASK 0x20000000
	119	#define PVR0_USE_HW_MUL_MASK 0x10000000
	120	#define PVR0_USE_FPU_MASK 0x08000000
	121	#define PVR0_USE_EXC_MASK 0x04000000
	122	#define PVR0_USE_ICACHE_MASK 0x02000000
	123	#define PVR0_USE_DCACHE_MASK 0x01000000
71446123	124	#define PVR0_USE_MMU_MASK 0x00800000
c4374bb7	125	#define PVR0_USE_BTC 0x00400000
a88bbb00	126	#define PVR0_ENDI_MASK 0x00200000
c4374bb7	127	#define PVR0_FAULT 0x00100000
4acb54ba EI	128	#define PVR0_VERSION_MASK 0x0000FF00
4acb54ba EI	129	#define PVR0_USER1_MASK 0x000000FF
9aaaa181	130	#define PVR0_SPROT_MASK 0x00000001
4acb54ba	131
79549c99 EI	132	#define PVR0_VERSION_SHIFT 8
79549c99 EI	133
4acb54ba EI	134	/* User 2 PVR mask */
	135	#define PVR1_USER2_MASK 0xFFFFFFFF
	136
	137	/* Configuration PVR masks */
	138	#define PVR2_D_OPB_MASK 0x80000000
	139	#define PVR2_D_LMB_MASK 0x40000000
	140	#define PVR2_I_OPB_MASK 0x20000000
	141	#define PVR2_I_LMB_MASK 0x10000000
	142	#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
	143	#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
	144	#define PVR2_D_PLB_MASK 0x02000000 /* new */
	145	#define PVR2_I_PLB_MASK 0x01000000 /* new */
	146	#define PVR2_INTERCONNECT 0x00800000 /* new */
	147	#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
	148	#define PVR2_USE_FSL_EXC 0x00040000 /* new */
	149	#define PVR2_USE_MSR_INSTR 0x00020000
	150	#define PVR2_USE_PCMP_INSTR 0x00010000
	151	#define PVR2_AREA_OPTIMISED 0x00008000
	152	#define PVR2_USE_BARREL_MASK 0x00004000
	153	#define PVR2_USE_DIV_MASK 0x00002000
	154	#define PVR2_USE_HW_MUL_MASK 0x00001000
	155	#define PVR2_USE_FPU_MASK 0x00000800
	156	#define PVR2_USE_MUL64_MASK 0x00000400
	157	#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
	158	#define PVR2_USE_IPLBEXC 0x00000100
	159	#define PVR2_USE_DPLBEXC 0x00000080
	160	#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
	161	#define PVR2_UNALIGNED_EXC_MASK 0x00000020
	162	#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
	163	#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
	164	#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
	165	#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
	166	#define PVR2_FPU_EXC_MASK 0x00000001
	167
	168	/* Debug and exception PVR masks */
	169	#define PVR3_DEBUG_ENABLED_MASK 0x80000000
	170	#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
	171	#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
	172	#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
	173	#define PVR3_FSL_LINKS_MASK 0x00000380
	174
	175	/* ICache config PVR masks */
	176	#define PVR4_USE_ICACHE_MASK 0x80000000
	177	#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
	178	#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
	179	#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
	180	#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
	181	#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
	182
	183	/* DCache config PVR masks */
	184	#define PVR5_USE_DCACHE_MASK 0x80000000
	185	#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
	186	#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
	187	#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
	188	#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
	189	#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
c4374bb7	190	#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
4acb54ba EI	191
	192	/* ICache base address PVR mask */
	193	#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
	194
	195	/* ICache high address PVR mask */
	196	#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
	197
	198	/* DCache base address PVR mask */
	199	#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
	200
	201	/* DCache high address PVR mask */
	202	#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
	203
	204	/* Target family PVR mask */
	205	#define PVR10_TARGET_FAMILY_MASK 0xFF000000
	206
	207	/* MMU descrtiption */
	208	#define PVR11_USE_MMU 0xC0000000
	209	#define PVR11_MMU_ITLB_SIZE 0x38000000
	210	#define PVR11_MMU_DTLB_SIZE 0x07000000
	211	#define PVR11_MMU_TLB_ACCESS 0x00C00000
7458a432	212	#define PVR11_MMU_ZONES 0x003E0000
4acb54ba EI	213	/* MSR Reset value PVR mask */
	214	#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
	215
6fad9e98 AF	216	#define C_PVR_NONE 0
	217	#define C_PVR_BASIC 1
	218	#define C_PVR_FULL 2
4acb54ba EI	219
	220	/* CPU flags. */
	221
	222	/* Condition codes. */
	223	#define CC_GE 5
	224	#define CC_GT 4
	225	#define CC_LE 3
	226	#define CC_LT 2
	227	#define CC_NE 1
	228	#define CC_EQ 0
	229
	230	#define NB_MMU_MODES 3
85453641 EI	231
	232	#define STREAM_EXCEPTION (1 << 0)
	233	#define STREAM_ATOMIC (1 << 1)
	234	#define STREAM_TEST (1 << 2)
	235	#define STREAM_CONTROL (1 << 3)
	236	#define STREAM_NONBLOCK (1 << 4)
	237
ae7d54d4	238	struct CPUMBState {
4acb54ba EI	239	uint32_t debug;
	240	uint32_t btaken;
	241	uint32_t btarget;
	242	uint32_t bimm;
	243
	244	uint32_t imm;
	245	uint32_t regs[33];
	246	uint32_t sregs[24];
97694c57	247	float_status fp_status;
5818dee5 EI	248	/* Stack protectors. Yes, it's a hw feature. */
5818dee5 EI	249	uint32_t slr, shr;
4acb54ba	250
8cc9b43f PC	251	/* lwx/swx reserved address */
	252	#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
	253	uint32_t res_addr;
11a76217	254	uint32_t res_val;
8cc9b43f	255
4acb54ba	256	/* Internal flags. */
cedb936b EI	257	#define IMM_FLAG 4
cedb936b EI	258	#define MSR_EE_FLAG (1 << 8)
4acb54ba EI	259	#define DRTI_FLAG (1 << 16)
	260	#define DRTE_FLAG (1 << 17)
	261	#define DRTB_FLAG (1 << 18)
	262	#define D_FLAG (1 << 19) /* Bit in ESR. */
68cee38a	263	/* TB dependent CPUMBState. */
fd1dc858	264	#define IFLAGS_TB_MASK (D_FLAG \| IMM_FLAG \| DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)
4acb54ba EI	265	uint32_t iflags;
4acb54ba EI	266
4acb54ba EI	267	#if !defined(CONFIG_USER_ONLY)
	268	/* Unified MMU. */
	269	struct microblaze_mmu mmu;
	270	#endif
	271
1f5c00cf AB	272	/* Fields up to this point are cleared by a CPU reset */
	273	struct {} end_reset_fields;
	274
4acb54ba	275	CPU_COMMON
8bac2242 AF	276
	277	/* These fields are preserved on reset. */
	278
	279	struct {
	280	uint32_t regs[16];
	281	} pvr;
ae7d54d4	282	};
4acb54ba	283
ffa3a3c6 PB	284	/**
	285	* MicroBlazeCPU:
	286	* @env: #CPUMBState
	287	*
	288	* A MicroBlaze CPU.
	289	*/
	290	struct MicroBlazeCPU {
	291	/< private >/
	292	CPUState parent_obj;
	293
	294	/< public >/
	295
	296	/* Microblaze Configuration Settings */
	297	struct {
	298	bool stackprot;
	299	uint32_t base_vectors;
	300	uint8_t use_fpu;
7faa66aa	301	bool use_barrel;
47709e4c	302	bool use_div;
ffa3a3c6 PB	303	bool use_mmu;
	304	bool dcache_writeback;
	305	bool endi;
	306	char *version;
	307	uint8_t pvr;
	308	} cfg;
	309
	310	CPUMBState env;
	311	};
	312
	313	static inline MicroBlazeCPU mb_env_get_cpu(CPUMBState env)
	314	{
	315	return container_of(env, MicroBlazeCPU, env);
	316	}
	317
	318	#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
	319
	320	#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
	321
	322	void mb_cpu_do_interrupt(CPUState *cs);
	323	bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
	324	void mb_cpu_dump_state(CPUState cpu, FILE f, fprintf_function cpu_fprintf,
	325	int flags);
	326	hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	327	int mb_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	328	int mb_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
b77f98ca	329
cd0c24f9	330	void mb_tcg_init(void);
b33ab1f7	331	MicroBlazeCPU cpu_mb_init(const char cpu_model);
4acb54ba EI	332	/* you can call this signal handler from your SIGBUS and SIGSEGV
	333	signal handlers to inform the virtual CPU of exceptions. non zero
	334	is returned if the signal was handled by the virtual CPU. */
	335	int cpu_mb_signal_handler(int host_signum, void *pinfo,
	336	void *puc);
	337
4acb54ba EI	338	/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
4acb54ba EI	339	#define TARGET_PAGE_BITS 12
4acb54ba	340
52705890 RH	341	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	342	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	343
2994fd96	344	#define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
b33ab1f7	345
4acb54ba EI	346	#define cpu_signal_handler cpu_mb_signal_handler
4acb54ba EI	347
4acb54ba EI	348	/* MMU modes definitions */
	349	#define MMU_MODE0_SUFFIX _nommu
	350	#define MMU_MODE1_SUFFIX _kernel
	351	#define MMU_MODE2_SUFFIX _user
	352	#define MMU_NOMMU_IDX 0
	353	#define MMU_KERNEL_IDX 1
	354	#define MMU_USER_IDX 2
	355	/* See NB_MMU_MODES further up the file. */
	356
97ed5ccd	357	static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
4acb54ba EI	358	{
	359	/* Are we in nommu mode?. */
	360	if (!(env->sregs[SR_MSR] & MSR_VM))
	361	return MMU_NOMMU_IDX;
	362
	363	if (env->sregs[SR_MSR] & MSR_UM)
	364	return MMU_USER_IDX;
	365	return MMU_KERNEL_IDX;
	366	}
	367
7510454e	368	int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
97b348e7	369	int mmu_idx);
4acb54ba	370
022c62cb	371	#include "exec/cpu-all.h"
4acb54ba	372
68cee38a	373	static inline void cpu_get_tb_cpu_state(CPUMBState env, target_ulong pc,
89fee74a	374	target_ulong cs_base, uint32_t flags)
4acb54ba EI	375	{
	376	*pc = env->sregs[SR_PC];
	377	*cs_base = 0;
fd1dc858 EI	378	*flags = (env->iflags & IFLAGS_TB_MASK) \|
fd1dc858 EI	379	(env->sregs[SR_MSR] & (MSR_UM \| MSR_VM \| MSR_EE));
4acb54ba	380	}
faed1c2a	381
3c7b48b7	382	#if !defined(CONFIG_USER_ONLY)
c658b94f AF	383	void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
	384	bool is_write, bool is_exec, int is_asi,
	385	unsigned size);
4acb54ba	386	#endif
f081c76c	387
3c7b48b7	388	#endif