[qemu.git] / tcg / i386 / tcg-target.h

/*
 * Tiny Code Generator for QEMU
 *
 * Copyright (c) 2008 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#define TCG_TARGET_I386 1

//#define TCG_TARGET_WORDS_BIGENDIAN

#if TCG_TARGET_REG_BITS == 64
# define TCG_TARGET_NB_REGS 16
#else
# define TCG_TARGET_NB_REGS 8
#endif

typedef enum {
    TCG_REG_EAX = 0,
    TCG_REG_ECX,
    TCG_REG_EDX,
    TCG_REG_EBX,
    TCG_REG_ESP,
    TCG_REG_EBP,
    TCG_REG_ESI,
    TCG_REG_EDI,

    /* 64-bit registers; always define the symbols to avoid
       too much if-deffing.  */
    TCG_REG_R8,
    TCG_REG_R9,
    TCG_REG_R10,
    TCG_REG_R11,
    TCG_REG_R12,
    TCG_REG_R13,
    TCG_REG_R14,
    TCG_REG_R15,
    TCG_REG_RAX = TCG_REG_EAX,
    TCG_REG_RCX = TCG_REG_ECX,
    TCG_REG_RDX = TCG_REG_EDX,
    TCG_REG_RBX = TCG_REG_EBX,
    TCG_REG_RSP = TCG_REG_ESP,
    TCG_REG_RBP = TCG_REG_EBP,
    TCG_REG_RSI = TCG_REG_ESI,
    TCG_REG_RDI = TCG_REG_EDI,
} TCGReg;

#define TCG_CT_CONST_S32 0x100
#define TCG_CT_CONST_U32 0x200

/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_ESP 
#define TCG_TARGET_STACK_ALIGN 16
#define TCG_TARGET_CALL_STACK_OFFSET 0

/* optional instructions */
#define TCG_TARGET_HAS_div2_i32         1
#define TCG_TARGET_HAS_rot_i32          1
#define TCG_TARGET_HAS_ext8s_i32        1
#define TCG_TARGET_HAS_ext16s_i32       1
#define TCG_TARGET_HAS_ext8u_i32        1
#define TCG_TARGET_HAS_ext16u_i32       1
#define TCG_TARGET_HAS_bswap16_i32      1
#define TCG_TARGET_HAS_bswap32_i32      1
#define TCG_TARGET_HAS_neg_i32          1
#define TCG_TARGET_HAS_not_i32          1
#define TCG_TARGET_HAS_andc_i32         0
#define TCG_TARGET_HAS_orc_i32          0
#define TCG_TARGET_HAS_eqv_i32          0
#define TCG_TARGET_HAS_nand_i32         0
#define TCG_TARGET_HAS_nor_i32          0
#define TCG_TARGET_HAS_deposit_i32      1

#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div2_i64         1
#define TCG_TARGET_HAS_rot_i64          1
#define TCG_TARGET_HAS_ext8s_i64        1
#define TCG_TARGET_HAS_ext16s_i64       1
#define TCG_TARGET_HAS_ext32s_i64       1
#define TCG_TARGET_HAS_ext8u_i64        1
#define TCG_TARGET_HAS_ext16u_i64       1
#define TCG_TARGET_HAS_ext32u_i64       1
#define TCG_TARGET_HAS_bswap16_i64      1
#define TCG_TARGET_HAS_bswap32_i64      1
#define TCG_TARGET_HAS_bswap64_i64      1
#define TCG_TARGET_HAS_neg_i64          1
#define TCG_TARGET_HAS_not_i64          1
#define TCG_TARGET_HAS_andc_i64         0
#define TCG_TARGET_HAS_orc_i64          0
#define TCG_TARGET_HAS_eqv_i64          0
#define TCG_TARGET_HAS_nand_i64         0
#define TCG_TARGET_HAS_nor_i64          0
#define TCG_TARGET_HAS_deposit_i64      1
#endif

#define TCG_TARGET_deposit_i32_valid(ofs, len) \
    (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
     ((ofs) == 0 && (len) == 16))
#define TCG_TARGET_deposit_i64_valid    TCG_TARGET_deposit_i32_valid

#define TCG_TARGET_HAS_GUEST_BASE

/* Note: must be synced with dyngen-exec.h */
#if TCG_TARGET_REG_BITS == 64
# define TCG_AREG0 TCG_REG_R14
#else
# define TCG_AREG0 TCG_REG_EBP
#endif

static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
}
Commit	Line	Data
c896fe29 FB	1	/*
	2	* Tiny Code Generator for QEMU
	3	*
	4	* Copyright (c) 2008 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#define TCG_TARGET_I386 1
	25
c896fe29 FB	26	//#define TCG_TARGET_WORDS_BIGENDIAN
c896fe29 FB	27
5d8a4f8f RH	28	#if TCG_TARGET_REG_BITS == 64
	29	# define TCG_TARGET_NB_REGS 16
	30	#else
	31	# define TCG_TARGET_NB_REGS 8
	32	#endif
c896fe29	33
771142c2	34	typedef enum {
c896fe29 FB	35	TCG_REG_EAX = 0,
	36	TCG_REG_ECX,
	37	TCG_REG_EDX,
	38	TCG_REG_EBX,
	39	TCG_REG_ESP,
	40	TCG_REG_EBP,
	41	TCG_REG_ESI,
	42	TCG_REG_EDI,
5d8a4f8f RH	43
	44	/* 64-bit registers; always define the symbols to avoid
	45	too much if-deffing. */
	46	TCG_REG_R8,
	47	TCG_REG_R9,
	48	TCG_REG_R10,
	49	TCG_REG_R11,
	50	TCG_REG_R12,
	51	TCG_REG_R13,
	52	TCG_REG_R14,
	53	TCG_REG_R15,
	54	TCG_REG_RAX = TCG_REG_EAX,
	55	TCG_REG_RCX = TCG_REG_ECX,
	56	TCG_REG_RDX = TCG_REG_EDX,
	57	TCG_REG_RBX = TCG_REG_EBX,
	58	TCG_REG_RSP = TCG_REG_ESP,
	59	TCG_REG_RBP = TCG_REG_EBP,
	60	TCG_REG_RSI = TCG_REG_ESI,
	61	TCG_REG_RDI = TCG_REG_EDI,
771142c2	62	} TCGReg;
c896fe29	63
5d8a4f8f RH	64	#define TCG_CT_CONST_S32 0x100
	65	#define TCG_CT_CONST_U32 0x200
	66
c896fe29 FB	67	/* used for function call generation */
	68	#define TCG_REG_CALL_STACK TCG_REG_ESP
	69	#define TCG_TARGET_STACK_ALIGN 16
39cf05d3	70	#define TCG_TARGET_CALL_STACK_OFFSET 0
c896fe29	71
9619376c	72	/* optional instructions */
25c4d9cc RH	73	#define TCG_TARGET_HAS_div2_i32 1
	74	#define TCG_TARGET_HAS_rot_i32 1
	75	#define TCG_TARGET_HAS_ext8s_i32 1
	76	#define TCG_TARGET_HAS_ext16s_i32 1
	77	#define TCG_TARGET_HAS_ext8u_i32 1
	78	#define TCG_TARGET_HAS_ext16u_i32 1
	79	#define TCG_TARGET_HAS_bswap16_i32 1
	80	#define TCG_TARGET_HAS_bswap32_i32 1
	81	#define TCG_TARGET_HAS_neg_i32 1
	82	#define TCG_TARGET_HAS_not_i32 1
	83	#define TCG_TARGET_HAS_andc_i32 0
	84	#define TCG_TARGET_HAS_orc_i32 0
	85	#define TCG_TARGET_HAS_eqv_i32 0
	86	#define TCG_TARGET_HAS_nand_i32 0
	87	#define TCG_TARGET_HAS_nor_i32 0
a4773324	88	#define TCG_TARGET_HAS_deposit_i32 1
9619376c	89
5d8a4f8f	90	#if TCG_TARGET_REG_BITS == 64
25c4d9cc RH	91	#define TCG_TARGET_HAS_div2_i64 1
	92	#define TCG_TARGET_HAS_rot_i64 1
	93	#define TCG_TARGET_HAS_ext8s_i64 1
	94	#define TCG_TARGET_HAS_ext16s_i64 1
	95	#define TCG_TARGET_HAS_ext32s_i64 1
	96	#define TCG_TARGET_HAS_ext8u_i64 1
	97	#define TCG_TARGET_HAS_ext16u_i64 1
	98	#define TCG_TARGET_HAS_ext32u_i64 1
	99	#define TCG_TARGET_HAS_bswap16_i64 1
	100	#define TCG_TARGET_HAS_bswap32_i64 1
	101	#define TCG_TARGET_HAS_bswap64_i64 1
	102	#define TCG_TARGET_HAS_neg_i64 1
	103	#define TCG_TARGET_HAS_not_i64 1
	104	#define TCG_TARGET_HAS_andc_i64 0
	105	#define TCG_TARGET_HAS_orc_i64 0
	106	#define TCG_TARGET_HAS_eqv_i64 0
	107	#define TCG_TARGET_HAS_nand_i64 0
	108	#define TCG_TARGET_HAS_nor_i64 0
a4773324	109	#define TCG_TARGET_HAS_deposit_i64 1
5d8a4f8f RH	110	#endif
5d8a4f8f RH	111
a4773324 JK	112	#define TCG_TARGET_deposit_i32_valid(ofs, len) \
	113	(((ofs) == 0 && (len) == 8) \|\| ((ofs) == 8 && (len) == 8) \|\| \
	114	((ofs) == 0 && (len) == 16))
	115	#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
	116
379f6698 PB	117	#define TCG_TARGET_HAS_GUEST_BASE
379f6698 PB	118
c896fe29	119	/* Note: must be synced with dyngen-exec.h */
5d8a4f8f RH	120	#if TCG_TARGET_REG_BITS == 64
	121	# define TCG_AREG0 TCG_REG_R14
	122	#else
	123	# define TCG_AREG0 TCG_REG_EBP
	124	#endif
c896fe29 FB	125
	126	static inline void flush_icache_range(unsigned long start, unsigned long stop)
	127	{
	128	}