[qemu.git] / target-mips / kvm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * KVM/MIPS: MIPS specific KVM APIs
 *
 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
 * Authors: Sanjay Lal <[email protected]>
*/

#include "qemu/osdep.h"
#include <sys/ioctl.h>
#include <sys/mman.h>

#include <linux/kvm.h>

#include "qemu-common.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "cpu.h"
#include "sysemu/cpus.h"
#include "kvm_mips.h"
#include "exec/memattrs.h"

#define DEBUG_KVM 0

#define DPRINTF(fmt, ...) \
    do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)

const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
    KVM_CAP_LAST_INFO
};

static void kvm_mips_update_state(void *opaque, int running, RunState state);

unsigned long kvm_arch_vcpu_id(CPUState *cs)
{
    return cs->cpu_index;
}

int kvm_arch_init(MachineState *ms, KVMState *s)
{
    /* MIPS has 128 signals */
    kvm_set_sigmask_len(s, 16);

    DPRINTF("%s\n", __func__);
    return 0;
}

int kvm_arch_init_vcpu(CPUState *cs)
{
    int ret = 0;

    qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);

    DPRINTF("%s\n", __func__);
    return ret;
}

void kvm_mips_reset_vcpu(MIPSCPU *cpu)
{
    CPUMIPSState *env = &cpu->env;

    if (env->CP0_Config1 & (1 << CP0C1_FP)) {
        fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
        env->CP0_Config1 &= ~(1 << CP0C1_FP);
    }

    DPRINTF("%s\n", __func__);
}

int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
    DPRINTF("%s\n", __func__);
    return 0;
}

int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
    DPRINTF("%s\n", __func__);
    return 0;
}

static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
{
    CPUMIPSState *env = &cpu->env;

    return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
}


void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    int r;
    struct kvm_mips_interrupt intr;

    qemu_mutex_lock_iothread();

    if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
            cpu_mips_io_interrupts_pending(cpu)) {
        intr.cpu = -1;
        intr.irq = 2;
        r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
        if (r < 0) {
            error_report("%s: cpu %d: failed to inject IRQ %x",
                         __func__, cs->cpu_index, intr.irq);
        }
    }

    qemu_mutex_unlock_iothread();
}

MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
{
    return MEMTXATTRS_UNSPECIFIED;
}

int kvm_arch_process_async_events(CPUState *cs)
{
    return cs->halted;
}

int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
    int ret;

    DPRINTF("%s\n", __func__);
    switch (run->exit_reason) {
    default:
        error_report("%s: unknown exit reason %d",
                     __func__, run->exit_reason);
        ret = -1;
        break;
    }

    return ret;
}

bool kvm_arch_stop_on_emulation_error(CPUState *cs)
{
    DPRINTF("%s\n", __func__);
    return true;
}

int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
{
    DPRINTF("%s\n", __func__);
    return 1;
}

int kvm_arch_on_sigbus(int code, void *addr)
{
    DPRINTF("%s\n", __func__);
    return 1;
}

void kvm_arch_init_irq_routing(KVMState *s)
{
}

int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
{
    CPUState *cs = CPU(cpu);
    struct kvm_mips_interrupt intr;

    if (!kvm_enabled()) {
        return 0;
    }

    intr.cpu = -1;

    if (level) {
        intr.irq = irq;
    } else {
        intr.irq = -irq;
    }

    kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);

    return 0;
}

int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
{
    CPUState *cs = current_cpu;
    CPUState *dest_cs = CPU(cpu);
    struct kvm_mips_interrupt intr;

    if (!kvm_enabled()) {
        return 0;
    }

    intr.cpu = dest_cs->cpu_index;

    if (level) {
        intr.irq = irq;
    } else {
        intr.irq = -irq;
    }

    DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);

    kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);

    return 0;
}

#define MIPS_CP0_32(_R, _S)                                     \
    (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))

#define MIPS_CP0_64(_R, _S)                                     \
    (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))

#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
#define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
#define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
#define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
#define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
#define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)

static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
                                       int32_t *addr)
{
    struct kvm_one_reg cp0reg = {
        .id = reg_id,
        .addr = (uintptr_t)addr
    };

    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
}

static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
                                         target_ulong *addr)
{
    uint64_t val64 = *addr;
    struct kvm_one_reg cp0reg = {
        .id = reg_id,
        .addr = (uintptr_t)&val64
    };

    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
}

static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
                                         uint64_t *addr)
{
    struct kvm_one_reg cp0reg = {
        .id = reg_id,
        .addr = (uintptr_t)addr
    };

    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
}

static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
                                       int32_t *addr)
{
    struct kvm_one_reg cp0reg = {
        .id = reg_id,
        .addr = (uintptr_t)addr
    };

    return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
}

static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id,
                                         target_ulong *addr)
{
    int ret;
    uint64_t val64 = 0;
    struct kvm_one_reg cp0reg = {
        .id = reg_id,
        .addr = (uintptr_t)&val64
    };

    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
    if (ret >= 0) {
        *addr = val64;
    }
    return ret;
}

static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id,
                                         uint64_t *addr)
{
    struct kvm_one_reg cp0reg = {
        .id = reg_id,
        .addr = (uintptr_t)addr
    };

    return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
}

/*
 * We freeze the KVM timer when either the VM clock is stopped or the state is
 * saved (the state is dirty).
 */

/*
 * Save the state of the KVM timer when VM clock is stopped or state is synced
 * to QEMU.
 */
static int kvm_mips_save_count(CPUState *cs)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    CPUMIPSState *env = &cpu->env;
    uint64_t count_ctl;
    int err, ret = 0;

    /* freeze KVM timer */
    err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
    if (err < 0) {
        DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
        ret = err;
    } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
        count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
        err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
        if (err < 0) {
            DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
            ret = err;
        }
    }

    /* read CP0_Cause */
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
        ret = err;
    }

    /* read CP0_Count */
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
        ret = err;
    }

    return ret;
}

/*
 * Restore the state of the KVM timer when VM clock is restarted or state is
 * synced to KVM.
 */
static int kvm_mips_restore_count(CPUState *cs)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    CPUMIPSState *env = &cpu->env;
    uint64_t count_ctl;
    int err_dc, err, ret = 0;

    /* check the timer is frozen */
    err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
    if (err_dc < 0) {
        DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
        ret = err_dc;
    } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
        /* freeze timer (sets COUNT_RESUME for us) */
        count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
        err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
        if (err < 0) {
            DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
            ret = err;
        }
    }

    /* load CP0_Cause */
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
        ret = err;
    }

    /* load CP0_Count */
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
        ret = err;
    }

    /* resume KVM timer */
    if (err_dc >= 0) {
        count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
        err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
        if (err < 0) {
            DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
            ret = err;
        }
    }

    return ret;
}

/*
 * Handle the VM clock being started or stopped
 */
static void kvm_mips_update_state(void *opaque, int running, RunState state)
{
    CPUState *cs = opaque;
    int ret;
    uint64_t count_resume;

    /*
     * If state is already dirty (synced to QEMU) then the KVM timer state is
     * already saved and can be restored when it is synced back to KVM.
     */
    if (!running) {
        if (!cs->kvm_vcpu_dirty) {
            ret = kvm_mips_save_count(cs);
            if (ret < 0) {
                fprintf(stderr, "Failed saving count\n");
            }
        }
    } else {
        /* Set clock restore time to now */
        count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
        ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
                                     &count_resume);
        if (ret < 0) {
            fprintf(stderr, "Failed setting COUNT_RESUME\n");
            return;
        }

        if (!cs->kvm_vcpu_dirty) {
            ret = kvm_mips_restore_count(cs);
            if (ret < 0) {
                fprintf(stderr, "Failed restoring count\n");
            }
        }
    }
}

static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    CPUMIPSState *env = &cpu->env;
    int err, ret = 0;

    (void)level;

    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
                                 &env->CP0_Context);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
                                 &env->active_tc.CP0_UserLocal);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
                               &env->CP0_PageMask);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
                                 &env->CP0_BadVAddr);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
        ret = err;
    }

    /* If VM clock stopped then state will be restored when it is restarted */
    if (runstate_is_running()) {
        err = kvm_mips_restore_count(cs);
        if (err < 0) {
            ret = err;
        }
    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
                                 &env->CP0_EntryHi);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
                               &env->CP0_Compare);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
                                 &env->CP0_ErrorEPC);
    if (err < 0) {
        DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
        ret = err;
    }

    return ret;
}

static int kvm_mips_get_cp0_registers(CPUState *cs)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    CPUMIPSState *env = &cpu->env;
    int err, ret = 0;

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
                                 &env->CP0_Context);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
                                 &env->active_tc.CP0_UserLocal);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
                               &env->CP0_PageMask);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
                                 &env->CP0_BadVAddr);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
                                 &env->CP0_EntryHi);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
                               &env->CP0_Compare);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
        ret = err;
    }

    /* If VM clock stopped then state was already saved when it was stopped */
    if (runstate_is_running()) {
        err = kvm_mips_save_count(cs);
        if (err < 0) {
            ret = err;
        }
    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
        ret = err;
    }
    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
                                 &env->CP0_ErrorEPC);
    if (err < 0) {
        DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
        ret = err;
    }

    return ret;
}

int kvm_arch_put_registers(CPUState *cs, int level)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    CPUMIPSState *env = &cpu->env;
    struct kvm_regs regs;
    int ret;
    int i;

    /* Set the registers based on QEMU's view of things */
    for (i = 0; i < 32; i++) {
        regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i];
    }

    regs.hi = (int64_t)(target_long)env->active_tc.HI[0];
    regs.lo = (int64_t)(target_long)env->active_tc.LO[0];
    regs.pc = (int64_t)(target_long)env->active_tc.PC;

    ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);

    if (ret < 0) {
        return ret;
    }

    ret = kvm_mips_put_cp0_registers(cs, level);
    if (ret < 0) {
        return ret;
    }

    return ret;
}

int kvm_arch_get_registers(CPUState *cs)
{
    MIPSCPU *cpu = MIPS_CPU(cs);
    CPUMIPSState *env = &cpu->env;
    int ret = 0;
    struct kvm_regs regs;
    int i;

    /* Get the current register set as KVM seems it */
    ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);

    if (ret < 0) {
        return ret;
    }

    for (i = 0; i < 32; i++) {
        env->active_tc.gpr[i] = regs.gpr[i];
    }

    env->active_tc.HI[0] = regs.hi;
    env->active_tc.LO[0] = regs.lo;
    env->active_tc.PC = regs.pc;

    kvm_mips_get_cp0_registers(cs);

    return ret;
}

int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
                             uint64_t address, uint32_t data, PCIDevice *dev)
{
    return 0;
}

int kvm_arch_msi_data_to_gsi(uint32_t data)
{
    abort();
}
Commit	Line	Data
e2132e0b SL	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* KVM/MIPS: MIPS specific KVM APIs
	7	*
	8	* Copyright (C) 2012-2014 Imagination Technologies Ltd.
	9	* Authors: Sanjay Lal <[email protected]>
	10	*/
	11
c684822a	12	#include "qemu/osdep.h"
e2132e0b SL	13	#include <sys/ioctl.h>
	14	#include <sys/mman.h>
	15
	16	#include <linux/kvm.h>
	17
	18	#include "qemu-common.h"
	19	#include "qemu/error-report.h"
	20	#include "qemu/timer.h"
	21	#include "sysemu/sysemu.h"
	22	#include "sysemu/kvm.h"
	23	#include "cpu.h"
	24	#include "sysemu/cpus.h"
	25	#include "kvm_mips.h"
4c663752	26	#include "exec/memattrs.h"
e2132e0b SL	27
	28	#define DEBUG_KVM 0
	29
	30	#define DPRINTF(fmt, ...) \
	31	do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
	32
	33	const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
	34	KVM_CAP_LAST_INFO
	35	};
	36
	37	static void kvm_mips_update_state(void *opaque, int running, RunState state);
	38
	39	unsigned long kvm_arch_vcpu_id(CPUState *cs)
	40	{
	41	return cs->cpu_index;
	42	}
	43
b16565b3	44	int kvm_arch_init(MachineState ms, KVMState s)
e2132e0b SL	45	{
	46	/* MIPS has 128 signals */
	47	kvm_set_sigmask_len(s, 16);
	48
	49	DPRINTF("%s\n", __func__);
	50	return 0;
	51	}
	52
	53	int kvm_arch_init_vcpu(CPUState *cs)
	54	{
	55	int ret = 0;
	56
	57	qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
	58
	59	DPRINTF("%s\n", __func__);
	60	return ret;
	61	}
	62
	63	void kvm_mips_reset_vcpu(MIPSCPU *cpu)
	64	{
0e928b12 JH	65	CPUMIPSState *env = &cpu->env;
	66
	67	if (env->CP0_Config1 & (1 << CP0C1_FP)) {
	68	fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
	69	env->CP0_Config1 &= ~(1 << CP0C1_FP);
	70	}
	71
e2132e0b SL	72	DPRINTF("%s\n", __func__);
	73	}
	74
	75	int kvm_arch_insert_sw_breakpoint(CPUState cs, struct kvm_sw_breakpoint bp)
	76	{
	77	DPRINTF("%s\n", __func__);
	78	return 0;
	79	}
	80
	81	int kvm_arch_remove_sw_breakpoint(CPUState cs, struct kvm_sw_breakpoint bp)
	82	{
	83	DPRINTF("%s\n", __func__);
	84	return 0;
	85	}
	86
	87	static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
	88	{
	89	CPUMIPSState *env = &cpu->env;
	90
e2132e0b SL	91	return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
	92	}
	93
	94
	95	void kvm_arch_pre_run(CPUState cs, struct kvm_run run)
	96	{
	97	MIPSCPU *cpu = MIPS_CPU(cs);
	98	int r;
	99	struct kvm_mips_interrupt intr;
	100
4b8523ee JK	101	qemu_mutex_lock_iothread();
4b8523ee JK	102
e2132e0b SL	103	if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
	104	cpu_mips_io_interrupts_pending(cpu)) {
	105	intr.cpu = -1;
	106	intr.irq = 2;
	107	r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
	108	if (r < 0) {
	109	error_report("%s: cpu %d: failed to inject IRQ %x",
	110	__func__, cs->cpu_index, intr.irq);
	111	}
	112	}
4b8523ee JK	113
4b8523ee JK	114	qemu_mutex_unlock_iothread();
e2132e0b SL	115	}
e2132e0b SL	116
4c663752	117	MemTxAttrs kvm_arch_post_run(CPUState cs, struct kvm_run run)
e2132e0b	118	{
4c663752	119	return MEMTXATTRS_UNSPECIFIED;
e2132e0b SL	120	}
	121
	122	int kvm_arch_process_async_events(CPUState *cs)
	123	{
	124	return cs->halted;
	125	}
	126
	127	int kvm_arch_handle_exit(CPUState cs, struct kvm_run run)
	128	{
	129	int ret;
	130
	131	DPRINTF("%s\n", __func__);
	132	switch (run->exit_reason) {
	133	default:
	134	error_report("%s: unknown exit reason %d",
	135	__func__, run->exit_reason);
	136	ret = -1;
	137	break;
	138	}
	139
	140	return ret;
	141	}
	142
	143	bool kvm_arch_stop_on_emulation_error(CPUState *cs)
	144	{
	145	DPRINTF("%s\n", __func__);
	146	return true;
	147	}
	148
	149	int kvm_arch_on_sigbus_vcpu(CPUState cs, int code, void addr)
	150	{
	151	DPRINTF("%s\n", __func__);
	152	return 1;
	153	}
	154
	155	int kvm_arch_on_sigbus(int code, void *addr)
	156	{
	157	DPRINTF("%s\n", __func__);
	158	return 1;
	159	}
	160
	161	void kvm_arch_init_irq_routing(KVMState *s)
	162	{
	163	}
	164
	165	int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
	166	{
	167	CPUState *cs = CPU(cpu);
	168	struct kvm_mips_interrupt intr;
	169
	170	if (!kvm_enabled()) {
	171	return 0;
	172	}
	173
	174	intr.cpu = -1;
	175
	176	if (level) {
	177	intr.irq = irq;
	178	} else {
	179	intr.irq = -irq;
	180	}
	181
	182	kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
	183
184	return 0;
185	}
186
187	int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
188	{
189	CPUState *cs = current_cpu;
190	CPUState *dest_cs = CPU(cpu);
191	struct kvm_mips_interrupt intr;
192
193	if (!kvm_enabled()) {
194	return 0;
195	}
196
197	intr.cpu = dest_cs->cpu_index;
198
199	if (level) {
200	intr.irq = irq;
201	} else {
202	intr.irq = -irq;
203	}
204
205	DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
206
207	kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
208
209	return 0;
210	}
211
212	#define MIPS_CP0_32(_R, _S) \
5a2db896	213	(KVM_REG_MIPS_CP0 \| KVM_REG_SIZE_U32 \| (8 * (_R) + (_S)))
e2132e0b SL	214
e2132e0b SL	215	#define MIPS_CP0_64(_R, _S) \
5a2db896	216	(KVM_REG_MIPS_CP0 \| KVM_REG_SIZE_U64 \| (8 * (_R) + (_S)))
e2132e0b SL	217
	218	#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
	219	#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
	220	#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
	221	#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
	222	#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
	223	#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
	224	#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
	225	#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
	226	#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
	227	#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
	228	#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
	229	#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
	230	#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
461a1582	231	#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
e2132e0b SL	232	#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
e2132e0b SL	233
e2132e0b SL	234	static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
	235	int32_t *addr)
	236	{
e2132e0b SL	237	struct kvm_one_reg cp0reg = {
e2132e0b SL	238	.id = reg_id,
f8b3e48b	239	.addr = (uintptr_t)addr
e2132e0b SL	240	};
	241
	242	return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
	243	}
	244
	245	static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
	246	target_ulong *addr)
	247	{
	248	uint64_t val64 = *addr;
	249	struct kvm_one_reg cp0reg = {
	250	.id = reg_id,
	251	.addr = (uintptr_t)&val64
	252	};
	253
	254	return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
	255	}
	256
	257	static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
	258	uint64_t *addr)
	259	{
	260	struct kvm_one_reg cp0reg = {
	261	.id = reg_id,
	262	.addr = (uintptr_t)addr
	263	};
	264
	265	return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
	266	}
	267
	268	static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
	269	int32_t *addr)
	270	{
e2132e0b SL	271	struct kvm_one_reg cp0reg = {
e2132e0b SL	272	.id = reg_id,
f8b3e48b	273	.addr = (uintptr_t)addr
e2132e0b SL	274	};
e2132e0b SL	275
f8b3e48b	276	return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
e2132e0b SL	277	}
e2132e0b SL	278
182f42fd	279	static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id,
e2132e0b SL	280	target_ulong *addr)
	281	{
	282	int ret;
	283	uint64_t val64 = 0;
	284	struct kvm_one_reg cp0reg = {
	285	.id = reg_id,
	286	.addr = (uintptr_t)&val64
	287	};
	288
	289	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
	290	if (ret >= 0) {
	291	*addr = val64;
	292	}
	293	return ret;
	294	}
	295
182f42fd	296	static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id,
e2132e0b SL	297	uint64_t *addr)
	298	{
	299	struct kvm_one_reg cp0reg = {
	300	.id = reg_id,
	301	.addr = (uintptr_t)addr
	302	};
	303
	304	return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
	305	}
	306
	307	/*
	308	* We freeze the KVM timer when either the VM clock is stopped or the state is
	309	* saved (the state is dirty).
	310	*/
	311
	312	/*
	313	* Save the state of the KVM timer when VM clock is stopped or state is synced
	314	* to QEMU.
	315	*/
	316	static int kvm_mips_save_count(CPUState *cs)
	317	{
	318	MIPSCPU *cpu = MIPS_CPU(cs);
	319	CPUMIPSState *env = &cpu->env;
	320	uint64_t count_ctl;
	321	int err, ret = 0;
	322
	323	/* freeze KVM timer */
	324	err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
	325	if (err < 0) {
	326	DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
	327	ret = err;
	328	} else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
	329	count_ctl \|= KVM_REG_MIPS_COUNT_CTL_DC;
	330	err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
	331	if (err < 0) {
	332	DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
	333	ret = err;
	334	}
	335	}
	336
	337	/* read CP0_Cause */
	338	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
	339	if (err < 0) {
	340	DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
	341	ret = err;
	342	}
	343
	344	/* read CP0_Count */
	345	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
	346	if (err < 0) {
	347	DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
	348	ret = err;
	349	}
	350
	351	return ret;
	352	}
	353
	354	/*
	355	* Restore the state of the KVM timer when VM clock is restarted or state is
	356	* synced to KVM.
	357	*/
	358	static int kvm_mips_restore_count(CPUState *cs)
	359	{
	360	MIPSCPU *cpu = MIPS_CPU(cs);
361	CPUMIPSState *env = &cpu->env;
362	uint64_t count_ctl;
363	int err_dc, err, ret = 0;
364
365	/* check the timer is frozen */
366	err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
367	if (err_dc < 0) {
368	DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
369	ret = err_dc;
370	} else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
371	/* freeze timer (sets COUNT_RESUME for us) */
372	count_ctl \|= KVM_REG_MIPS_COUNT_CTL_DC;
373	err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
374	if (err < 0) {
375	DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
376	ret = err;
377	}
378	}
379
380	/* load CP0_Cause */
381	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
382	if (err < 0) {
383	DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
384	ret = err;
385	}
386
387	/* load CP0_Count */
388	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
389	if (err < 0) {
390	DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
391	ret = err;
392	}
393
394	/* resume KVM timer */
395	if (err_dc >= 0) {
396	count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
397	err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
398	if (err < 0) {
399	DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
400	ret = err;
401	}
402	}
403
404	return ret;
405	}
406
407	/*
408	* Handle the VM clock being started or stopped
409	*/
410	static void kvm_mips_update_state(void *opaque, int running, RunState state)
411	{
412	CPUState *cs = opaque;
413	int ret;
414	uint64_t count_resume;
415
416	/*
417	* If state is already dirty (synced to QEMU) then the KVM timer state is
418	* already saved and can be restored when it is synced back to KVM.
419	*/
420	if (!running) {
421	if (!cs->kvm_vcpu_dirty) {
422	ret = kvm_mips_save_count(cs);
423	if (ret < 0) {
424	fprintf(stderr, "Failed saving count\n");
425	}
426	}
427	} else {
428	/* Set clock restore time to now */
906b53a2	429	count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e2132e0b SL	430	ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
	431	&count_resume);
	432	if (ret < 0) {
	433	fprintf(stderr, "Failed setting COUNT_RESUME\n");
	434	return;
	435	}
	436
	437	if (!cs->kvm_vcpu_dirty) {
	438	ret = kvm_mips_restore_count(cs);
	439	if (ret < 0) {
	440	fprintf(stderr, "Failed restoring count\n");
	441	}
	442	}
	443	}
	444	}
	445
	446	static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
	447	{
	448	MIPSCPU *cpu = MIPS_CPU(cs);
	449	CPUMIPSState *env = &cpu->env;
	450	int err, ret = 0;
	451
	452	(void)level;
	453
	454	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
	455	if (err < 0) {
	456	DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
	457	ret = err;
	458	}
	459	err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
	460	&env->CP0_Context);
	461	if (err < 0) {
	462	DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
	463	ret = err;
	464	}
	465	err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
	466	&env->active_tc.CP0_UserLocal);
	467	if (err < 0) {
	468	DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
	469	ret = err;
	470	}
	471	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
	472	&env->CP0_PageMask);
	473	if (err < 0) {
	474	DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
	475	ret = err;
	476	}
	477	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
	478	if (err < 0) {
	479	DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
	480	ret = err;
	481	}
	482	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
	483	if (err < 0) {
	484	DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
	485	ret = err;
	486	}
	487	err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
	488	&env->CP0_BadVAddr);
	489	if (err < 0) {
	490	DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
	491	ret = err;
	492	}
	493
494	/* If VM clock stopped then state will be restored when it is restarted */
495	if (runstate_is_running()) {
496	err = kvm_mips_restore_count(cs);
497	if (err < 0) {
498	ret = err;
499	}
500	}
501
502	err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
503	&env->CP0_EntryHi);
504	if (err < 0) {
505	DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
506	ret = err;
507	}
508	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
509	&env->CP0_Compare);
510	if (err < 0) {
511	DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
512	ret = err;
513	}
514	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
515	if (err < 0) {
516	DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
517	ret = err;
518	}
519	err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
520	if (err < 0) {
521	DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
522	ret = err;
523	}
461a1582 JH	524	err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
	525	if (err < 0) {
	526	DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
	527	ret = err;
	528	}
e2132e0b SL	529	err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
	530	&env->CP0_ErrorEPC);
	531	if (err < 0) {
	532	DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
	533	ret = err;
	534	}
	535
	536	return ret;
	537	}
	538
	539	static int kvm_mips_get_cp0_registers(CPUState *cs)
	540	{
	541	MIPSCPU *cpu = MIPS_CPU(cs);
	542	CPUMIPSState *env = &cpu->env;
	543	int err, ret = 0;
	544
	545	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
	546	if (err < 0) {
	547	DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
	548	ret = err;
	549	}
	550	err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
	551	&env->CP0_Context);
	552	if (err < 0) {
	553	DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
	554	ret = err;
	555	}
	556	err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
	557	&env->active_tc.CP0_UserLocal);
	558	if (err < 0) {
	559	DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
	560	ret = err;
	561	}
	562	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
	563	&env->CP0_PageMask);
	564	if (err < 0) {
	565	DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
	566	ret = err;
	567	}
	568	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
	569	if (err < 0) {
	570	DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
	571	ret = err;
	572	}
	573	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
	574	if (err < 0) {
	575	DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
	576	ret = err;
	577	}
	578	err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
	579	&env->CP0_BadVAddr);
	580	if (err < 0) {
	581	DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
	582	ret = err;
	583	}
	584	err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
	585	&env->CP0_EntryHi);
	586	if (err < 0) {
	587	DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
	588	ret = err;
	589	}
	590	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
	591	&env->CP0_Compare);
	592	if (err < 0) {
593	DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
594	ret = err;
595	}
596	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
597	if (err < 0) {
598	DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
599	ret = err;
600	}
601
602	/* If VM clock stopped then state was already saved when it was stopped */
603	if (runstate_is_running()) {
604	err = kvm_mips_save_count(cs);
605	if (err < 0) {
606	ret = err;
607	}
608	}
609
610	err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
611	if (err < 0) {
612	DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
613	ret = err;
614	}
461a1582 JH	615	err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
	616	if (err < 0) {
	617	DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
	618	ret = err;
	619	}
e2132e0b SL	620	err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
	621	&env->CP0_ErrorEPC);
	622	if (err < 0) {
	623	DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
	624	ret = err;
	625	}
	626
	627	return ret;
	628	}
	629
	630	int kvm_arch_put_registers(CPUState *cs, int level)
	631	{
	632	MIPSCPU *cpu = MIPS_CPU(cs);
	633	CPUMIPSState *env = &cpu->env;
	634	struct kvm_regs regs;
	635	int ret;
	636	int i;
	637
	638	/* Set the registers based on QEMU's view of things */
	639	for (i = 0; i < 32; i++) {
02dae26a	640	regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i];
e2132e0b SL	641	}
e2132e0b SL	642
02dae26a JH	643	regs.hi = (int64_t)(target_long)env->active_tc.HI[0];
	644	regs.lo = (int64_t)(target_long)env->active_tc.LO[0];
	645	regs.pc = (int64_t)(target_long)env->active_tc.PC;
e2132e0b SL	646
	647	ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
	648
	649	if (ret < 0) {
	650	return ret;
	651	}
	652
	653	ret = kvm_mips_put_cp0_registers(cs, level);
	654	if (ret < 0) {
	655	return ret;
	656	}
	657
	658	return ret;
	659	}
	660
	661	int kvm_arch_get_registers(CPUState *cs)
	662	{
	663	MIPSCPU *cpu = MIPS_CPU(cs);
	664	CPUMIPSState *env = &cpu->env;
	665	int ret = 0;
	666	struct kvm_regs regs;
	667	int i;
	668
	669	/* Get the current register set as KVM seems it */
	670	ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
	671
	672	if (ret < 0) {
	673	return ret;
	674	}
	675
	676	for (i = 0; i < 32; i++) {
	677	env->active_tc.gpr[i] = regs.gpr[i];
	678	}
	679
	680	env->active_tc.HI[0] = regs.hi;
	681	env->active_tc.LO[0] = regs.lo;
	682	env->active_tc.PC = regs.pc;
	683
	684	kvm_mips_get_cp0_registers(cs);
	685
	686	return ret;
	687	}
9e03a040 FB	688
9e03a040 FB	689	int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca	690	uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 FB	691	{
	692	return 0;
	693	}
1850b6b7 EA	694
	695	int kvm_arch_msi_data_to_gsi(uint32_t data)
	696	{
	697	abort();
	698	}