[qemu.git] / target-cris / helper.c

/*
 *  CRIS helper routines.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "mmu.h"
#include "qemu/host-utils.h"


//#define CRIS_HELPER_DEBUG


#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if defined(CONFIG_USER_ONLY)

void cris_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;

    env->exception_index = -1;
    env->pregs[PR_ERP] = env->pc;
}

void crisv10_cpu_do_interrupt(CPUState *cs)
{
    cris_cpu_do_interrupt(cs);
}

int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
                              int mmu_idx)
{
    env->exception_index = 0xaa;
    env->pregs[PR_EDA] = address;
    cpu_dump_state(env, stderr, fprintf, 0);
    return 1;
}

#else /* !CONFIG_USER_ONLY */


static void cris_shift_ccs(CPUCRISState *env)
{
    uint32_t ccs;
    /* Apply the ccs shift.  */
    ccs = env->pregs[PR_CCS];
    ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
    env->pregs[PR_CCS] = ccs;
}

int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
                              int mmu_idx)
{
    D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
    struct cris_mmu_result res;
    int prot, miss;
    int r = -1;
    target_ulong phy;

    D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
    miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
                              rw, mmu_idx, 0);
    if (miss) {
        if (env->exception_index == EXCP_BUSFAULT) {
            cpu_abort(env,
                      "CRIS: Illegal recursive bus fault."
                      "addr=%x rw=%d\n",
                      address, rw);
        }

        env->pregs[PR_EDA] = address;
        env->exception_index = EXCP_BUSFAULT;
        env->fault_vector = res.bf_vec;
        r = 1;
    } else {
        /*
         * Mask off the cache selection bit. The ETRAX busses do not
         * see the top bit.
         */
        phy = res.phy & ~0x80000000;
        prot = res.prot;
        tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
                     prot, mmu_idx, TARGET_PAGE_SIZE);
        r = 0;
    }
    if (r > 0) {
        D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
              __func__, r, cpu->interrupt_request, address, res.phy,
              res.bf_vec, env->pc);
    }
    return r;
}

void crisv10_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ex_vec = -1;

    D_LOG("exception index=%d interrupt_req=%d\n",
          env->exception_index,
          cs->interrupt_request);

    assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
    switch (env->exception_index) {
    case EXCP_BREAK:
        /* These exceptions are genereated by the core itself.
           ERP should point to the insn following the brk.  */
        ex_vec = env->trap_vector;
        env->pregs[PRV10_BRP] = env->pc;
        break;

    case EXCP_NMI:
        /* NMI is hardwired to vector zero.  */
        ex_vec = 0;
        env->pregs[PR_CCS] &= ~M_FLAG_V10;
        env->pregs[PRV10_BRP] = env->pc;
        break;

    case EXCP_BUSFAULT:
        cpu_abort(env, "Unhandled busfault");
        break;

    default:
        /* The interrupt controller gives us the vector.  */
        ex_vec = env->interrupt_vector;
        /* Normal interrupts are taken between
           TB's.  env->pc is valid here.  */
        env->pregs[PR_ERP] = env->pc;
        break;
    }

    if (env->pregs[PR_CCS] & U_FLAG) {
        /* Swap stack pointers.  */
        env->pregs[PR_USP] = env->regs[R_SP];
        env->regs[R_SP] = env->ksp;
    }

    /* Now that we are in kernel mode, load the handlers address.  */
    env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
    env->locked_irq = 1;
    env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */

    qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
                  __func__, env->pc, ex_vec,
                  env->pregs[PR_CCS],
                  env->pregs[PR_PID],
                  env->pregs[PR_ERP]);
}

void cris_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ex_vec = -1;

    D_LOG("exception index=%d interrupt_req=%d\n",
          env->exception_index,
          cs->interrupt_request);

    switch (env->exception_index) {
    case EXCP_BREAK:
        /* These exceptions are genereated by the core itself.
           ERP should point to the insn following the brk.  */
        ex_vec = env->trap_vector;
        env->pregs[PR_ERP] = env->pc;
        break;

    case EXCP_NMI:
        /* NMI is hardwired to vector zero.  */
        ex_vec = 0;
        env->pregs[PR_CCS] &= ~M_FLAG_V32;
        env->pregs[PR_NRP] = env->pc;
        break;

    case EXCP_BUSFAULT:
        ex_vec = env->fault_vector;
        env->pregs[PR_ERP] = env->pc;
        break;

    default:
        /* The interrupt controller gives us the vector.  */
        ex_vec = env->interrupt_vector;
        /* Normal interrupts are taken between
           TB's.  env->pc is valid here.  */
        env->pregs[PR_ERP] = env->pc;
        break;
    }

    /* Fill in the IDX field.  */
    env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;

    if (env->dslot) {
        D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
              " ERP=%x pid=%x ccs=%x cc=%d %x\n",
              ex_vec, env->pc, env->dslot,
              env->regs[R_SP],
              env->pregs[PR_ERP], env->pregs[PR_PID],
              env->pregs[PR_CCS],
              env->cc_op, env->cc_mask);
        /* We loose the btarget, btaken state here so rexec the
           branch.  */
        env->pregs[PR_ERP] -= env->dslot;
        /* Exception starts with dslot cleared.  */
        env->dslot = 0;
    }
	
    if (env->pregs[PR_CCS] & U_FLAG) {
        /* Swap stack pointers.  */
        env->pregs[PR_USP] = env->regs[R_SP];
        env->regs[R_SP] = env->ksp;
    }

    /* Apply the CRIS CCS shift. Clears U if set.  */
    cris_shift_ccs(env);

    /* Now that we are in kernel mode, load the handlers address.
       This load may not fault, real hw leaves that behaviour as
       undefined.  */
    env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);

    /* Clear the excption_index to avoid spurios hw_aborts for recursive
       bus faults.  */
    env->exception_index = -1;

    D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
          __func__, env->pc, ex_vec,
          env->pregs[PR_CCS],
          env->pregs[PR_PID],
          env->pregs[PR_ERP]);
}

hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
{
    uint32_t phy = addr;
    struct cris_mmu_result res;
    int miss;

    miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
    /* If D TLB misses, try I TLB.  */
    if (miss) {
        miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
    }

    if (!miss) {
        phy = res.phy;
    }
    D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
    return phy;
}
#endif
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
81fdc5f8 TS	21	#include "cpu.h"
81fdc5f8 TS	22	#include "mmu.h"
1de7afc9	23	#include "qemu/host-utils.h"
81fdc5f8	24
d12d51d5 AL	25
	26	//#define CRIS_HELPER_DEBUG
	27
	28
	29	#ifdef CRIS_HELPER_DEBUG
	30	#define D(x) x
3f668b6c	31	#define D_LOG(...) qemu_log(__VA_ARGS__)
d12d51d5	32	#else
e62b5b13	33	#define D(x)
d12d51d5 AL	34	#define D_LOG(...) do { } while (0)
d12d51d5 AL	35	#endif
e62b5b13	36
81fdc5f8 TS	37	#if defined(CONFIG_USER_ONLY)
81fdc5f8 TS	38
97a8ea5a	39	void cris_cpu_do_interrupt(CPUState *cs)
81fdc5f8	40	{
97a8ea5a AF	41	CRISCPU *cpu = CRIS_CPU(cs);
	42	CPUCRISState *env = &cpu->env;
	43
21317bc2 AF	44	env->exception_index = -1;
21317bc2 AF	45	env->pregs[PR_ERP] = env->pc;
81fdc5f8 TS	46	}
81fdc5f8 TS	47
b21bfeea AF	48	void crisv10_cpu_do_interrupt(CPUState *cs)
	49	{
	50	cris_cpu_do_interrupt(cs);
	51	}
	52
a1170bfd	53	int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
97b348e7	54	int mmu_idx)
81fdc5f8	55	{
21317bc2 AF	56	env->exception_index = 0xaa;
	57	env->pregs[PR_EDA] = address;
	58	cpu_dump_state(env, stderr, fprintf, 0);
	59	return 1;
81fdc5f8 TS	60	}
81fdc5f8 TS	61
81fdc5f8 TS	62	#else /* !CONFIG_USER_ONLY */
81fdc5f8 TS	63
e62b5b13	64
a1170bfd	65	static void cris_shift_ccs(CPUCRISState *env)
e62b5b13	66	{
21317bc2 AF	67	uint32_t ccs;
	68	/* Apply the ccs shift. */
	69	ccs = env->pregs[PR_CCS];
	70	ccs = ((ccs & 0xc0000000) \| ((ccs << 12) >> 2)) & ~0x3ff;
	71	env->pregs[PR_CCS] = ccs;
e62b5b13 EI	72	}
e62b5b13 EI	73
21317bc2 AF	74	int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
21317bc2 AF	75	int mmu_idx)
81fdc5f8	76	{
259186a7	77	D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
21317bc2 AF	78	struct cris_mmu_result res;
	79	int prot, miss;
	80	int r = -1;
	81	target_ulong phy;
	82
	83	D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
	84	miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
	85	rw, mmu_idx, 0);
	86	if (miss) {
	87	if (env->exception_index == EXCP_BUSFAULT) {
	88	cpu_abort(env,
	89	"CRIS: Illegal recursive bus fault."
	90	"addr=%x rw=%d\n",
	91	address, rw);
	92	}
	93
	94	env->pregs[PR_EDA] = address;
	95	env->exception_index = EXCP_BUSFAULT;
	96	env->fault_vector = res.bf_vec;
	97	r = 1;
	98	} else {
	99	/*
	100	* Mask off the cache selection bit. The ETRAX busses do not
	101	* see the top bit.
	102	*/
	103	phy = res.phy & ~0x80000000;
	104	prot = res.prot;
	105	tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
	106	prot, mmu_idx, TARGET_PAGE_SIZE);
	107	r = 0;
	108	}
	109	if (r > 0) {
	110	D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
259186a7	111	__func__, r, cpu->interrupt_request, address, res.phy,
21317bc2 AF	112	res.bf_vec, env->pc);
	113	}
	114	return r;
81fdc5f8 TS	115	}
81fdc5f8 TS	116
b21bfeea	117	void crisv10_cpu_do_interrupt(CPUState *cs)
7a977356	118	{
b21bfeea AF	119	CRISCPU *cpu = CRIS_CPU(cs);
b21bfeea AF	120	CPUCRISState *env = &cpu->env;
21317bc2 AF	121	int ex_vec = -1;
	122
	123	D_LOG("exception index=%d interrupt_req=%d\n",
	124	env->exception_index,
259186a7	125	cs->interrupt_request);
21317bc2 AF	126
	127	assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
	128	switch (env->exception_index) {
	129	case EXCP_BREAK:
	130	/* These exceptions are genereated by the core itself.
	131	ERP should point to the insn following the brk. */
	132	ex_vec = env->trap_vector;
	133	env->pregs[PRV10_BRP] = env->pc;
	134	break;
	135
	136	case EXCP_NMI:
	137	/* NMI is hardwired to vector zero. */
	138	ex_vec = 0;
	139	env->pregs[PR_CCS] &= ~M_FLAG_V10;
	140	env->pregs[PRV10_BRP] = env->pc;
	141	break;
	142
	143	case EXCP_BUSFAULT:
	144	cpu_abort(env, "Unhandled busfault");
	145	break;
	146
	147	default:
	148	/* The interrupt controller gives us the vector. */
	149	ex_vec = env->interrupt_vector;
	150	/* Normal interrupts are taken between
	151	TB's. env->pc is valid here. */
	152	env->pregs[PR_ERP] = env->pc;
	153	break;
	154	}
	155
	156	if (env->pregs[PR_CCS] & U_FLAG) {
	157	/* Swap stack pointers. */
	158	env->pregs[PR_USP] = env->regs[R_SP];
	159	env->regs[R_SP] = env->ksp;
	160	}
	161
	162	/* Now that we are in kernel mode, load the handlers address. */
	163	env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
	164	env->locked_irq = 1;
	165	env->pregs[PR_CCS] \|= F_FLAG_V10; /* set F. */
	166
	167	qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	168	__func__, env->pc, ex_vec,
	169	env->pregs[PR_CCS],
	170	env->pregs[PR_PID],
	171	env->pregs[PR_ERP]);
7a977356 EI	172	}
7a977356 EI	173
97a8ea5a	174	void cris_cpu_do_interrupt(CPUState *cs)
81fdc5f8	175	{
97a8ea5a AF	176	CRISCPU *cpu = CRIS_CPU(cs);
97a8ea5a AF	177	CPUCRISState *env = &cpu->env;
21317bc2 AF	178	int ex_vec = -1;
21317bc2 AF	179
21317bc2 AF	180	D_LOG("exception index=%d interrupt_req=%d\n",
21317bc2 AF	181	env->exception_index,
259186a7	182	cs->interrupt_request);
21317bc2 AF	183
	184	switch (env->exception_index) {
	185	case EXCP_BREAK:
	186	/* These exceptions are genereated by the core itself.
	187	ERP should point to the insn following the brk. */
	188	ex_vec = env->trap_vector;
	189	env->pregs[PR_ERP] = env->pc;
	190	break;
	191
	192	case EXCP_NMI:
	193	/* NMI is hardwired to vector zero. */
	194	ex_vec = 0;
	195	env->pregs[PR_CCS] &= ~M_FLAG_V32;
	196	env->pregs[PR_NRP] = env->pc;
	197	break;
	198
	199	case EXCP_BUSFAULT:
	200	ex_vec = env->fault_vector;
	201	env->pregs[PR_ERP] = env->pc;
	202	break;
	203
	204	default:
	205	/* The interrupt controller gives us the vector. */
	206	ex_vec = env->interrupt_vector;
	207	/* Normal interrupts are taken between
	208	TB's. env->pc is valid here. */
	209	env->pregs[PR_ERP] = env->pc;
	210	break;
	211	}
	212
	213	/* Fill in the IDX field. */
	214	env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
	215
	216	if (env->dslot) {
	217	D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
	218	" ERP=%x pid=%x ccs=%x cc=%d %x\n",
	219	ex_vec, env->pc, env->dslot,
	220	env->regs[R_SP],
	221	env->pregs[PR_ERP], env->pregs[PR_PID],
	222	env->pregs[PR_CCS],
	223	env->cc_op, env->cc_mask);
	224	/* We loose the btarget, btaken state here so rexec the
	225	branch. */
	226	env->pregs[PR_ERP] -= env->dslot;
	227	/* Exception starts with dslot cleared. */
	228	env->dslot = 0;
	229	}
b41f7df0	230
21317bc2 AF	231	if (env->pregs[PR_CCS] & U_FLAG) {
	232	/* Swap stack pointers. */
	233	env->pregs[PR_USP] = env->regs[R_SP];
	234	env->regs[R_SP] = env->ksp;
	235	}
	236
	237	/* Apply the CRIS CCS shift. Clears U if set. */
	238	cris_shift_ccs(env);
	239
	240	/* Now that we are in kernel mode, load the handlers address.
	241	This load may not fault, real hw leaves that behaviour as
	242	undefined. */
	243	env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
	244
	245	/* Clear the excption_index to avoid spurios hw_aborts for recursive
	246	bus faults. */
	247	env->exception_index = -1;
	248
	249	D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	250	__func__, env->pc, ex_vec,
	251	env->pregs[PR_CCS],
	252	env->pregs[PR_PID],
	253	env->pregs[PR_ERP]);
81fdc5f8 TS	254	}
81fdc5f8 TS	255
a8170e5e	256	hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
81fdc5f8	257	{
21317bc2 AF	258	uint32_t phy = addr;
	259	struct cris_mmu_result res;
	260	int miss;
	261
	262	miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
	263	/* If D TLB misses, try I TLB. */
	264	if (miss) {
	265	miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
	266	}
	267
	268	if (!miss) {
	269	phy = res.phy;
	270	}
	271	D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
	272	return phy;
81fdc5f8 TS	273	}
81fdc5f8 TS	274	#endif